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Author SHA1 Message Date
Ian Romanick
8a6de2d973 brw/validate: Eliminate duplicate integer multiply validation 
I think two MRs must have crossed in the mail so to speak. Keep Caio's
formatting and error message, and keep my PRM quote.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
 2026-03-09 19:21:38 +00:00
Ian Romanick
64c60582b5 elk/algebraic: Don't optimize SEL.L.SAT or SEL.G.SAT 
shader-db:

Broadwell
total instructions in shared programs: 18607516 -> 18607530 (<.01%)
instructions in affected programs: 2095 -> 2109 (0.67%)
helped: 0 / HURT: 8

total cycles in shared programs: 955704436 -> 955702925 (<.01%)
cycles in affected programs: 34299 -> 32788 (-4.41%)
helped: 2 / HURT: 6

All Haswell and older platforms had similar results. (Haswell shown)
total instructions in shared programs: 16989200 -> 16989201 (<.01%)
instructions in affected programs: 461 -> 462 (0.22%)
helped: 0 / HURT: 1

total cycles in shared programs: 946537070 -> 946537035 (<.01%)
cycles in affected programs: 16378 -> 16343 (-0.21%)
helped: 1 / HURT: 0

Test: piglit!1100
Reported-by: Georg Lehmann
Fixes: ca675b73d3 ("i965/fs: Optimize saturating SEL.L(E) with imm val >= 1.0.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40284>
 2026-03-09 18:41:55 +00:00
Ian Romanick
6c6c6ce054 brw/algebraic: Don't optimize SEL.L.SAT or SEL.G.SAT 
This optimization was added in October 2013, and the error was only just
now discovered. Removing the SEL.G.SAT optimization affected zero
shader-db shaders, and it affected 9 fossil-db shaders for instruction
size only.

I haven't checked to see if any of the hurt shaders are helped by
!39987.

shader-db:

All Intel platforms had similar results. (Lunar Lake shown)
total instructions in shared programs: 17093041 -> 17093055 (<.01%)
instructions in affected programs: 2072 -> 2086 (0.68%)
helped: 0 / HURT: 8

total cycles in shared programs: 876739578 -> 876739154 (<.01%)
cycles in affected programs: 18946 -> 18522 (-2.24%)
helped: 2 / HURT: 6

fossil-db:

Lunar Lake
Totals:
Instrs: 906230557 -> 906240487 (+0.00%); split: -0.00%, +0.00%
CodeSize: 14498856128 -> 14499003168 (+0.00%); split: -0.00%, +0.00%
Send messages: 40667184 -> 40667205 (+0.00%); split: -0.00%, +0.00%
Cycle count: 104068494103 -> 104068561943 (+0.00%); split: -0.00%, +0.00%
Max live registers: 189570192 -> 189570204 (+0.00%); split: -0.00%, +0.00%
Max dispatch width: 48157648 -> 48157552 (-0.00%)
Non SSA regs after NIR: 139823587 -> 139823016 (-0.00%); split: -0.00%, +0.00%

Totals from 9172 (0.46% of 1985212) affected shaders:
Instrs: 10774709 -> 10784639 (+0.09%); split: -0.00%, +0.09%
CodeSize: 177868384 -> 178015424 (+0.08%); split: -0.08%, +0.17%
Send messages: 311154 -> 311175 (+0.01%); split: -0.00%, +0.01%
Cycle count: 232471392 -> 232539232 (+0.03%); split: -0.15%, +0.18%
Max live registers: 1243549 -> 1243561 (+0.00%); split: -0.00%, +0.01%
Max dispatch width: 196672 -> 196576 (-0.05%)
Non SSA regs after NIR: 509663 -> 509092 (-0.11%); split: -0.19%, +0.08%

Test: piglit!1100
Reported-by: Georg Lehmann
Fixes: ca675b73d3 ("i965/fs: Optimize saturating SEL.L(E) with imm val >= 1.0.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40284>
 2026-03-09 18:41:55 +00:00
Valentine Burley
827370d144 intel/ci: Document recent Intel flakes
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Not caused by the new kernel, these have been flaking for a while now.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
 2026-03-09 17:42:03 +00:00
Valentine Burley
64b7388bc2 etnaviv/ci: Switch CI-tron to gfx-ci/linux kernel 
We can now use the standard gfx-ci/linux v6.19.5 kernel for all etnaviv
jobs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
 2026-03-09 17:42:03 +00:00
Valentine Burley
68e0eb78d1 freedreno/ci: Switch sm8650 to gfx-ci/linux kernel 
Use the standard gfx-ci/linux v6.19.5 kernel for the a750 jobs on
sm8650-hdk.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
 2026-03-09 17:42:03 +00:00
Valentine Burley
31090dea4c ci: Update kernel to Linux 6.19.6 
The new kernel also fixes the previous issue in the virgl-traces job, but
sadly Xe regressed, so keep the 6.17 kernel in zink-anv-adl.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14161
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
 2026-03-09 17:42:03 +00:00
Valentine Burley
efd980aa15 ci/lava: Uprev lava-job-submitter 
The new version drops our internal timestamp handling since newer
gitlab-runner versions already provide native timestamp support.

It also prepares for future CI-tron support in gfx-ci/linux by appending
`noinitrd` and `initcall_blacklist=cdc_driver_init` to the kernel
cmdline, disabling the initramdisk and CDC Composite Device that CI-tron
needs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
 2026-03-09 17:42:03 +00:00
Valentine Burley
de7a584093 radeonsi/ci: Skip subgroups.arithmetic tests on Mendocino 
This is not caused by the new kernel, these tests have occasionally
timed out over the last couple of weeks.
Running them single-threaded didn't help.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
 2026-03-09 17:42:03 +00:00
Karmjit Mahil
72870051d8 zink: Fix incorrect assert checking for linear state format 
With `pres->format == PIPE_FORMAT_L8_UNORM` and
`state->format == PIPE_FORMAT_L8_SRGB` the assert is triggered.
We should be comparing the linear version of `state->format` since
we're only concerned about the physical memory layout here.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31717>
 2026-03-09 17:02:26 +00:00
Lionel Landwerlin
de29b88668 anv: fix pulling constant data in compute/mesh/task shaders
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Missing the accounting for the base offset.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15029
Fixes: 9f2215b480 ("anv/brw: remove push constant load emulation from the backend compiler")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40301>
 2026-03-09 16:25:43 +00:00
Lionel Landwerlin
e70bb86e1c anv: only go into buffer relocs after we've looked at all batches 
With the slab, anv_device_lookup_bo() will have anv_bo::map = NULL
while the seen_bbos will not and we want a host pointer for decoding.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40294>
 2026-03-09 15:50:51 +00:00
Alyssa Rosenzweig
edccd06a0b nir/lower_subgroups: fix boolean clustered reductions 
It is legal to have a cluster size larger than the subgroup/ballot size,
but our lowering would blow up in this case due to the nir_ishl_imm
overflowing in the lowering. Fortunately, this is easy to handle.

Fixes sub_group_clustered_reduce_logical_and()

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40224>
 2026-03-09 14:50:37 +00:00
Aitor Camacho
97756219c4 kk: Set command buffer state to 0 when reset
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nvk and hk were setting the state to 0, but we weren't which led to issues
with the state being carried over after resetting.

Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40193>
 2026-03-09 13:37:09 +00:00
Eric R. Smith
8521051cfa pco: fix a typo in the check for optimization looping
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The count isn't incremented anywhere else.

Signed-off-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Fixes: f1b24267d2 ("pco: rework nir processing and passes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40240>
 2026-03-09 11:27:27 +00:00
Pavel Ondračka
ce33f82f83 r300: disable clip-discard watermark for triangles
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Commit 0d4aa5f55f introduced the watermark to optimize the guardband
state changes and always computed new_distance as MAX2(distance,
watermark).

That is correct for point/line paths where distance > 0, but it keeps a
non-zero discard distance alive when the next draw sets distance = 0
(triangles). This leaks wide point/line clip-discard state into later
triangle draws and can clip away large parts of geometry (as observed in
Sauerbraten). Only apply the watermark when distance > 0 and reset it to
zero otherwise so triangle draws disable clip-discard as intended.

Fixes: 0d4aa5f55f ("r300: pop-free clipping")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14959
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40223>
 2026-03-09 10:18:51 +00:00
Samuel Pitoiset
8f10e2886c radv: dump the PS epilog in the GPU hang report 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40219>
 2026-03-09 09:53:27 +00:00
Samuel Pitoiset
4c7958ae6c radv: apply the 1D workgroup optimization for mesh/task shaders too 
Suggested-by: Georg Lehmann <dadschoorse@gmail.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40194>
 2026-03-09 09:29:35 +00:00
Samuel Pitoiset
3c4cb16159 radv: fix local invocation index for mesh/task and quad derivatives on GFX12 
It must be lowered.

This fixes
dEQP-VK.spirv_assembly.instruction.compute.compute_shader_derivatives.{mesh,task}.*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40194>
 2026-03-09 09:29:34 +00:00
Samuel Pitoiset
4428541c54 radv/meta: fix HTILE fixup after copying depth/stencil image copies 
Typo, it should be false because it's after the copy.

Fixes: 4f41818194 ("radv/meta: add a function to fixup HTILE metadata for copies on compute queue")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40270>
 2026-03-09 09:07:09 +00:00
Samuel Pitoiset
fff16a9748 radv: replace radv_sdma_surf by ac_sdma_surf 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
 2026-03-09 08:40:47 +00:00
Samuel Pitoiset
c40225e490 radv: tidy up radv_sdma_surf 
Adjust few things before replacing it by ac_sdma_surf.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
 2026-03-09 08:40:47 +00:00
Samuel Pitoiset
0616fd22a5 radv: simplify getting bpe for SDMA surfaces 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
 2026-03-09 08:40:46 +00:00
Samuel Pitoiset
9893ac3674 radv: remove unnecessary radv_sdma_surf::{blk_w,blk_h} 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
 2026-03-09 08:40:46 +00:00
Samuel Pitoiset
94acb7edd5 radv: simplify computing offset/extent of SDMA surfaces 
By computing in elements earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
 2026-03-09 08:40:45 +00:00
Samuel Pitoiset
5923a7b8c6 radv: use vk_image_buffer_copy_layout() for SDMA buf layout 
For consistency with non-SDMA paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
 2026-03-09 08:40:45 +00:00
Samuel Pitoiset
02d047099e radv: simplify 96-bit copies with SDMA 
By adjusting offset/extent earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
 2026-03-09 08:40:45 +00:00
Samuel Pitoiset
6f3b9a62b3 radv: remove redundant radv_sdma_surf::is_linear 
is_linear is never used for buffers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
 2026-03-09 08:40:44 +00:00
Samuel Pitoiset
dba9809e0c radv: remove redundant radv_sdma_surf::is_3d 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
 2026-03-09 08:40:44 +00:00
Samuel Pitoiset
1a00587c44 radv: fix a GPU hang with PS epilogs and secondary command buffers 
If the secondary changes the fragment output state and if the same
PS epilog used before ExecuteCommands() is re-bind immediately after
that call, the PS epilog state wouldn't be re-emitted.

Apply the same change for VS prologs, although the logic is slightly
different and the bug shouldn't occur. The whole logic of secondaries
should be completely rewritten because it's definitely not robust.

This fixes a GPU hang in Where Winds Meet, see
https://github.com/doitsujin/dxvk/issues/5436.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40221>
 2026-03-09 08:16:49 +00:00
Samuel Pitoiset
ac3fd06987 radv: always enable DISABLE_CONSERVATIVE_ZPASS_COUNTS on GFX11
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This might cause incorrect occlusion queries count.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40235>
 2026-03-09 07:26:25 +00:00
Kenneth Graunke
952bf55483 nir: Fix divergence of Intel URB input/output handle intrinsics
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Tessellation evaluation shaders have a single convergent URB handle
(for the common patch data) used by all lanes.  Every other stage's
IO handles have separate handles in each lane.

Thanks to Alyssa Rosenzweig for catching this bug.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40280>
 2026-03-09 02:38:59 +00:00
Connor Abbott
6e3d805735 freedreno: Rename afuc to QRisc
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In [1] the AQE is called the "Application QRisc Engine." Thus the real
name of afuc is QRisc. Rename everything.

[1] a698ebd321

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40287>
 2026-03-08 22:32:39 +00:00
Connor Abbott
554eec159b freedreno/afuc: Update cread/cwrite syntax in README 
We now print actual modifiers instead of mysterious flags. Remove the
remaining ones.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40287>
 2026-03-08 22:32:39 +00:00
Mel Henning
1371c53e6a nvk: Expose VK_KHR_depth_clamp_zero_one
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Promoted from EXT

Reviewed-By: Thomas H.P. Andersen <phomes@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39812>
 2026-03-08 17:16:26 -04:00
Mel Henning
8e2707950b nvk: Use the MME for cond rendering on Turing+
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We can avoid the stalls from subc switches by avoiding using the copy engine
during vkCmdBeginConditionalRenderingEXT. Implement this by loading the
cond render value using the MME, since the hardware doesn't have a
suitable 32-bit comparison itself.

This brings the Sascha Willems conditionalrender demo from
from 1661 to 8334 fps on my blackwell system with all meshes disabled.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40277>
 2026-03-08 17:31:32 +00:00
Mel Henning
905557ab31 nvk: Use SET_GLOBAL_RENDER_ENABLE 
This brings the Sascha Willems conditionalrender demo from
927 to 1661 fps on my blackwell system with all meshes disabled.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40277>
 2026-03-08 17:31:32 +00:00
Eric Engestrom
1c14a7f283 etnaviv/ci: fix expectation
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Fixes: 3c0aa7c633 ("etnaviv/ci: update expectations")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40286>
 2026-03-07 23:35:55 +00:00
Karol Herbst
65c5c4e1a1 nvk: run nir_opt_large_constants before nir_lower_load_const_to_scalar 
nir_opt_large_constants isn't able to deal with complex derefs and
nir_lower_load_const_to_scalar e.g. splits up vectors to scalars.

This prevented nir_opt_large_constants from extracting large constants
in shaders that e.g. use a array of vector constant table.

Totals:
CodeSize: 9460341008 -> 9443435056 (-0.18%); split: -0.20%, +0.02%
Number of GPRs: 47363466 -> 47300498 (-0.13%); split: -0.13%, +0.00%
SLM Size: 5409320 -> 1202912 (-77.76%)
Static cycle count: 6130972462 -> 6121193466 (-0.16%); split: -0.20%, +0.04%
Spills to reg: 184840 -> 184828 (-0.01%); split: -0.01%, +0.01%
Fills from reg: 223889 -> 223874 (-0.01%); split: -0.01%, +0.00%
Max warps/SM: 50637796 -> 50641540 (+0.01%); split: +0.01%, -0.00%

Totals from 32429 (2.79% of 1163204) affected shaders:
CodeSize: 824883920 -> 807977968 (-2.05%); split: -2.25%, +0.20%
Number of GPRs: 2413077 -> 2350109 (-2.61%); split: -2.61%, +0.00%
SLM Size: 4437016 -> 230608 (-94.80%)
Static cycle count: 1208715713 -> 1198936717 (-0.81%); split: -1.02%, +0.21%
Spills to reg: 11934 -> 11922 (-0.10%); split: -0.20%, +0.10%
Fills from reg: 14118 -> 14103 (-0.11%); split: -0.14%, +0.04%
Max warps/SM: 1035736 -> 1039480 (+0.36%); split: +0.37%, -0.01%

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14993
Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Tested-by: Thomas H.P. Andersen <phomes@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40282>
 2026-03-07 23:21:40 +00:00
Karol Herbst
faea742c3a nouveau/drm-shim: implement get_zcull_info 
Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Tested-by: Thomas H.P. Andersen <phomes@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40282>
 2026-03-07 23:21:40 +00:00
Lucas Fryzek
844c5a1ae6 lvp: Export -1 as sync fd 
If the gallium context does not support `native_fence_fd`, we can still
support sync fd export/import by exporting -1 as sync_fd in vulkan.

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40211>
 2026-03-07 22:21:13 +00:00
Lucas Fryzek
420b934494 lvp: Mark opaque FD and dmabuf as compatible is supported 
If dmabuf export is supported we can now mark them as compatible handle
types. Additionally we can always store the backed_fd for export.

v2 (zzyiwei): hide opaque fd compat with dmabuf export behind udmabuf

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40211>
 2026-03-07 22:21:13 +00:00
Yiwei Zhang
848da336dd lvp: hide import-only dmabuf support from zink 
Zink has assumed both import and export when dmabuf extension is
advertised, so lavapipe has to hide the extension for zink without
supporting both.

Together with the prior commit, now zink-on-lvp in the CI env without
udmabuf will no longer test against fake dmabuf support.

Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40211>
 2026-03-07 22:21:13 +00:00
Yiwei Zhang
5ab8c8a439 lvp: avoid advertising dmabuf support for kms_swrast 
Lavapipe relies on true udmabuf support for dmabuf export allocation.
This changes aligns the behavior with both llvmpipe_allocate_memory_fd
and llvmpipe_import_memory_fd.

Fixes: 7d0a631f20 ("llvmpipe: export dmabuf caps for kms_swrast")
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40211>
 2026-03-07 22:21:12 +00:00
Mel Henning
bfde63e4d8 driconf: force_vk_vendor on No Man's Sky + NVK
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Cc: mesa-stable
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40278>
 2026-03-07 15:55:08 +00:00
Georg Lehmann
406935c6fe radv: use nir_opt_fp_math_ctrl
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Foz-DB Navi21:
Totals from 10833 (9.63% of 112497) affected shaders:
Instrs: 10090308 -> 10043030 (-0.47%); split: -0.48%, +0.01%
CodeSize: 53681564 -> 53556756 (-0.23%); split: -0.25%, +0.01%
VGPRs: 511568 -> 511296 (-0.05%); split: -0.08%, +0.03%
SpillSGPRs: 2442 -> 2438 (-0.16%); split: -0.20%, +0.04%
Latency: 58989785 -> 58935280 (-0.09%); split: -0.18%, +0.09%
InvThroughput: 15142587 -> 15067217 (-0.50%); split: -0.52%, +0.02%
VClause: 200588 -> 200410 (-0.09%); split: -0.20%, +0.11%
SClause: 257273 -> 257262 (-0.00%); split: -0.20%, +0.19%
Copies: 741430 -> 741397 (-0.00%); split: -0.22%, +0.22%
Branches: 211023 -> 211020 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 491752 -> 491663 (-0.02%); split: -0.02%, +0.00%
PreVGPRs: 418558 -> 418089 (-0.11%); split: -0.12%, +0.01%
VALU: 7064149 -> 7017847 (-0.66%); split: -0.66%, +0.01%
SALU: 1227287 -> 1226639 (-0.05%); split: -0.13%, +0.07%
SMEM: 449268 -> 449343 (+0.02%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40098>
 2026-03-07 08:16:29 +01:00
Georg Lehmann
7c217e540c nir: add a pass to optimize fp_math_ctrl 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40098>
 2026-03-07 08:16:27 +01:00
Georg Lehmann
042ee8dafc panvk/ci: document new crashes on bifrost
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39987>
 2026-03-07 05:01:45 +00:00
Georg Lehmann
f474e9853e nir: add fp class analysis tests 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39987>
 2026-03-07 05:01:45 +00:00
Georg Lehmann
4885e5cf3a nir: remove more fsat using range analysis 
Foz-DB Navi48:
Totals from 3018 (3.65% of 82636) affected shaders:
MaxWaves: 69274 -> 69280 (+0.01%)
Instrs: 7165414 -> 7157581 (-0.11%); split: -0.12%, +0.01%
CodeSize: 38890212 -> 38823132 (-0.17%); split: -0.18%, +0.00%
VGPRs: 228672 -> 228624 (-0.02%)
Latency: 64789026 -> 64784877 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 11805156 -> 11802642 (-0.02%); split: -0.02%, +0.00%
VClause: 136900 -> 136886 (-0.01%); split: -0.03%, +0.02%
SClause: 150135 -> 150130 (-0.00%); split: -0.01%, +0.01%
Copies: 574690 -> 574894 (+0.04%); split: -0.03%, +0.06%
Branches: 187169 -> 187086 (-0.04%); split: -0.04%, +0.00%
PreSGPRs: 190074 -> 190067 (-0.00%); split: -0.00%, +0.00%
PreVGPRs: 189564 -> 189538 (-0.01%); split: -0.02%, +0.00%
VALU: 3955188 -> 3949411 (-0.15%); split: -0.15%, +0.00%
SALU: 1114659 -> 1114729 (+0.01%); split: -0.02%, +0.03%
SMEM: 231080 -> 231077 (-0.00%); split: -0.00%, +0.00%
VOPD: 116150 -> 116180 (+0.03%); split: +0.04%, -0.02%

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39987>
 2026-03-07 05:01:45 +00:00