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22564 commits

Author SHA1 Message Date
Ian Romanick
88e3a57605 Merge branch 'mesa_7_5_branch' into mesa_7_6_branch 
Conflicts:
	src/mesa/main/dlist.c
 2009-09-16 07:57:19 -07:00
Ian Romanick
2921a2555d intel: Deassociated drawables from private context struct in intelUnbindContext 
The generic DRI infrastructure makes sure that __DRIcontextRec::driDrawablePriv
and __DRIcontextRec::driReadablePriv are set to NULL after unbinding a
context.  However, the intel_context structure keeps cached copies of
these pointers.  If these cached pointers are not NULLed and the
drawable is actually destroyed after unbinding the context (typically
by way of glXDestroyWindow), freed memory will be dereferenced in
intelDestroyContext.

This should fix bug #23418.
 2009-09-16 07:39:58 -07:00
Zou Nan hai
76e836a41a i965: do a flush in clear, fix openarena render issue, 
fd.o bug# 23857
 2009-09-16 13:25:46 +08:00
Brian Paul
41fff1b9a1 mesa: compile glUniformMatrix() functions into display lists 
I believe this is the last of the shader-related functions that needed
display list treatment.
 2009-09-15 15:10:29 -06:00
Brian Paul
6681981fe1 mesa: implement more glUniform display list functions 2009-09-15 14:56:55 -06:00
Brian Paul
f42c66c138 mesa: compile glUniform4f() into display lists 
Note: there are more glUniform functions to compile...
 2009-09-15 14:37:45 -06:00
Brian Paul
81de9d68f7 mesa: compile glUseProgram/glUseProgramObjectARB into display lists 
Fixes bug 23746
 2009-09-15 14:37:45 -06:00
Ian Romanick
6c6fe0a704 Merge commit 'origin/mesa_7_5_branch' into mesa_7_6_branch 2009-09-15 13:13:35 -07:00
Ian Romanick
1f309c40b8 GLX: Complain when buggy applications call GLX 1.3 functions. 2009-09-15 13:12:22 -07:00
Brian Paul
5d526ed21a Merge branch 'mesa_7_5_branch' into mesa_7_6_branch 2009-09-15 09:45:18 -06:00
Brian Paul
ac3c8e3b53 glsl: added some link debug code (disabled) 2009-09-14 17:32:03 -06:00
Brian Paul
b8b774c775 glsl: remove extra #version directives from concatenated shader sources 
When we concatenate shaders to do our form of poor-man linking, if there's
multiple #version directives, preprocessing fails.  This change disables
the extra #version directives by changing the first two chars to //.

This should help with some Wine issues such as bug 23946.
 2009-09-14 17:24:25 -06:00
Vinson Lee
2729db8976 gallium: Add Mac OS to pipe/p_thread.h. 
Mac OS also has POSIX threads.
 2009-09-14 11:50:48 -06:00
Brian Paul
d81086a86b llvmpipe: asst fixes for 'make linux-llvmpipe' 2009-09-11 13:39:14 -06:00
Vinson Lee
0fa1692f14 mesa: raise GL_INVALID_ENUM not GL_INVALID_VALUE for glTexParamter errors 
Signed-off-by: Brian Paul <brianp@vmware.com>
 2009-09-11 08:04:37 -06:00
Pauli Nieminen
796c96de80 radeon: Remove structure allocation from iterator variable. 
dma_bo varaible is only used for iterating so allocating memory for it only
causes memory leaks.
 2009-09-11 01:29:07 +03:00
Brian Paul
4b1cbfcbe6 Merge branch 'mesa_7_5_branch' into mesa_7_6_branch 2009-09-10 15:40:26 -06:00
Brian Paul
9e6ae75cc8 intel: disable intel_stencil_drawpixels() for now 
It doesn't work reliably even when all the prerequisite checks are made.
 2009-09-10 15:34:34 -06:00
Brian Paul
3f4d776199 softpipe: minor indentation fix 2009-09-10 14:14:18 -06:00
Brian Paul
988db64119 softpipe: set dirty_render_cache in softpipe_clear() 
This fixes a bug seen when doing a glDrawPixels(GL_STENCIL_INDEX) right
after a glClear().  The check-for-flush test was failing because we
didn't set the dirty_render_cache flag in softpipe_clear().  So we saw
stale data when we mapped the stencil buffer.
 2009-09-10 14:11:41 -06:00
Ian Romanick
8fd4e4dfc3 Fix merge fail 
One of the conflicst from this merge was missed:

commit 0c309bb494
Merge: c6c44bf d27d659
Author: Brian Paul <brianp@vmware.com>
Date:   Wed Sep 9 08:33:39 2009 -0600
 2009-09-10 11:47:24 -07:00
Brian Paul
d78a196121 tgsi: use new tgsi_call_record to handle execution mask stacks 
This fixes some issues when "return"ing from nested loops/conditionals.
 2009-09-10 12:45:27 -06:00
Brian Paul
c5f8594aeb mesa: need to set all stencil bits to 0 before setting the 1 bits 
Plus, check for pixel transfer stencil index/offset.
 2009-09-10 12:45:27 -06:00
Ian Romanick
8398535331 Merge branch 'mesa_7_5_branch' into mesa_7_6_branch 
Conflicts:
	src/mesa/drivers/dri/intel/intel_context.c
 2009-09-10 11:24:56 -07:00
Eric Anholt
acfea5c705 i965: Fix relocation delta for WM surfaces. 
This was a regression in 0f328c90db.

Bug #23688
Bug #23254
(cherry picked from commit 5604b27b93)
 2009-09-10 11:22:56 -07:00
Zhenyu Wang
2dd3da3a4a intel: add B43 chipset support 
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>

Hopefully this will be one of the last cherry-picks.

(cherry picked from commit ca246dd186)
 2009-09-10 11:18:41 -07:00
Brian Paul
e9ba9ffc9a mesa: in texenvprogram code, only do saturation when really needed. 
For some env modes (like modulate or replace) we don't have to clamp
because we know the results will be in [0,1].
 2009-09-10 08:41:12 -06:00
Vinson Lee
23fefa031f gallium: Add PIPE_OS_APPLE back to auxiliary/util/u_time.h. 
Fixes typo from commit c6c44bf481.
 2009-09-10 08:40:16 -06:00
Pauli Nieminen
3d1324a66a radeon: Change debugging code to use macros instead of inline functions. 
Variadic functions can't be inlined which makes debugging to have quite large
function overead. Only aleternative method is to use variadic macros which are
inlined so compiler can optimize debugging to minimize overhead.
 2009-09-10 16:53:08 +03:00
Pauli Nieminen
e0f99b8268 radeon: Add more verbose error message for failed command buffer. 2009-09-09 18:31:52 +03:00
Brian Paul
0c309bb494 Merge branch 'mesa_7_5_branch' into mesa_7_6_branch 
Conflicts:

	Makefile
	configs/default
	progs/glsl/Makefile
	src/gallium/auxiliary/util/u_simple_shaders.c
	src/gallium/state_trackers/glx/xlib/xm_api.c
	src/mesa/drivers/dri/i965/brw_draw_upload.c
	src/mesa/drivers/dri/i965/brw_vs_emit.c
	src/mesa/drivers/dri/intel/intel_context.h
	src/mesa/drivers/dri/intel/intel_pixel.c
	src/mesa/drivers/dri/intel/intel_pixel_read.c
	src/mesa/main/texenvprogram.c
	src/mesa/main/version.h
 2009-09-09 08:33:39 -06:00
aljen
c6c44bf481 gallium: Added HaikuOS platform 2009-09-09 08:24:18 -06:00
Brian Paul
89a765e92b mesa: disable GL_LUMINANCE case in _mesa_meta_draw_pixels() 
Works around a bug found on i965.  See bug 23670.
 2009-09-09 08:23:14 -06:00
Brian Paul
42943a4cf9 mesa: bump version to 7.5.2 
I'm not 100% sure there'll be a 7.5.2 release, but just in case.
 2009-09-08 14:45:27 -06:00
Brian Paul
8de625c7cf i965: fix incorrect test for vertex position attribute 2009-09-08 12:21:42 -06:00
Eric Anholt
b2cba25f9e i965: Fix warnings in intel_pixel_read.c. 
(cherry picked from commit c80ce5ac90)
 2009-09-04 14:41:33 -07:00
Eric Anholt
cf820a045f intel: Also get the DRI2 front buffer when doing front buffer reading. 
(cherry picked from commit df70d3049a)
 2009-09-04 14:40:21 -07:00
Eric Anholt
2855ee82c6 intel: Update Mesa state before span setup in glReadPixels. 
We could have mapped the wrong set of draw buffers.  Noticed while looking
into a DRI2 glean ReadPixels issue.
(cherry picked from commit afc981ee46)
 2009-09-04 14:40:15 -07:00
Eric Anholt
04081a164c intel: Move intel_pixel_read.c to shared for use with i965. 
(cherry picked from commit dcfe0d66bf)
 2009-09-04 14:40:12 -07:00
Eric Anholt
1d1dfc96c4 i965: Add missing state dependency of sf_unit on _NEW_BUFFERS. 
(cherry picked from commit 99174e7630)
 2009-09-04 14:12:37 -07:00
Eric Anholt
a9504edee3 intel: Align cubemap texture height to its padding requirements. 
(cherry picked from commit a70e131584)
(cherry picked from commit 29e51c3872)
 2009-09-04 14:12:37 -07:00
Eric Anholt
945d34e88a intel: Align untiled region height to 2 according to 965 docs. 
This may or may not be required pre-965, but it doesn't seem unlikely, and
I'd rather be safe.
(cherry picked from commit b053474378)
 2009-09-04 14:12:36 -07:00
Eric Anholt
94d3b832cc i965: Fix source depth reg setting for FSes reading and writing to depth. 
For some IZ setups, we'd forget to account for the source depth register
being present, so we'd both read the wrong reg, and write output depth to
the wrong reg.

Bug #22603.
(cherry picked from commit f44916414e)
 2009-09-04 14:12:36 -07:00
Eric Anholt
8c764d5c34 i965: Respect CondSwizzle in OPCODE_IF. 
Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be
useful for the looping code.

Bug #18992
(cherry picked from commit 78c022acd0)
(cherry picked from commit 63d7a2f53f)
 2009-09-04 14:12:36 -07:00
Brian Paul
a0b7850f1d i965: asst clean-ups, etc in brw_vs_emit() 
(cherry picked from commit fd7d764514)
 2009-09-04 14:12:36 -07:00
Eric Anholt
3d6c73513c i965: Emit conditional code updates as required for GLSL VS if statements. 
Previously, we'd be branching based on whatever condition code happened to be
laying around.
(cherry picked from commit 7007f8b352)
 2009-09-04 14:12:36 -07:00
Eric Anholt
83e6c67363 i965: Spell "conditional" correctly. 2009-09-04 14:12:36 -07:00
Eric Anholt
f396263651 i965: Fix RECT shadow sampling by not losing the other texcoords. 
Bug #20821
(cherry picked from commit 191e028de2)
 2009-09-04 14:12:36 -07:00
Eric Anholt
63b3fa2bce i965: Assert that the offset in the VBO is below the VBO size. 
This avoids sending a bad buffer address to the GPU due to programmer error,
and is permitted by the ARB_vbo spec.  Note that we still have the opportunity
to dereference past the end of the GPU, because we aren't clipping to a
correct _MaxElement, but that appears to be harder than it should be.  This
gets us the 90% solution.

Bug #19911.
(cherry picked from commit d7430d942f)
 2009-09-04 14:12:36 -07:00
Eric Anholt
217af32c2d i965: Even if no VS inputs are set, still load some amount of URB as required. 
See comment on Vertex URB Entry Read Length for VS_STATE.

This, combined with the previous three commits, fixes #22945.
(cherry picked from commit e340d4f986)
 2009-09-04 14:12:35 -07:00