Commit graph

28104 commits

Author SHA1 Message Date
Eric Anholt
83b8ca58e1 vc4: Detect and report kernel support for branching. 2016-07-20 16:15:15 -07:00
Eric Anholt
16985eb308 vc4: Switch to using the libdrm-provided vc4_drm.h.
The required version is set to .69 for the getparam ioctl that will be
used in the next commit.
2016-07-20 16:15:15 -07:00
Tom Stellard
106946153f clover: Re-order includes in invocation.cpp to fix build
The build was failing because the official CL headers have a few defines,
like: # define cl_khr_gl_sharing 1

Which have the same name as some class members of clang's OpenCLOptions class.
If we include the cl headers first, this breaks the build because the member
names of this class are replaced by the literal 1.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
2016-07-20 21:15:53 +00:00
Tom Stellard
a73bf11a63 clover: Add missing include v2
clang commit r275822 removed unnecessary includes from header files,
so we now need to explicitly include clang/Lex/PreprocessorOptions.h

v2:
  - Use <> instead of "" for the include path.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
2016-07-20 21:15:53 +00:00
Tim Rowley
0f13a8f770 swr: [rasterizer core] introduce simd16intrin.h
Refactoring to leave existing simd_* intrinsics in "simdintrin.h" unchanged,
adding corresponding simd16_* intrinsics in "simd16intrin.h" on the side,
with emulation, that we can use piecemeal, rather than the all-or-nothing
approach to bring up avx512.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:15 -05:00
Tim Rowley
5fe361e2c0 swr: [rasterizer core] fix for possible int32 overflow condition
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:15 -05:00
Tim Rowley
a123d12e14 swr: [rasterizer core] rename *_MAX enum values to *_COUNT
Makes these names semantically correct.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:15 -05:00
Tim Rowley
e41d9dd576 swr: [rasterizer core] centroid correction
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:15 -05:00
Tim Rowley
e0529a4668 swr: [rasterizer core] support range of values in TemplateArgUnroller
Fixes Linux warnings.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:15 -05:00
Tim Rowley
0363015964 swr: [rasterizer core] ensure adjacent topologies use the cut-aware PA
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:15 -05:00
Tim Rowley
efdaf5fa3e swr: [rasterizer] attribute swizzling and linkage
Add support for enhanced attribute swizzling. Currently supports constant
source overrides to handle PrimitiveID support. No support yet for input
select swizzling or wrap shortest. Removes obsoleted linkageMask and
associated code.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:15 -05:00
Tim Rowley
a5846fb75a swr: [rasterizer common] icc declspec definitions
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:15 -05:00
Tim Rowley
0d13f2e801 swr: [rasterizer jitter] rework vertex/instance ID storage in fetch
Moved the setting into the existing component control code. Fixes bad
interaction between attribute/component setting for vertex/instance ID
and component packing.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:14 -05:00
Tim Rowley
1d09b3971a swr: [rasterizer core] avx512 simd utility work
Enabling KNOB_SIMD_WIDTH = 16 for AVX512 pre-work and low level simd utils

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:14 -05:00
Tim Rowley
98641f4e73 swr: [rasterizer core] viewport rounding for disabled scissor
Adjust viewport rounding when scissor rect is disabled during macro
tile scissor setup.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-07-20 10:22:14 -05:00
Tomasz Figa
70a28afb29 gallium/dri: Add shared glapi to LIBADD on Android
An earlier patch fixed the problem for classic drivers, however Gallium
was still left broken. This patch applies the same workaround to
Gallium, when compiled for Android. Following is a quote from the
original patch:

0cbc90c57c mesa: dri: Add shared glapi to LIBADD on Android

/system/vendor/lib/dri/*_dri.so actually depend on libglapi: without
this, loading the so file fails with:
cannot locate symbol "__emutls_v._glapi_tls_Context"

On non-Android (non-bionic) platform, EGL uses the following
workflow, which works fine:
  dlopen("libglapi.so", RTLD_LAZY | RTLD_GLOBAL);
  dlopen("dri/<driver>_dri.so", RTLD_NOW | RTLD_GLOBAL);

However, bionic does not respect the RTLD_GLOBAL flag, and the dri
library cannot find symbols in libglapi.so, so we need to link
to libglapi.so explicitly. Android.mk already does this.

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-07-20 15:10:33 +01:00
Józef Kucia
14608ef920 radeonsi: advertise 8 bits subpixel precision for viewport bounds
Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-07-20 12:45:31 +02:00
Józef Kucia
98aa807188 r600: advertise 8 bits subpixel precision for viewport bounds
Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-07-20 12:45:31 +02:00
Józef Kucia
3cd28fe3de gallium: add a cap for VIEWPORT_SUBPIXEL_BITS (v2)
This allows Gallium drivers to advertise the subpixel precision
for floating point viewports bounds.

v2:
  - Set ViewportSubpixelBits in st_init_limits.

Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-20 12:45:31 +02:00
Samuel Pitoiset
3c78d89692 nvc0: disable MS images on GM107+
MS images have to be handled explicitly and I don't plan to implement
them for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-20 11:11:33 +02:00
Samuel Pitoiset
8489f20689 nv50/ir: print OP_SUREDB subops in debug mode
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-20 11:11:30 +02:00
Samuel Pitoiset
1edc44bfd3 gm107/ir: add emission for SUREDx
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-20 11:11:26 +02:00
Samuel Pitoiset
4aaacd6dd0 gm107/ir: add emission for SUSTx and SULDx
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-20 11:11:21 +02:00
Samuel Pitoiset
e14cb05ce1 gm107/ra: fix constraints for surface operations
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-20 11:11:16 +02:00
Samuel Pitoiset
c68989b2c8 gm107/ir: lower surface operations
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-20 11:11:12 +02:00
Samuel Pitoiset
2ae4b5d622 nvc0: bind images for 3d/cp shaders on GM107+
On Maxwell, images binding is slightly different (and much better)
regarding Fermi and Kepler because a texture view needs to be uploaded
for each image and this is going to simplify the thing a lot.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-20 11:11:03 +02:00
Samuel Pitoiset
1da704a94c nvc0: increase the tex handles area size in the driver cb
Currently, we can store 32 tex handles of 32-bits integer each and
that fits perfectly with the underlying hardware except on GM107+
which requires to upload a texture view for each images.

This patch increases the number of storable texture handles in the
driver constant buffer from 32 to 40 because we expose 8 images.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-20 11:10:56 +02:00
Marek Olšák
0ab47146c9 winsys/amdgpu: use pb_cache buckets for fewer pb_cache misses
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-19 23:45:06 +02:00
Marek Olšák
dea6fdadca winsys/radeon: use pb_cache buckets for fewer pb_cache misses
This makes Bioshock Infinite with deferred flushing 2.2% faster.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-19 23:45:06 +02:00
Marek Olšák
8d5944199d gallium/pb_cache: reduce the number of pointer dereferences
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-19 23:45:06 +02:00
Marek Olšák
3cdc0e133f gallium/pb_cache: divide the cache into buckets for reducing cache misses
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-19 23:45:06 +02:00
Marek Olšák
fec7f74129 gallium/pb_cache: check parameters that are more likely to fail first
This makes Bioshock Infinite with deferred flushing 2% faster.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-19 23:45:06 +02:00
Marek Olšák
2596ae2b6e radeonsi: emit PS exports last
This effectively removes s_waitcnt instructions after FP16 exports.

Before:

    v_cvt_pkrtz_f16_f32_e32 v0, v0, v1   ; 5E000300
    v_cvt_pkrtz_f16_f32_e32 v1, v2, v3   ; 5E020702
    exp 15, 0, 1, 0, 0, v0, v1, v0, v0   ; F800040F 00000100
    s_waitcnt expcnt(0)                  ; BF8C0F0F
    v_cvt_pkrtz_f16_f32_e32 v0, v4, v5   ; 5E000B04
    v_cvt_pkrtz_f16_f32_e32 v1, v6, v7   ; 5E020F06
    exp 15, 1, 1, 0, 0, v0, v1, v0, v0   ; F800041F 00000100
    s_waitcnt expcnt(0)                  ; BF8C0F0F
    v_cvt_pkrtz_f16_f32_e32 v0, v8, v9   ; 5E001308
    v_cvt_pkrtz_f16_f32_e32 v1, v10, v11 ; 5E02170A
    exp 15, 2, 1, 0, 0, v0, v1, v0, v0   ; F800042F 00000100
    s_waitcnt expcnt(0)                  ; BF8C0F0F
    v_cvt_pkrtz_f16_f32_e32 v0, v12, v13 ; 5E001B0C
    v_cvt_pkrtz_f16_f32_e32 v1, v14, v15 ; 5E021F0E
    exp 15, 3, 1, 1, 1, v0, v1, v0, v0   ; F8001C3F 00000100
    s_endpgm                             ; BF810000

After:

    v_cvt_pkrtz_f16_f32_e32 v0, v0, v1   ; 5E000300
    v_cvt_pkrtz_f16_f32_e32 v1, v2, v3   ; 5E020702
    v_cvt_pkrtz_f16_f32_e32 v2, v4, v5   ; 5E040B04
    v_cvt_pkrtz_f16_f32_e32 v3, v6, v7   ; 5E060F06
    exp 15, 0, 1, 0, 0, v0, v1, v0, v0   ; F800040F 00000100
    v_cvt_pkrtz_f16_f32_e32 v4, v8, v9   ; 5E081308
    v_cvt_pkrtz_f16_f32_e32 v5, v10, v11 ; 5E0A170A
    exp 15, 1, 1, 0, 0, v2, v3, v0, v0   ; F800041F 00000302
    v_cvt_pkrtz_f16_f32_e32 v6, v12, v13 ; 5E0C1B0C
    v_cvt_pkrtz_f16_f32_e32 v7, v14, v15 ; 5E0E1F0E
    exp 15, 2, 1, 0, 0, v4, v5, v0, v0   ; F800042F 00000504
    exp 15, 3, 1, 1, 1, v6, v7, v0, v0   ; F8001C3F 00000706
    s_endpgm                             ; BF810000

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-19 23:45:06 +02:00
Marek Olšák
b2b45cecef radeonsi: set optimal settings in COMPUTE_RESOURCE_LIMITS
ported from Vulkan

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-19 23:45:06 +02:00
Marek Olšák
ad70c3954b radeonsi: really wait for the second EOP event and not the first one
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-19 23:45:06 +02:00
Marek Olšák
1a1cc67edd gallium/radeon: remove RADEON_FLUSH_KEEP_TILING_FLAGS flag
always set

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-19 23:45:06 +02:00
Samuel Pitoiset
9c63224540 gm107/ir: make use of ADD32I for all immediates
ADD only allows to emit 19-bits immediates.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
2016-07-19 18:07:15 +02:00
Samuel Pitoiset
0904a2ba97 gm107/ir: add missing NEG modifier for IADD32I
Like FADD32I, the NEG modifier of src0 is at position 56.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2016-07-19 18:07:10 +02:00
Andreas Boll
c482decd4d ddebug: Fix trivial typo in stderr message
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
2016-07-19 16:04:40 +02:00
Eric Engestrom
8ba46fbd9e vl: fix memory leak
CovID: 1363008
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-07-19 12:41:00 +02:00
Boyuan Zhang
60c7450f16 vl: add entry point
Add entrypoint to distinguish H.264 decode and encode. For example, in patch
5/11 when is calling "VaCreateContext", "pps" and "sps" shouldn't be allocated
for H.264 encoding. So we need to use the entry_point to determine this is
H.264 decode or H.264 encode. We can use config to determine the entrypoint
since config_id is passed to us for VaCreateContext call. However, for
VaDestoyContext call, only context_id is passed to us. So we need to know the
entrypoint in order to not free the pps/sps for encoding case.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-07-19 12:36:46 +02:00
Ilia Mirkin
ed9dd3bcd9 nv50,nvc0: srgb rendering is only available for rgba/bgra
Mark both L8_SRGB and L8A8_SRGB as non-renderable (the latter already
didn't have the bind flags). This makes the state tracker pick a
different format when rendering is required, or mark the fb as
incomplete. This fixes:

  bin/getteximage-formats init-by-clear-and-render -auto -fbo
  bin/getteximage-formats init-by-rendering -auto -fbo

which previously ran into srgb-encoding differences.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2016-07-18 20:04:17 -04:00
Ilia Mirkin
8e7893eb53 nvc0: add support for BGRA8 images
This is useful for pbo downloads, which are now accelerated with images.
BGRA8 is a moderately common format to do that in.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-07-18 20:04:17 -04:00
Christian König
3e1ad846f9 radeon/uvd: add session context buffer for polaris 10/11 v2
This way we have unlimited UVD sessions.

v2: only enable it when kernel supports it as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-18 17:13:17 +02:00
Leo Liu
134d6e4e4f vl/dri3: fix a memory leak from front buffer
Inspired by fix for mem leak of vdpau interop, resource_from_handle
set texture reference count, that need to be decreased and released,
recall there is a similar case for DRI3, that is with VA-API glx
extension, there is temporary TFP(texture from pixmap), we target it
through dma-buf. leak happens when without count down the reference.

Checked and found with mpv vo=opengl case, there only one static TFP,
the leak happens once, but for totem player using gstreamer VA-API glx,
the dynamic TFP for each frame, so leak quite a bit.

This fixes mem leak for mpv and totem.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-07-18 09:20:40 -04:00
Kenneth Graunke
ac1181ffbe compiler: Rename INTERP_QUALIFIER_* to INTERP_MODE_*.
Likewise, rename the enum type to glsl_interp_mode.

Beyond the GLSL front-end, talking about "interpolation modes" seems
more natural than "interpolation qualifiers" - in the IR, we're removed
from how exactly the source language specifies how to interpolate an
input.  Also, SPIR-V calls these "decorations" rather than "qualifiers".

Generated by:
$ find . -regextype egrep -regex '.*\.(c|cpp|h)' -type f -exec sed -i \
  -e 's/INTERP_QUALIFIER_/INTERP_MODE_/g' \
  -e 's/glsl_interp_qualifier/glsl_interp_mode/g' {} \;

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Dave Airlie <airlied@redhat.com>
2016-07-17 19:26:48 -07:00
Dave Airlie
e7d96e7685 virgl: drop pointless leftover init of virgl_transfer_inline_write.
Pointed out by Marek.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-07-17 06:20:53 +10:00
Ilia Mirkin
062c6b8e54 nv50: fix alphatest for non-blendable formats
The hardware can only do alphatest when using a blendable format. This
means that the various *16 norm formats didn't work with alphatest. It
appears that Talos Principle uses such formats, as well as alpha tests,
for some internal renders, which made them be incorrect. However this
does not appear to affect the final renders, but in a different game it
easily could.

The approach we take is that when alphatests are enabled and a suitable
format is used (which we anticipate is the vast minority of the time),
we insert code into the shader to perform the comparison and discard.
Once inserted, that code lives in the shader forever, and we re-upload
it each time the function changes with a fixed-up compare. To avoid
re-uploading too often, if we switch back to a blendable format, the
test is (effectively) disabled and the hw alphatest functionality is
used.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-16 11:45:30 -04:00
Rob Clark
44bbfedbd9 gallium/u_queue: add optional cleanup callback
Adds a second optional cleanup callback, called after the fence is
signaled.  This is needed if, for example, the queue has the last
reference to the object that embeds the util_queue_fence.  In this
case we cannot drop the ref in the main callback, since that would
result in the fence being destroyed before it is signaled.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-16 10:00:04 -04:00
Nicolai Hähnle
6f73c7595f radeonsi: remove the DRAW_PREAMBLE packet
According to firmware guys, the new sequence that we added for Polaris should
work on all CIK parts, and should actually be faster on some parts.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-16 13:02:37 +02:00