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gm107/ir: add emission for SUREDx

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Samuel Pitoiset 2016-06-24 22:35:59 +02:00
parent 4aaacd6dd0
commit 1edc44bfd3
1 changed files with 50 additions and 0 deletions
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50
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
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@ -205,6 +205,7 @@ private:
void emitSUHandle(const int s);
void emitSUSTx();
void emitSULDx();
void emitSUREDx();
};
/*******************************************************************************
@ -2913,6 +2914,51 @@ CodeEmitterGM107::emitSULDx()
emitSUHandle(1);
}
void
CodeEmitterGM107::emitSUREDx()
{
const TexInstruction *insn = this->insn->asTex();
uint8_t type = 0, subOp;
if (insn->subOp == NV50_IR_SUBOP_ATOM_CAS)
emitInsn(0xeac00000);
else
emitInsn(0xea600000);
if (insn->op == OP_SUREDB)
emitField(0x34, 1, 1);
emitSUTarget();
// destination type
switch (insn->dType) {
case TYPE_S32: type = 1; break;
case TYPE_U64: type = 2; break;
case TYPE_F32: type = 3; break;
case TYPE_S64: type = 5; break;
default:
assert(insn->dType == TYPE_U32);
break;
}
// atomic operation
if (insn->subOp == NV50_IR_SUBOP_ATOM_CAS) {
subOp = 0;
} else if (insn->subOp == NV50_IR_SUBOP_ATOM_EXCH) {
subOp = 8;
} else {
subOp = insn->subOp;
}
emitField(0x24, 3, type);
emitField(0x1d, 4, subOp);
emitGPR (0x14, insn->src(1));
emitGPR (0x08, insn->src(0));
emitGPR (0x00, insn->def(0));
emitSUHandle(2);
}
/*******************************************************************************
* assembler front-end
******************************************************************************/
@ -3235,6 +3281,10 @@ CodeEmitterGM107::emitInstruction(Instruction *i)
case OP_SULDP:
emitSULDx();
break;
case OP_SUREDB:
case OP_SUREDP:
emitSUREDx();
break;
default:
assert(!"invalid opcode");
emitNOP();