Commit graph

510 commits

Author SHA1 Message Date
Hyunjun Ko
d5f8265e05 intel/genxml: add a command VD_CONTROL_STATE to gen12/125
It's essentially needed to execute hevc decoding on gen12.

Note that we set HCP by default.
 - Command OpCode : VDENC(1), HCP(7), AVP(3)
 - SubOpcode      : HCP(10), VDENC(11)

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
2023-05-19 06:15:01 +00:00
Hyunjun Ko
27dcd18210 intel/genxml: align some fields on gen9/11/12/125 with media driver.
Most of them are length of each instruction and the rest are
some corrections on specific gens.

v1. Added a default value to DWordLength of each instruction.
( Lionel Landwerlin <lionel.g.landwerlin@intel.com> )

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
2023-05-19 06:15:01 +00:00
Hyunjun Ko
b3a1a8c617 intel/genxml: conform some fields to each other gen.
There are same fields across gens but the existing xmls are not exactly same,
which needs to be fixed.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
2023-05-19 06:15:01 +00:00
Hyunjun Ko
44bc651aba intel/genxml: fix num bits of some MOCS fields
Actually the first bit is a bit of protected mask (or reserved)
and the next 6 bits are for MOCS but they are being handled together
currently in isl_device_setup_mocs. So we need to fix some MOCS fields
defined as 6 bits to 7 bits.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
2023-05-19 06:15:01 +00:00
Rohan Garg
3b6dbf8902 intel/genxml: Add the preferred slm size enum for gen125
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>
2023-04-06 10:54:46 +00:00
Anuj Phogat
606a39f9d1 intel/genxml/125: Add preferred SLM allocation size field
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>
2023-04-06 10:54:46 +00:00
Dave Airlie
f85b2cbe33 anv/video: fix chroma qp to be a integer value.
This is just a cleanup to the genxml

Fixes: 98c58a16ef ("anv: add initial video decode support for h264.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21433>
2023-03-14 07:32:00 +00:00
Lionel Landwerlin
42e8a2c1d6 genxml: fix border color offset field on Gfx12+
I wonder if the docs are correct for Gfx11 because this is the
generation that gave us the Bindless Sampler Heap of 4Gb. So it would
make sense that the border colors can also be placed anywhere in that
4Gb heap.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21600>
2023-03-01 08:45:11 +00:00
Lionel Landwerlin
58b687d77b genxml: Fix STATE_BASE_ADDRESS::BindlessSurfaceStateSize field size
BSpec 44507

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21600>
2023-03-01 08:45:11 +00:00
Dave Airlie
bff627142d intel/genxml: add missing power well control bits
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20782>
2023-02-08 02:56:28 +00:00
Dave Airlie
cfc62802f8 intel/genxml: align some of the fields with the media driver
These values are taking from runtime interrogation of the media driver.

It would be nice to know if they are correct, but they work.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20782>
2023-02-08 02:56:28 +00:00
José Roberto de Souza
eb9ab4efeb intel/genxml/gen125: Tune 3DSTATE_WM Walker direction
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21105>
2023-02-07 07:34:44 -08:00
José Roberto de Souza
bea93f7058 intel/genxml/gen125: Add walker configuration fields to 3DSTATE_WM
Setting default expected values as default in the xml.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21105>
2023-02-07 07:34:35 -08:00
Tapani Pälli
0813c1a6fa intel/genxml: set unused 3DSTATE_PS_EXTRA field as mbz
Wa_14015360517 mentions situations where HW produces invalid
occlusion query results when "Pixel Shader Does not write to RT"
bit is set.

"When Pixel Shader Kills Pixel is set, SW must perform a dummy render
 target write from the shader and not set this bit, so that Occlusion
 Query is correct."

Another situation is when writing to UAV or to NULL render target.
Patch sets field as 'must be zero' to discourage possible use of it.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20849>
2023-01-24 10:28:15 +00:00
Kenneth Graunke
ebdf6a7926 intel/genxml: Drop CACHE_MODE_SS definition.
This is a global register which isn't settable by userspace contexts.
It also shouldn't appear in any of our aubinator decodes from error
states or aub dumps, as no userspace batch should be setting it.

So it's not very valuable to have here.  Just makes us think we can
set it.  Plus, a lot of the field definitions changed a bunch, and
would need updating.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20627>
2023-01-12 21:48:40 +00:00
José Roberto de Souza
def474e916 intel/genxml/gen12.5: Pipe_Control::Remove Global Snapshot Count Reset
It was not meant to be used(Iris have assert for it) and it was
removed from Pipe_Control instruction in gen12.5 and newer.

BSpec: 47112
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20444>
2022-12-29 08:34:25 -08:00
Tapani Pälli
910f5a18cf intel/genxml: add disable preemption field for gen125
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20438>
2022-12-27 15:53:42 +00:00
Nanley Chery
2add57d0c2 intel: Hook up RENDER_SURFACE_STATE::DecompressInL3
The sampler's decompressor seems to lack support for some types of
format re-interpretation. Use the more capable decompressor for these
cases. This will be needed to avoid regressing piglit's
arb_texture_view-rendering-formats in later commits.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19937>
2022-12-14 03:05:24 +00:00
Lionel Landwerlin
971e07361a genxml: add gen12/12.5 CS prefetch disable bits
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20295>
2022-12-13 19:22:02 +00:00
Jason Ekstrand
9859413bf4 intel/genxml: Add 3DPRIMITIVE_EXTENDED opcodes on Gen11+
On Gen11 and above, the 3DPRIMITIVE command takes an optional additional
three DWORDs of data as "extended parameters".  These extended
parameters only exist in the packet if "Extended Parameters Present" is
set.  Because our packing code doesn't handle variable-length commands
well, this commit adds a second version of the command which isn't real
but is just a copy of 3DPRIMITIVE with the additional dwords where the
"Extended Parameters Present" defaults to true and "DWord Length" is
adjusted by 3 as needed.  The 3DPRIMITIVE command is then the gen4-9
version which still works fine but doesn't have the new parameters.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20295>
2022-12-13 19:22:02 +00:00
Jason Ekstrand
781a16382d intel/genxml: Make some fields Booleans
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20295>
2022-12-13 19:22:02 +00:00
Jordan Justen
0d9be82fe6 intel/genxml: Add genX_rt_pack.h
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20225>
2022-12-09 01:43:39 +00:00
Lionel Landwerlin
675c5bd4cc anv: refactor ray tracing dispatch
Preparing for vkCmdTraceRaysIndirect2KHR

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20011>
2022-12-02 09:28:23 +00:00
Lionel Landwerlin
7d7c32de4c anv/genxml: make gen_rt more like other genxml files
The main goal is to be able to generate genX_bits.h for those
structures so we can get generated field offsets.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20011>
2022-12-02 09:28:23 +00:00
Lionel Landwerlin
1d9608be1a genxml: forbid usage of L1CC_WBP/L1CC_UC for stateless messages
We want to avoid those settings so that we do not have to emit a tile
fence to implement Wa_22013689345.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19322>
2022-11-23 06:54:04 +00:00
Marcin Ślusarz
11612d81b7 intel/genxml: fix width of 3DSTATE_TASK_CONTROL.MaximumNumberofThreadGroups
Fixes: 3567d47f3e ("intel/genxml: Inline the BODY structs into the instructions")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19412>
2022-11-02 08:56:53 +00:00
Nanley Chery
0fa540ef61 iris: Reduce use of RHWO optimization (Wa_1508744258)
Implement Wa_1508744258:

   Disable RHWO by setting 0x7010[14] by default except during resolve
   pass.

Disable the RCC RHWO optimization at all times except when resolving
single sampled color surfaces. MCS partial resolves are done via
software (i.e., not via a HW bit) and so are not expected to need this
workaround.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19360>
2022-10-31 23:26:06 +00:00
Dylan Baker
3395b40b37 intel/genxml: use Path.replace instead of unlink and rename
Suggested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
2022-10-12 10:59:15 -07:00
Dylan Baker
ede03c99db intel/genxml: use a main() function
So we have less stuff in the global namespace

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
2022-10-12 10:59:12 -07:00
Dylan Baker
0ac3b6f671 intel/genxml: split the processing code up
Instead of crewating output or validating in the process code, just
process, then let main handle the rest

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
2022-10-12 10:59:09 -07:00
Dylan Baker
8c8a1966ab intel/genxml: reprocess xml with elementree output
This makes two relatively small changes, first it addes the encoding to
the xml delcaration, and switches the quote style. Second, it changes
the final newline. These seemed minor enough to not warrent patches to
make the old wrter do the same thing as the new writer.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
2022-10-12 10:59:06 -07:00
Dylan Baker
9a185d78ca intel/genxml: use ElementTree.write and .indent
This removes a bunch of hand-written code, and allows for fewer corner
cases. The resulting code has some minor differences (no empty newlines
and the encoding is declared in the xml declaration)

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
2022-10-12 10:59:03 -07:00
Dylan Baker
b876f4daa9 intel/genxml: re-process with extra whitespace removed
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
2022-10-12 10:59:01 -07:00
Dylan Baker
db8c6590e0 intel/genxml: remove newlines between xml islands
When we move to using etree to print this it won't have them, so this
minimizes the diff further.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
2022-10-12 10:58:58 -07:00
Dylan Baker
9acd459bee intel/genxml: re-process with space before />
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
2022-10-12 10:58:56 -07:00
Dylan Baker
b150b89e61 intel/genxml: write a space before the '/>` closing tag
ElementTree.write will do this, and we want to minimize the diff when we
switch from our own writer to the builtin one.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
2022-10-12 10:58:49 -07:00
Tapani Pälli
1cf1a94f97 intel: revert preemption disable via VFG changes
This register will not be whitelisted and this change will be
done in kernel instead.

This change reverts commits d5d4604a, ddcd6b38, 27c5b93d.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18897>
2022-10-04 10:38:49 +00:00
Dylan Baker
1f0a0a46d9 meson: run genxml sort tests
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Dylan Baker
3f0da1bbfa intel/genxml: run gen_sort_tags on all of the xml
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Dylan Baker
106da29196 intel/genxml: add a validation mode to gen_sort_tags
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Dylan Baker
1386fd6a7b intel/genxml: add 'nonzero' to gen_sort_tags
which was added in ebe2a2b5f6.

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Dylan Baker
92857fd5c9 intel/genxml: don't overwrite the input of gen_sort_tags in place
otherwise we can be left with garbage

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Dylan Baker
c0aeeb93a8 intel/genxml: remove unused variable in gen_sort_tags.py
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Dylan Baker
27d89a673d intel/genxml: use a not in {x, y} instead of a != x or a != y
It's faster, less code, and more idiomatic

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Dylan Baker
4fd2e15855 intel/genxml: add type annotations to gen_sort_tags.py
let static analysis help us out

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Dylan Baker
3f9fe21988 intel/genxml: don't use parens with python assert statement
assert is a statement in python, not a function. Useing parens with it
leads to madness, because assert takes two arguments in the form `assert
expression: bool, message: str`. With parens though it's tempting to
write `assert(expression, message)`, which results in an assert that is
*always* true, because a non-empty tuple (which is what is written) is
*never* false.

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Dylan Baker
f286451ada intel/genxml: use a set for lookups
Python will pre-compute the set since it's const, and the performance of
a set search is significantly better than that of a list search

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Dylan Baker
e04ece53d7 intel/genxml: use a single pattern for res
regex is expensive, do less of it.

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
2022-10-01 14:03:49 -07:00
Kenneth Graunke
98bd984977 intel/genxml: Add XY_FAST_COLOR_BLT
We'll need to use this for VkCmdFillBuffer on transfer queues.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183>
2022-09-28 08:41:35 +00:00
Jason Ekstrand
5814436159 anv: Set up the memory-backed FIFO buffer
v2: Fix incorrect goto (Caio)
    Comment 3DSTATE_BTD programming (Caio)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
2022-09-28 05:38:36 +00:00