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Author SHA1 Message Date
Andres Gomez
81149c8f52 docs: add news item and link release notes for 17.0.5 
Signed-off-by: Andres Gomez <agomez@igalia.com>
 2017-04-29 01:21:17 +03:00
Andres Gomez
e06aec99f2 docs: add sha256 checksums for 17.0.5 
Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 6cb65ce2d3)
 2017-04-29 01:20:51 +03:00
Andres Gomez
0ad8c4f375 docs: add release notes for 17.0.5 
Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 61b134a862)
 2017-04-29 01:19:51 +03:00
Marek Olšák
7a515a607c radeonsi: don't load unused compute shader input SGPRs and VGPRs 
Basically, don't load GRID_SIZE or BLOCK_SIZE if they are unused, determine
whether to load BLOCK_ID for each component separately, and set the number
of THREAD_ID VGPRs to load. Now we should get the maximum CS launch wave
rate in most cases.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:57:44 +02:00
Marek Olšák
46e48d4044 tgsi/scan: record compute shader system value usage 
v2: just do indexing with swizzle[i]

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
fa15436e63 radeonsi: add a HUD query for draw calls with primitive restart 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
55445ff189 radeonsi: tell LLVM not to remove s_barrier instructions 
LLVM 5.0 removes s_barrier instructions if the max-work-group-size
attribute is not set. What a surprise.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
0490074cab radeonsi: fix tess offchip offset for per-patch attributes 
We need 4 more bits there. I don't know what is fixed by this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
4e50062028 radeonsi: pass tessellation ring addresses via user SGPRs 
This removes s_load_dword latency for tess rings.

We need just 1 SGPR for the address if we use 64K alignment. The final asm
for recreating the descriptor is:

    // s2 is (address >> 16)
    s_mov_b32 s3, 0
    s_lshl_b64 s[4:5], s[2:3], 16
    s_mov_b32 s6, -1
    s_mov_b32 s7, 0x27fac

v2: bitcast the descriptor type from v2i64 to v4i32

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
2823e15f60 radeonsi: use si_insert_input_ret in si_llvm_emit_tcs_epilogue 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
9fd9a7d0ba radeonsi: remove VS epilog code, compile VS with PrimID export on demand 
The use of PrimID in the pixel shader is too rare to deserve such
a sizable support code.

The initial idea of the VS epilog was to move the clipping code there and
remove it based on states, but optimized variants are now used to do that
and are easier to support, so the VS epilog has turned out to be not so
useful.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
3b2e93e472 radeonsi: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3 
VGPR1 = InstanceID / StepRate0; // StepRate0 can be set to 1

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
678d568c7b radeonsi: don't load PrimID in TES if it's not used 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
808c33f6f0 radeonsi: explain (non-)monolithic shaders 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
fc478248f3 radeonsi/gfx9: enable OpenGL 4.5 
Tentatively enable it, expecting the scratch buffer support to be done before
the next Mesa release.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
ed9a51cd3b radeonsi/gfx9: 2nd shader of merged shaders should hold a reference of the 1st 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
ef40937854 radeonsi: add reference counting for shader selectors 
The 2nd shader of merged shaders should take a reference of the 1st shader.
The next commit will do that.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
6c15e15af4 radeonsi/gfx9: set VGT_VERTEX_REUSE for ES in ES-GS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
887ef1de34 radeonsi/gfx9: set TES registers for merged ES-GS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
49cd0cbfd5 radeonsi/gfx9: disallow scratch buffer for LS-HS and ES-GS 
not implemented yet

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
2857b14bba radeonsi/gfx9: always compile monolithic ES-GS (asynchronously) 
In addition to the non-monolithic variant.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
a82398a8f5 radeonsi/gfx9: add support for monolithic ES-GS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
6a9c20fdd5 radeonsi/gfx9: make sure the 1st shader's main part exists for merged shaders 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
7df682c291 radeonsi/gfx9: select shader parts for non-monolithic ES-GS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
cd99c442c4 radeonsi/gfx9: add GS prolog support for merged ES-GS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
e0570bc283 radeonsi/gfx9: add VS prolog support for merged ES-GS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
6b93452b24 radeonsi/gfx9: pass GS input SGPRs and VGPRs from the ES part to GS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
37e22ab65e radeonsi/gfx9: store ES outputs to LDS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
d616c57342 radeonsi/gfx9: load GS inputs from LDS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
fc781fa0ab radeonsi/gfx9: get GS wave ID from the correct input 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
bcaf905129 radeonsi/gfx9: add the function signature of merged ES-GS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
8b220877ad radeonsi/gfx9: set registers and shader key for merged ES-GS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
ab197ad8d1 radeonsi/gfx9: add GS user SGPRs 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
b2f5d03152 radeonsi: rename declare_tess_lds -> declare_lds_as_pointer 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
e3caa1cd36 radeonsi: simplify some shader type conditions 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
021e65640e radeonsi: rename the swizzle parameter of lds_store 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
dcea7e5d19 radeonsi: add si_shader::prolog2 
For a GS prolog in merged ES-GS.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
eb35238ffe radeonsi/gfx9: move RW_BUFFERS to s[0:1] for merged shaders 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
0af00f179e radeonsi/gfx9: add support for monolithic merged LS-HS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
0d6d25475d radeonsi/gfx9: set EXEC for non-mono merged shaders, add a barrier between them 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
a84a6feac9 radeonsi/gfx9: don't store the HS control word 
GFX9 doesn't have it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
1d90ecd3a5 radeonsi/gfx9: pass inputs from LS to TCS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
cbd1bc2e3e radeonsi/gfx9: add TCS epilog support for merged LS-HS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
f11ced475e radeonsi/gfx9: add VS prolog support for merged LS-HS 
HS input VGPRs must be reserved.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
82a0e4f658 radeonsi/gfx9: merged shaders have scratch offset at the beginning 
also, screen wasn't initialized for compute shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
0c253557b2 radeonsi/gfx9: define LS-HS main shader function prototype 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
852ea69a2d radeonsi: assign VS/TCS/TES/GS shader input parameter locations dynamically 
They will vary with merged stages.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
067dacd1b1 radeonsi/gfx9: define and set LS-HS user SGPRs 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
0588146cb0 radeonsi/gfx9: set up shader registers for merged LS-HS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
62abdb17bb radeonsi/gfx9: add initial code generation for non-monolithic merged LS-HS 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00