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radeonsi: fix tess offchip offset for per-patch attributes

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We need 4 more bits there. I don't know what is fixed by this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-04-22 21:12:08 +02:00
parent 4e50062028
commit 0490074cab
3 changed files with 18 additions and 12 deletions
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8
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -715,8 +715,8 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
LLVMValueRef param_stride, constant16;
vertices_per_patch = unpack_param(ctx, ctx->param_tcs_offchip_layout, 9, 6);
num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 9);
vertices_per_patch = unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
num_patches, "");
@ -742,7 +742,7 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
if (!vertex_index) {
LLVMValueRef patch_data_offset =
unpack_param(ctx, ctx->param_tcs_offchip_layout, 16, 16);
unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
patch_data_offset, "");
@ -1546,7 +1546,7 @@ static void declare_system_value(struct si_shader_context *ctx,
if (ctx->type == PIPE_SHADER_TESS_CTRL)
value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
else if (ctx->type == PIPE_SHADER_TESS_EVAL)
value = unpack_param(ctx, ctx->param_tcs_offchip_layout, 9, 7);
value = unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
else
assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
break;

17
src/gallium/drivers/radeonsi/si_shader_internal.h
View file

@ -130,7 +130,7 @@ struct si_shader_context {
* [0] = clamp vertex color
* [1] = indexed
* [8:20] = stride between patches in DW = num_inputs * num_vertices * 4
* max = 32*32*4
* max = 32*32*4 + 32*4
* [24:31] = stride between vertices in DW = num_inputs * 4
* max = 32*4
*/
@ -142,21 +142,26 @@ struct si_shader_context {
/* API TCS & TES */
/* Layout of TCS outputs in the offchip buffer
* [0:8] = the number of patches per threadgroup.
* [9:15] = the number of output vertices per patch.
* [16:31] = the offset of per patch attributes in the buffer in bytes. */
* # 6 bits
* [0:5] = the number of patches per threadgroup, max = NUM_PATCHES (40)
* # 6 bits
* [6:11] = the number of output vertices per patch, max = 32
* # 20 bits
* [12:31] = the offset of per patch attributes in the buffer in bytes.
* max = NUM_PATCHES*32*32*16
*/
int param_tcs_offchip_layout;
/* API TCS */
/* Offsets where TCS outputs and TCS patch outputs live in LDS:
* [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
* [16:31] = TCS output patch0 offset for per-patch / 16
* max = NUM_PATCHES*32*32* + 32*32
* max = (NUM_PATCHES + 1) * 32*32
*/
int param_tcs_out_lds_offsets;
/* Layout of TCS outputs / TES inputs:
* [0:12] = stride between output patches in DW, num_outputs * num_vertices * 4
* max = 32*32*4
* max = 32*32*4 + 32*4
* [13:20] = stride between output vertices in DW = num_inputs * 4
* max = 32*4
* [26:31] = gl_PatchVerticesIn, max = 32

5
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -211,8 +211,9 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
((output_vertex_size / 4) << 13);
tcs_out_offsets = (output_patch0_offset / 16) |
((perpatch_output_offset / 16) << 16);
offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
(num_tcs_output_cp << 9) | *num_patches;
offchip_layout = *num_patches |
(num_tcs_output_cp << 6) |
(pervertex_output_patch_size * *num_patches << 12);
/* Compute the LDS size. */
lds_size = output_patch0_offset + output_patch_size * *num_patches;