If the ISL caller didn't specify a row_pitch_B, let's use the
NVIDIA/AMD requirements. Otherwise keep using the Intel requirement,
as the caller is likely trying to import a buffer and if we can deal
with that row_pitch_B, we should accept it.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a3a4517f41 ("isl: Work around NVIDIA and AMD display pitch requirements")
Reported-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13024>
(cherry picked from commit 9fb2c84768)
Otherwise we hit assert in vk_object_base_assert_valid when attemping to
create handle from anv_fence with unknown base type.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13330>
(cherry picked from commit d729038c07)
Two carchase compute shaders (shader-db) and two Fallout 4 fragment
shaders (fossil-db) were helped. Based on the NIR of the shaders, all
four had structures like
for (i = 0; i < 1; i++) {
...
for (...) {
...
}
}
All HSW+ platforms had similar results. (Ice Lake shown)
total loops in shared programs: 6033 -> 6031 (-0.03%)
loops in affected programs: 4 -> 2 (-50.00%)
helped: 2
HURT: 0
All Intel platforms had similar results. (Ice Lake shown)
Instructions in all programs: 143692018 -> 143692006 (-0.0%)
SENDs in all programs: 6947154 -> 6947154 (+0.0%)
Loops in all programs: 38285 -> 38283 (-0.0%)
Cycles in all programs: 8434822225 -> 8434476815 (-0.0%)
Spills in all programs: 191665 -> 191665 (+0.0%)
Fills in all programs: 298822 -> 298822 (+0.0%)
In the presense of loop unrolling like this, the change in cycles is not
accurate.
v2: Rearrange the logic in the if-condition to read a little better.
Suggested by Tim.
Closes: #5089
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13323>
(cherry picked from commit ae99ea6f4d)
Fixes: 8b95f51ef1 - radeonsi: fix and enable full DCC with MSAA 2x on gfx9
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13256>
(cherry picked from commit 86a33569f4)
Conflicts:
src/gallium/drivers/radeonsi/ci/raven-deqp-fail.csv
CI file does not exist in 21.2, so remove it
KHR-GL32.packed_pixels.pbo_rectangle.r16i on zink on lavapipe
ends up using a pbo that does an SINT image write. This was producing
truncated rather than clamped values.
Fix the calculations for 8/16-bit signed ints to clamp not truncate.
Fixes: 13e5f331db ("gallivm/nir: fix image store conversions")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13187>
(cherry picked from commit 1d48022dab)
Conflicts:
src/gallium/drivers/zink/ci/deqp-zink-lvp-fails.txt
We already set HALF_INTEGER, which is what the compiler actually does.
If we also set PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER, we get
incorrect lowering. Only set the CAP we respect.
On Bifrost, this convention is arbitrary. We should consider moving the
Bifrost lowering into NIR to optimize this better...
Fixes Piglit glsl-arb-fragment-coord-conventions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13070>
(cherry picked from commit 12facf23b1)
Conflicts:
src/panfrost/ci/piglit-panfrost-g52-fails.txt
This CI file doesn't exist in 21.2.x, so it was removed from this patch
When the determinant that we use for calculating triangle area
is NaN, it's not possible to decide the facing of the triangle.
This can happen when a coordinate of one of the triangle's vertices
is INFINITY. It's better to just accept these triangles in the shader
and let the PA deal with them.
Let's do the same for +/- Infinity too.
Though we haven't seen this yet, it may be troublesome as well.
Fixes: 651a3da1b5Closes: #5470
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13299>
(cherry picked from commit 783f8f728c)
Traces with clock = 0 are totally useless due to RGP getting very
confused.
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13301>
(cherry picked from commit 33065149c1)
Dropping the final pipe ref could in turn drop the final ref to one
of a couple other bo's, which in turn could indirectly recurse back
into cleanup_fences() on the same bo, resulting in a double decrement
of bo->nr_fences and underflow to a large positive #. This happens
because free'ing a bo back to the bo cache periodically calls
fd_bo_cache_cleanup() and any bo's that have not been re-used can
be really free'd, which in turn calls cleanup_fences().
Fixes: 7dabd62464 ("freedreno/drm: Userspace fences")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13263>
(cherry picked from commit faed3d4dfe)
Translate PIPE_BIND_SCANOUT as ISL_SURF_USAGE_DISPLAY_BIT,
instead of PIPE_BIND_DISPLAY_TARGET.
PIPE_BIND_DISPLAY_TARGET isn't used for dri images and seem to
be set only for fake winsys buffers (which aren't displayed).
The trouble is that a fake buffer could be multisampled and we
cannot have multisampled surface with display bit.
Ported from iris 82b4666783
Fixes: f3630548f1 ("crocus: initial gallium driver for Intel gfx 4-7")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Tested-by: Jason Ekstrand <jason@jlekstrand.net>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5464
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13260>
(cherry picked from commit 40fdb35c65)
Gallium caches sampler states for TBOs. Now if a buffer is first
attached to a TBO specifying one format, and later attached by
specifying another format and this TBO is then used, that would lead
to an assertion failure in debug builds, or to invalid rendering in
release builds, because the TBO picks the original, wrong format for
the sampler view.
Resolve this by signalling the change to Gallium (and other drivers), so
that Gallium clears the sampler view cache.
Fixes: f0ecd36ef8
st/mesa: add an entirely separate codepath for setting up buffer views
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13230>
(cherry picked from commit e95ecff784)
New access flags & pipeline stages got added for transform feedback
and we missed handling them.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 36ee2fd61c ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9045>
(cherry picked from commit ad9d95eee4)
Fixes leaks (release) or assertion failures (debug) on allocating small
scanout resources, when falling through to the non-scanout-specific layout
code, which became more common as of ad50b47a14 ("gbm: assume
USE_SCANOUT in create_with_modifiers").
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13202>
(cherry picked from commit 60f464bbce)
We want to assert that the number of varyings (the count) is at most the
the maximum count. This is <=, not <, with the assertion previously
failing for exactly the maximum.
Fixes: 2c2cf0ecfe ("panfrost: Streamline varying linking code")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13070>
(cherry picked from commit 9c8311b737)
The number of special varyings on midgard can influence how much space
we need to allocate for varyings in the compiler ABI. Move the enum so
we can get access it.
No functional change. This is cc stable purely so the following patches
can be backported.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13070>
(cherry picked from commit 00b0529061)
When a GPU hang occurs, the syncobj will eventually timeout,
if this is a wait, just set ready, so things will continue.
This matches 965 behaviour better.
Fixes: c282a082be ("crocus/query: poll the syncobj in the no wait situation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13188>
(cherry picked from commit 0a592db573)
Use 0xB instead of 0x00FFFFFF - this allows to jump over the culling
code when no actual culling is enabled but the ngg_cull_face_is_ccw
flag is set.
Fixes: 182d9b1e60
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13129>
(cherry picked from commit 6ca66808b5)
Use the newly added wrapper lp_set_module_stack_alignment_override() to
achieve the same end result.
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Closes: mesa/mesa#4906
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11940>
(cherry picked from commit 3a2d317b99)
We need it in the next commit to replace setting the stack alignment on
i386 with LLVM >= 13 through the TargetOption::StackAlignmentOverride,
which was removed in the upstream commit
<3787ee4571>.
Unfortunately Module::setOverrideStackAlignment() is not available
through the C API and we need to wrap it ourselves.
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reference: mesa/mesa#4906
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11940>
(cherry picked from commit c1b4c64a28)
If we're going to have to bind them as separate planes with colorspace
conversion for sampling on the frontend, then we need to report that
they're only for external-image samplers, otherwise the lowering won't be
applied.
Fixes: 4e3a7dcf ("gallium: enable EGL_EXT_image_dma_buf_import_modifiers unconditionally")
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13038>
(cherry picked from commit c530510514)
force_vrs was always RADV_FORCE_VRS_NONE at that point and the
hw workaround was never applied.
Found by inspection.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13098>
(cherry picked from commit 0c88c5cdc4)
This fixes SPECVIEWPERF13 creo test case hang:
1. Client: send present pixmap request (serial=1) when swap_interval==1
and increase send_sbc=1
2. Server: pend the request before vblank arrives
3. Client: set swap_interval=0 (so set XCB_PRESENT_OPTION_ASYNC),
send another present pixmap request (serial=2), increase send_sbc=2
4. Server: handle the async request immediately and send complete event
(serial=2)
5. Client: handle the event and set recv_sbc=event->serial=2
6. Server: vblank arrives so handle pending request and send complete
event (serial=1)
7. Client: handle the event and set recv_sbc=event->serial=1
8. Client: someone call loader_dri3_swapbuffer_barrier() and waiting
on recv_sbc==send_sbc, but no one will set recv_sbc=2 again
So basically it's caused by swap happens out of order. This commit
fixes the problem by waiting on the pending sync swaps all done when
switching to async mode, so move 6&7 before 3.
Attach the xtrace when problem happens:
005:<:003e: 72: Present-Request(148,1): Pixmap window=0x03000002 pixmap=0x0300000b serial=1 valid=0x00000000 update=0x00000000 x_off=0 y_off=0 target_crtc=0x00000000 wait_fence=0x00000000 idle_fence=0x0300000c options=0 target_msc=4294967296 divisor=0 remainder=0 notifies=;
...
005:<:0041: 72: Present-Request(148,1): Pixmap window=0x03000002 pixmap=0x03000011 serial=2 valid=0x00000000 update=0x00000000 x_off=0 y_off=0 target_crtc=0x00000000 wait_fence=0x00000000 idle_fence=0x03000012 options=Async target_msc=0 divisor=0 remainder=0 notifies=;
005:>:0041: Event Generic(35) Present(148) IdleNotify(2) event=0x03000006 window=0x03000002 serial=2 pixmap=0x03000011 idle_fence=0x03000012
005:>:0041: Event Generic(35) Present(148) CompleteNotify(1) kind=Pixmap(0x00) mode=Copy(0x00) event=0x03000006 window=0x03000002 serial=2 ust=7505462213117739011 msc=3565046193979392
005:>:0041: Event Generic(35) Present(148) IdleNotify(2) event=0x03000006 window=0x03000002 serial=1 pixmap=0x0300000b idle_fence=0x0300000c
005:>:0041: Event Generic(35) Present(148) CompleteNotify(1) kind=Pixmap(0x00) mode=Copy(0x00) event=0x03000006 window=0x03000002 serial=1 ust=7505533793042694147 msc=3565050488946688
Cc: mesa-stable
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13019>
(cherry picked from commit e55e61758c)
The vk_shader_module_handle_from_nir() macro was constructing a
temporary vk_shader_module and passing it through
vk_shader_module_to_handle(). Since this is a function and not a macro,
it means that the lifetime of the temporary vk_shader_module will end
once the to_handle() function is called. Technically, this is a
use-after-free. I really don't know why no one has been bitten by this
yet....
Fixes: a41e98ddca "vk/util: add a util macro for initializing stack..."
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13101>
(cherry picked from commit 24637a6579)
