Commit graph

55713 commits

Author SHA1 Message Date
Marek Olšák
e951d6362c ci: update pass/fail results for spec@!opengl 1.0@gl-1.0-dlist-bitmap
This is mostly positive.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
2022-08-24 18:13:02 +00:00
Mike Blumenkrantz
c4f78396d4 zink: support PIPE_CAP_FBFETCH_COHERENT
that's what VK_EXT_rasterization_order_attachment_access is for

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18133>
2022-08-24 12:19:13 +00:00
Lucas Stach
8b8beae8d5 etnaviv: expose ARB_draw_instanced
Just set the pipe cap correctly. The InstanceID support is already
hooked up in the NIR compiler. All enabled piglit tests pass.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18046>
2022-08-24 09:13:31 +00:00
Vinson Lee
1dffad2f83 zink: Remove duplicate variable zero.
Fix defect reported by Coverity Scan.

Evaluation order violation (EVALUATION_ORDER)
write_write_typo: In zero = zero = nir_imm_zero(b, nir_dest_num_components(intr->dest), nir_dest_bit_size(intr->dest)),
zero is written twice with the same value.

Fixes: 0f97e317e3 ("zink: rewrite all undefined shader reads as 0001 instead of undef")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18164>
2022-08-24 04:48:10 +00:00
Qiang Yu
ff7c59672f radeonsi: fix tcs_out_lds_offsets arg alignment
tcs_out_lds_offsets is not sure to be 16 byte aligned, it's
calculated like this:

  num_patches * patch_vertices * lshs_vertex_stride

num_patches and patch_vertices are not sure to be any value aligned,
lshs_vertex_stride is added one extra dword, so it's only 4 byte
aligned.

This may cause problem even before we switch to nir tess output
lower when write tess factor before read tail of input. But it's
more likely to cause problem after we switch to nir tess output
lower because the main body won't eliminate the low 4bit offset
but epilog will, so they use different offset to read/write tess
factor.

Fixes: 7598bfd768 ("radeonsi: replace llvm tcs output with nir lower pass")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7083
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18174>
2022-08-24 02:04:15 +00:00
Caio Oliveira
a1b1fdf70d intel/compiler: Rename 8_PATCH to MULTI_PATCH
Make it clearer we are dealing with multiple patches,
works better in constrast with SINGLE_PATCH.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18151>
2022-08-24 00:39:57 +00:00
Jordan Justen
e9f40e42de iris: Drop extra file-descriptor dup in iris_drm_screen_create()
In a99e85db9e, we added a dup into iris_screen_create(). Apparently
some android code paths must be hitting iris_screen_create() without
calling iris_drm_screen_create(). After a99e85db9e, the code paths
that do hit iris_drm_screen_create() will now dup the fd twice, but
iris_screen_destroy() will only close 1 of these fds.

Fixes: a99e85db9e ("iris:Duplicate DRM fd internally instead of reuse.")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18020>
2022-08-23 22:54:23 +00:00
Kai Wasserbäch
559c027ade chore(deps): clover: raise the minimum LLVM version to 11.0.0
LLVM 11 was released in October 2020. If you want to build against
Mesa's Git version, that seems like enough time to upgrade to at least
LLVM 11 (Debian stable has this too).

It reduces the amount of #if gates we need and more will be incoming
again, given the Opaque Pointer transition.

Additionally radeonsi is already requiring LLVM 11. Therefore the
minimum will have been LLVM 11 for many builds anyway.

Note that clc is kept to LLVM 10 for the time being.

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16047>
2022-08-23 19:23:05 +00:00
Karol Herbst
f56609a679 nvc0: limit max global and alloc size
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10711>
2022-08-23 18:29:44 +00:00
Pierre Moreau
f360086c30 nv50: Mark RESOURCE_FROM_USER_MEMORY_COMPUTE_ONLY as unsupported
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10711>
2022-08-23 18:29:44 +00:00
Pierre Moreau
ebcec3b637 nv50: Disallow allocating more than VRAM size
Allocations larger than the amount of VRAM available might be possible,
but has not been tested.

v4: Change it back to just VRAM size
v3: Increase the minimum from 32 MB to 128 MB, as OpenCL 1.x mandated at
    least 128 MB.
v2: Further lower the allocation size.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10711>
2022-08-23 18:29:44 +00:00
Pierre Moreau
66385d79dc nv50: Report actual VRAM size
v2: handle vram_size == 0 (Karol)

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10711>
2022-08-23 18:29:44 +00:00
Pierre Moreau
bb61bfc90e nv50: Rename interps to fixups
This matches the denomination used in nvc0, and finishes the name change
that started in f5fe9030.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10711>
2022-08-23 18:29:44 +00:00
Pierre Moreau
120c43cf46 nv50: Rename fixups to relocs
This matches the names used on nvc0.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10711>
2022-08-23 18:29:44 +00:00
Pierre Moreau
8c066e7a57 nv50,nvc0: Do not resize global residents if unnecessary
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10711>
2022-08-23 18:29:44 +00:00
Ruijing Dong
10de12d710 radeonsi/vcn: add AUD syntax to h264 encoding
Adding AUD syntax to h264 bitstream, for easier locate
frame boundaries.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17994>
2022-08-23 15:56:07 +00:00
Ruijing Dong
12cde23c38 radeonsi/vcn: remove rate control double begin IBs
[why]
when start rate control, two begin IBs have been sent

[how]
merge two begin IBs together

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17994>
2022-08-23 15:56:07 +00:00
Ruijing Dong
b0c3f62b54 radeonsi/vcn: support VBAQ modes
add VBAQ supports to all vcn versions.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17994>
2022-08-23 15:56:07 +00:00
Ruijing Dong
d00d4b9b6a radeonsi/vcn: support encoding preset modes
- support preset modes for all vcn versions
- SAO HEVC cannot use SPEED mode from vcn2 and up

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17994>
2022-08-23 15:56:07 +00:00
Ruijing Dong
20ca84646b radeonsi/vcn: dpb change for supporting pre-encoding
- dpb buffer created while receive the first begin_frame
  moved out from encoder creation.
- dpb buffer name changed from cpb.
- dpb buffer allocation to support pre-encoding
- different vcn version IB package adjustment
- merge reconstructed_picture_v4_0_t to reconstructed_picture_t

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17994>
2022-08-23 15:56:07 +00:00
Ruijing Dong
60f0a182e1 radeonsi/vcn: add enc quality bits interface
- define quality_level interface in mesa
- interprete quality_level to internal modes

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17994>
2022-08-23 15:56:07 +00:00
Ruijing Dong
a727ec83ba frontends/va: improve enc quality interface change
[why]
to enhance va video encoding quality

[how]
use va encoding quality_level interface, and provide
default value and encoding quality adjustment options,
so that users can finetune encoding quality and performance
from va quality interface. (limited to VCNs)

There are 3 settings added:
- preset modes: speed, balance, quality
  they are using different encoding strategies
- vbaq modes:
  vbaq mode is using variance based strategy
  to improve the subjective image quality
- pre-encoding modes:
  Using scaled down input image for pre-encoding to have
  better rate-control reaction and consume more memory
  in the same time. Only preencoding-4x mode is enabled.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17994>
2022-08-23 15:56:07 +00:00
Yonggang Luo
da4edc0d2a osmesa: Fixes [-Wdeprecated-declarations] in test-render.cpp
Warning message:
../src/gallium/targets/osmesa/test-render.cpp:150:1: warning: 'InstantiateTestCase_P_IsDeprecated' is deprecated: INSTANTIATE_TEST_CASE_P is deprecated, please use INSTANTIATE_TEST_SUITE_P [-Wdeprecated-declarations]

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18203>
2022-08-23 15:19:16 +00:00
Yonggang Luo
993889a995 virgl: Fixes [-Wdeprecated-declarations] in virgl_staging_mgr_test.cpp
Warning message:
../src/gallium/drivers/virgl/tests/virgl_staging_mgr_test.cpp:188:1: warning: 'InstantiateTestCase_P_IsDeprecated' is deprecated: INSTANTIATE_TEST_CASE_P is deprecated, please use INSTANTIATE_TEST_SUITE_P [-Wdeprecated-declarations]

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18203>
2022-08-23 15:19:16 +00:00
Sviatoslav Peleshko
0a0aa24b33 iris: Always initialize shader compilation queue ready fence
We use/delete this fence unconditionally, but it was initialized only
when screen->precompile is set. Move the util_queue_fence_init call
to the iris_create_uncompiled_shader to initialize it always.

Fixes: 42c34e1a ("iris: Enable threaded shader compilation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7074
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Tested-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18182>
2022-08-23 12:38:11 +00:00
Mike Blumenkrantz
585fa6bf40 zink: ignore nir_texop_lod for tex dest matching
this doesn't need fixing

Fixes: 3a47576687 ("zink: add a compiler pass to match up tex op dest types")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18196>
2022-08-23 01:44:59 +00:00
Mike Blumenkrantz
e95b9ac9a8 zink: handle nir_intrinsic_sparse_residency_code_and mechanics
without glsl array lowering, this intrinsic can creep in for tg4 ops,
which complicates everything. instead, rewrite these ops as residency+iand,
and then rewrite the existing residency ops to match

v2 (idr): Add missing size parameter to nir_is_sparse_texels_resident
calls.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16547>
2022-08-23 01:10:23 +00:00
Ian Romanick
1aacd9492d radeonsi: r600: d3d12: st: Use NIR lowering for tg4 offset arrays instead of GLSL lowering
I think I got all the drivers that need updating.  This is only
necessary in drivers that support GLSL 4.00 / GL_ARB_gpu_shader5 and
have PIPE_CAP_TEXTURE_GATHER_OFFSETS = 0.

v2: Don't (accidentally) condition tg4 offsets lowering on tex rect
lowering.  Noticed by Qiang.

v3: Add missing bool() cast.

v4: don't use designated initializers

Fixes: 640f909862 ("glsl: add _texture related sparse texture builtin functions")
Closes: #6365
Tested-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16547>
2022-08-23 01:10:23 +00:00
Charmaine Lee
f73862d339 svga: fix invalid component access of domain location
Tesscoord is declared as vec3 in the incoming shader but the z component
of a tesscoord should only be referenced in the domain shader if the
tessellator domain is of triangle type.

Fixes vmx crash running GFXBench-Tessellation with MTL Renderer.

Reviewed-by: Martin Krastev <krastevm@vmware.com>
Reviewed-by: Min-Yu Huang <min-yuhuang@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18185>
2022-08-23 00:38:08 +00:00
Rob Clark
16d33b8ba1 freedreno: Avoid deferred-flush dependency loops
We can't blindly make every other batch a dependency of the current
batch, because it is possible they already have a dependency on the
current batch, which would result in a loop.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18200>
2022-08-22 23:51:10 +00:00
Rob Clark
425514e62e freedreno: Simplify add_dep logic
These two cases never happen, guaranteed by the logic above that adds
to the batches[] table.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18200>
2022-08-22 23:51:10 +00:00
Rob Clark
027dbe2cb3 freedreno: Extract helper to check for batch dependency
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18200>
2022-08-22 23:51:10 +00:00
Yonggang Luo
a5972eb7ac mapi: Remove usage of _glapi_check_multithread and _glapi_destroy_multithread
They are empty stub functions now so have no need call to them

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17814>
2022-08-22 21:32:09 +00:00
marek
ddd74bec38 radeonsi/ci: make the running script easy to use
Changes:
- No path parameters are needed to run all tests.
- All test results are stored next to cloned repos instead of /tmp.
  This is a personal preference, though not necessary.

The new setup guide is going to be:
- mesa, piglit, deqp, and glcts directories must be next to each other.
- Add `PATH=$HOME/?/mesa/src/gallium/drivers/radeonsi/ci:$PATH` into
  `.bashrc`. Replace `?` with the proper path.
- Install Rust, which will include its package manager Cargo:
  https://www.rust-lang.org/tools/install
  - The installer will add the Cargo environment into `.bashrc`, which will
    add cargo into `PATH`.
- Restart bash to get the new `PATH`.
- Run: `cargo install deqp-runner`

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

The parameters setting the various paths won't be explained to keep
the guide short.

The path parameters and env vars can be removed if everybody stops using
them after this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18155>
2022-08-22 20:04:52 +00:00
Alyssa Rosenzweig
9573b24ab4 gallium: Remove util_make_fragment_tex_shader_xrbias
Unused.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17918>
2022-08-22 15:32:05 +00:00
Alyssa Rosenzweig
18539a4099 gallium: Inline away util_make_fragment_tex_shader interp_mode
Everything sets it to linear.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17918>
2022-08-22 15:32:05 +00:00
Alyssa Rosenzweig
b61ce265d7 gallium: Inline away util_make_fragment_tex_shader_writemask
Nothing actually uses writemasks, get rid of them.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17918>
2022-08-22 15:32:05 +00:00
Alyssa Rosenzweig
4ac72f7d1a r600/sfn: Don't use broken idiv lowering
NIR has two implementations of lower_idiv, keyed on the imprecise_32bit_lowering
flag. This flag is misleading: the results when setting this flag "imprecise",
they're completely wrong for some values. Non-constant highp integer division is
rare enough this shouldn't noticeably harm performance of real applications.

Address r600 portion of #6555.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18154>
2022-08-22 13:06:39 +00:00
Pavel Ondračka
c38023a9b2 r300: Set more shadow sampler lowering in precompiles.
This extends the commit 17cea74b8c
also for rectangular textures. They are otherwise lowered to MOV
dst temp[0].0000 and deadcode elimitation goes crazy.

Fixes shader-db with tesseract shaders from https://gitlab.freedesktop.org/mesa/mesa/-/issues/6771

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18168>
2022-08-22 11:21:24 +00:00
Juan A. Suarez Romero
4ba21c3e8c vc4: store tex sampler in proper register
When unpacking the texture sample result ensure it is moved to the
proper expected dest register.

This fixes incorrect texturing in Chromium using PixiJS framework.

CC: mesa-stable
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18122>
2022-08-22 10:34:39 +00:00
Konstantin Seurer
ddae033674 lavapipe: Set ss_dirty in emit_state
Set ss_dirty to false when updating the samplers.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18161>
2022-08-22 09:43:03 +00:00
Alyssa Rosenzweig
0a71d56fd4 panfrost: Invert no_colour to enabled
This way, blend info that's left zeroed out defaults to disabled. Fixes an
assertion failure in KHR-GLES31.core.draw_buffers_indexed.color_masks due to
the blend CSO max_rt being set unreliably. This is also probably clearer.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17841>
2022-08-21 19:37:10 +00:00
Alyssa Rosenzweig
39bf3ea7d3 panfrost: Don't compile empty blend shaders
This is silly. They'll be masked out later, but it's still pointless, and adds
noise when grepping BIFROST_MESA_DEBUG=shaders,internal for "pan_blend" when
debugging why an app is using blend shaders.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17841>
2022-08-21 19:37:10 +00:00
Alyssa Rosenzweig
d849d9779a panfrost: Avoid blend shader when not blending
On Midgard, we need a "blend" shader even if blending is disabled, if the format
isn't blendable. This is inefficient. Bifrost solves this by decoupling the
format conversion from the blending, allowing opaque (unblended) output to any
format without a blend shader or fragment key.

Unfortunately, our blend code is from the Midgard era -- I wrote an early
version of nir_lower_blend when I was still in high school! -- so we've been
using blend shaders for opaque output even on Bifrost. Whoops!

In SuperTuxKart, reduces blend shader calls by 30%, translating to a 15%
reduction in i-cache misses.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17841>
2022-08-21 19:37:10 +00:00
Alyssa Rosenzweig
d680560970 panfrost: Handle untyped_color_outputs on Bifrost
For untyped_color_outputs, we need to ignore the type of the colour output in
the shader and instead use the type from the format. We have all the information
to do this at blend descriptor pack time, but not at shader compile time. This
means we need a (somewhat expensive) fixup in this edge case to ingest
NIR-to-TGSI. This will prevent a regression from the rest of the series.

Although the register_format field is also present on Valhall blend descriptors,
it is ignored so we don't need the fixup there.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17841>
2022-08-21 19:37:10 +00:00
Pavel Ondračka
9c01fff445 r300: merge MOVs with MULs or ADDs in merge channels
Shader-db stats with RV530:
total instructions in shared programs: 166499 -> 164362 (-1.28%)
instructions in affected programs: 80056 -> 77919 (-2.67%)
total temps in shared programs: 21658 -> 21565 (-0.43%)
temps in affected programs: 1780 -> 1687 (-5.22%)

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17560>
2022-08-21 09:52:50 +02:00
Pavel Ondračka
275beae42d r300: merge MOVs into ADD using the 0 swizzle
Shader-db stats with RV530:
total instructions in shared programs: 169509 -> 166013 (-2.06%)
instructions in affected programs: 99126 -> 95630 (-3.53%)
total presub in shared programs: 10975 -> 10758 (-1.98%)
presub in affected programs: 744 -> 527 (-29.17%)
total temps in shared programs: 21722 -> 21649 (-0.34%)
temps in affected programs: 1350 -> 1277 (-5.41%)

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17560>
2022-08-21 09:52:31 +02:00
Pavel Ondračka
13607d8c48 r300: don't merge w channel in fragment shaders
Skip the merge if one of the instructions writes just w channel
and we are compiling a fragment shader. We can pair-schedule it together
later anyway and it will also give the scheduler a bit more flexibility.

Shader-db stats with RV530:
total instructions in shared programs: 169522 -> 169509 (<.01%)
instructions in affected programs: 14170 -> 14157 (-0.09%)
total temps in shared programs: 21712 -> 21722 (0.05%)
temps in affected programs: 324 -> 334 (3.09%)

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17560>
2022-08-21 09:52:15 +02:00
Pavel Ondračka
268f317f22 r300: generalize the merge_movs pass
To allow a simple extension with more merging combinations in the
later commits.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17560>
2022-08-21 09:51:49 +02:00
Pavel Ondračka
05785d482e r300: run dataflow optimizations in separate loops
Constant folding first, than copy propagate simple movs, after that
we run the merge movs pass and finally peephole. The important part
is to do the copy propagate for the whole program before running merge
movs.

We no longer check the return from merge_movs so convert it to void.

Shader-db changes with RV530:
total instructions in shared programs: 155361 -> 154787 (-0.37%)
instructions in affected programs: 67920 -> 67346 (-0.85%)
total temps in shared programs: 20836 -> 20773 (-0.30%)
temps in affected programs: 711 -> 648 (-8.86%)
total presub in shared programs: 8226 -> 8202 (-0.29%)
presub in affected programs: 223 -> 199 (-10.76%)
total temps in shared programs: 20836 -> 20773 (-0.30%)
temps in affected programs: 711 -> 648 (-8.86%)

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17560>
2022-08-21 09:51:10 +02:00