fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-03 12:08:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radeonsi/vcn: support encoding preset modes

Browse source 
- support preset modes for all vcn versions
- SAO HEVC cannot use SPEED mode from vcn2 and up

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17994>
This commit is contained in:
Ruijing Dong 2022-08-19 19:59:59 -04:00 • committed by Marge Bot
parent 20ca84646b
commit d00d4b9b6a
2 changed files with 28 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
View file

@ -1205,9 +1205,18 @@ static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
RADEON_ENC_END();
}
static void radeon_enc_op_speed(struct radeon_encoder *enc)
static void radeon_enc_op_preset(struct radeon_encoder *enc)
{
RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
uint32_t preset_mode;
if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_QUALITY)
preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_BALANCE)
preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
else
preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
RADEON_ENC_BEGIN(preset_mode);
RADEON_ENC_END();
}
@ -1381,7 +1390,7 @@ void radeon_enc_1_2_init(struct radeon_encoder *enc)
enc->op_enc = radeon_enc_op_enc;
enc->op_init_rc = radeon_enc_op_init_rc;
enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv;
enc->op_preset = radeon_enc_op_speed;
enc->op_preset = radeon_enc_op_preset;
enc->encode_params = radeon_enc_encode_params;
enc->session_init = radeon_enc_session_init;

19
src/gallium/drivers/radeonsi/radeon_vcn_enc_2_0.c
View file

@ -73,9 +73,22 @@
#define RENCODE_COLOR_PACKING_FORMAT_NV12 0
#define RENCODE_COLOR_PACKING_FORMAT_P010 1
static void radeon_enc_op_balance(struct radeon_encoder *enc)
static void radeon_enc_op_preset(struct radeon_encoder *enc)
{
RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE);
uint32_t preset_mode;
if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_SPEED &&
(enc->enc_pic.sample_adaptive_offset_enabled_flag &&
(u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC)))
preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_QUALITY)
preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_BALANCE)
preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
else
preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
RADEON_ENC_BEGIN(preset_mode);
RADEON_ENC_END();
}
@ -489,7 +502,7 @@ void radeon_enc_2_0_init(struct radeon_encoder *enc)
enc->input_format = radeon_enc_input_format;
enc->output_format = radeon_enc_output_format;
enc->ctx = radeon_enc_ctx;
enc->op_preset = radeon_enc_op_balance;
enc->op_preset = radeon_enc_op_preset;
if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
enc->deblocking_filter = radeon_enc_loop_filter_hevc;