Don't report compressed memory type in the case of Xe2 modifiers
as the Vulkan spec requires identical memory types behind the
VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
Instead, we require dedicated allocation to get the right
compressed memory in allocation stage. The BMG modifier also
requires scanout flag to set. Refer to comments.
Thanks for the help from:
Nanley Chery <nanley.g.chery@intel.com>
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke <kenneth@whitecape.org>
and other people not listed.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
When aux has to be disabled (ISL_SURF_USAGE_DISABLE_AUX_BIT)
for some reasons like VK_SHARING_MODE_CONCURRENT, we simply
cannot implicitly choose any modifier with compression.
Otherwise, we run into a situation that an image is created
with a modifier but without the aux support that modifier
requires. It will fail a CTS test once Xe2 modifiers are
enabled:
dEQP-VK.wsi.wayland.swapchain.private_data.image_sharing_mode
MESA: warning: ../src/intel/vulkan/anv_image.c:1198: image with
modifier unexpectedly has wrong aux usage (VK_ERROR_UNKNOWN)
GFX12.x (MTL) does not show this failure because only one queue
family is present. But they will face the same issue when aux is
disabled for any other reasons:
NotSupported (Only 1 queue families available for
VK_SHARING_MODE_CONCURRENT at vktWsiSwapchainTests.cpp:715)
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
As a part of the effort to unify the displayable attribute
on dmabuf sharing across drivers, we set scanout flag on
imported bos on Xe2+.
Refer to the comment in the change.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
Update the conditions of reallocation for Xe2 modifiers and also
ensure the realloation to happen on all bos.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
Refer to the comment added into the change, buffers imported
with a Xe2 modifier supporting compression should get a
compression-enabled PAT entry.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
Narrow down the definition of two compression flags suggested by
Nanley Chery <nanley.g.chery@intel.com> so that we can address
the unified compression support of Xe2 modifiers and don't have
to set media compression flag thats result more update in the
stack.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
With cl_khr_fp16 we can get texture instructions w/ f16 dest. Not all
drivers handle this, so convert to 32b dest and insert alu conversion to
the requested type. Drivers that can handle f16 texture loads would
fold away the extra conversion with nir_opt_16bit_tex_image.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35470>
This fixes the following warning from Meson:
meson.options:179: WARNING: Project targets '>= 1.3.0' but uses
feature deprecated since '1.1.0': "boolean option" keyword argument
"value" of type str. use a boolean, not a string
Fixes: d348fd5fb5 ("mediafoundation: Add mediafoundation frontend")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35468>
For Linux guests, remove syncFd semaphores entirely, as they are waited
on/signaled using the guest-side syncFd operations, and coarse
queueWaits only.
Reviewed-by: Gurchetan Singh <gurchetansingh@google.com>
Reviewed-by: Marcin Radomski <dextero@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34751>
LOAD_MULTIPLE can be emitted inside of a loop body. We need to WAIT if
that loads targets a register for which a load was not already in-flight
at the start of the loop body.
Technically we only have to emit the wait if the dst reg of a new load
is actually used inside the loop, but that would require separate
tracking of source regs used in the loop and is probably not worth
the effort for now.
Fixes: f75569734e (panvk: Remove explicit LS waits)
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35436>
str.find(substr) returns -1 if the substring's not in the string, and
bool(-1) returns True in Python, so the _WIN32 ifdef guard was actually
inserted everywhere.
Also, the win32 functions actually have "Win32" in their name, like
vkGetMemoryWin32HandleKHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35389>
For cases when less than 4 components are read, the original code
would compute an incorrect dmask. eg: with a single component + is_sparse,
the dmask was 0x13:
- 0x 3 = coming from nir_def_components_read
- 0x10 = the sparse bit
While it should have at 2 bits set (1 for the color/depth, 1 for tfe).
This caused problem when expand_vector() used the dmask to generate
the final results, because the value for the sparse component was
read from the wrong index.
So after the call to emit_mimg() dmask needs to be adjusted
because the components will be stored in order, so if mask is 0x11
the tfe value would be stored at invalid index=5 (while it should
be at index=1).
This fixes KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupResidency_texture_2d_depth_component16
and KHR-GL46.sparse_texture2_tests.SparseTexture2Lookup_texture_2d_depth_component16
with ACO.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35206>
The referenced commit was a step in the right direction, but not
complete.
ac_build_image_opcode returns a vec<4> or a struct<vec<4>, int>
so we can simplify visit_tex. We just need to map these 4/5 values
to the expected layout from NIR.
eg: depth + TFE would produces "<d, x, x, x>, t" so it has to be
transformed into <d, t>.
nir_texop_fragment_mask_fetch_amd + sparse doesn't exist, so it's
another opportunity for simplification.
This is required to get KHR-GL46.sparse_texture2_tests.SparseTexture2Lookup_texture_2d_depth_component16
working properly.
The same test fails with ACO so it probably needs a change in the
same area.
Fixes: c0ef2aa7f8 ("DEPENDENCY: ac/llvm: fix sparse code handling")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35206>
When running radeonsi-run-tests.py with the -t option, it's possible that
some suite won't generate any result so don't fail in this case.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35206>
