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spirv: use feq for OpIsInf
This effectively reverts fcca6a83cd because feq was clarified to be ordered
when used with exact and without fast math flags.
It's common for HW to only have free abs for floating point instructions.
Foz-DB Navi21:
Totals from 63 (0.08% of 80065) affected shaders:
Instrs: 337027 -> 336667 (-0.11%); split: -0.12%, +0.02%
CodeSize: 1846752 -> 1845000 (-0.09%); split: -0.13%, +0.03%
Latency: 3401087 -> 3400633 (-0.01%); split: -0.04%, +0.03%
InvThroughput: 847299 -> 845939 (-0.16%); split: -0.19%, +0.03%
VClause: 7693 -> 7694 (+0.01%)
Copies: 45175 -> 45240 (+0.14%); split: -0.12%, +0.27%
PreSGPRs: 3555 -> 3553 (-0.06%)
PreVGPRs: 4565 -> 4564 (-0.02%)
VALU: 225473 -> 225245 (-0.10%); split: -0.13%, +0.03%
SALU: 44735 -> 44625 (-0.25%)
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35437>
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2 changed files with 10 additions and 2 deletions
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@ -3115,7 +3115,7 @@ optimizations += [(bitfield_reverse_cp2077('x@32'), ('bitfield_reverse', 'x'), '
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def vkd3d_proton_packed_f2f16_rtz_lo(a, abs_a):
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packed_half = ('pack_half_2x16_rtz_split', a, 0)
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packed_half_minus1 = ('iadd', packed_half, 0xffffffff)
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f32_was_not_inf = ('ine', abs_a, 0x7f800000)
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f32_was_not_inf = ('fneu', abs_a, 0x7f800000)
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f16_is_now_inf = ('ieq', ('iand', packed_half, 0x7fff), 0x7c00)
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return ('bcsel', ('iand', f32_was_not_inf, f16_is_now_inf), packed_half_minus1, packed_half)
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@ -893,8 +893,16 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
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}
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case SpvOpIsInf: {
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const bool save_exact = b->nb.exact;
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const unsigned save_fast_math = b->nb.fp_fast_math;
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b->nb.exact = true;
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b->nb.fp_fast_math = 0;
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nir_def *inf = nir_imm_floatN_t(&b->nb, INFINITY, src[0]->bit_size);
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dest->def = nir_ieq(&b->nb, nir_fabs(&b->nb, src[0]), inf);
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dest->def = nir_feq(&b->nb, nir_fabs(&b->nb, src[0]), inf);
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b->nb.exact = save_exact;
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b->nb.fp_fast_math = save_fast_math;
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break;
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}
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