Commit graph

16735 commits

Author SHA1 Message Date
Michel Dänzer
7443e4e697 radeonsi: Properly handle NULL sampler views.
Fixes piglit shaders/glsl-fs-uniform-sampler-array and many other similar
tests.

In fact, I just completed a piglit quick-driver.tests run without any GPU
lockups or even VM protection faults. Yay!

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-12 15:53:51 +02:00
Michel Dänzer
d67d8e2471 radeonsi: Fix calculation of number of records in buffer resource.
The value was too small by 1 in some cases (non-first of several vertex
elements interleaved in a single buffer).

Fixes intermittent incorrect geometry in many apps, e.g. piglit
spec/EXT_texture_snorm/fbo-generatemipmap-formats.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-12 13:23:09 +02:00
Tom Stellard
843ac06ad2 radeon/llvm: Fix operand order of V_CNDMASK in custom inserter
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:48 -04:00
Tom Stellard
d399ce7615 radeon/llvm: Assert if we try to encode an unknown register
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:48 -04:00
Tom Stellard
0df2753ad2 radeon/llvm: Add register encoding for VCC
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard
056d9c6ef1 radeon/llvm: Ignore special registers when calculating reg count
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard
0fb1e68a0b radeonsi: Handle position input parameter for pixel shaders v2
v2:
  - Don't increment ninterp or set any of the have_* flags for
    TGSI_SEMANTIC_POSITION

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard
0410e9e8c7 radeon/llvm: Coding style fixes
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard
d3e58f75d2 radeonsi: Move interpolation mode check into the compiler
The compiler needs to know which interpolation modes are enabled, so
it knows which values will be preloaded into the VGPRs.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard
5fff032dd5 radeonsi: Add missing interpolation mode to check for enabled modes
At least one interpolation mode must be enable, but the code that checks
this was not checking for perspective center.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard
cc571a367e radeonsi: Pass shader type to the compiler
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard
dfd3d61abf radeon/llvm: Add SHADER_TYPE instruction
This allows the program to specify the type of shader being compiled
(e.g. PXEL, VERTEX, etc.)

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Jerome Glisse
841c1b5f54 r600g: avoid GPU doing constant preload from random address
Previous command stream might have set any of the constant buffer
and the previous address might no longer be valid thus GPU might
preload constant from random invalid address and possibly triggering
lockup.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-09-11 12:57:54 -04:00
Michel Dänzer
9ccaa24f84 radeonsi: Texture border colour fixes.
* Handle arbitrary border colours.
* Use correct packing format for detecting special border colours.

Fixes piglit tex-border-1 and probably many other tests using border colours.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-11 11:06:56 +02:00
Michel Dänzer
03dfa30596 radeonsi: Handle NULL sampler states.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-11 11:06:16 +02:00
Marek Olšák
87389d4e5c r600g: remove unused function 2012-09-11 00:02:58 +02:00
Marek Olšák
830b6f3273 r600g: fix printf warning 2012-09-11 00:02:58 +02:00
Christoph Bumiller
3433471e8b nvc0/ir: add initial code to support GK110 ISA encoding 2012-09-07 19:03:40 +02:00
Michel Dänzer
8a497e5955 radeonsi: Float format fixups.
Fixes piglit spec/ARB_texture_float/fbo-generatemipmap-formats.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-07 18:23:08 +02:00
Michel Dänzer
15c009af28 radeonsi: Handle more SNORM formats.
Fixes piglit spec/EXT_texture_snorm/fbo-generatemipmap-formats (except for
what seems like a random fluke).

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-07 18:23:08 +02:00
Michel Dänzer
30b303743d radeonsi: Handle TGSI_SEMANTIC_FOG.
Fixes exponential fog. The pixel shaders for linear fog seem to get
miscompiled still somehow.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-07 16:12:04 +02:00
Michel Dänzer
3144821ef6 radeon/llvm: Match fexp2 for SI.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-07 12:16:32 +02:00
Jerome Glisse
5ceb87286f r600g: order atom emission v3
To avoid GPU lockup registers must be emited in a specific order
(no kidding ...). This patch rework atom emission so order in which
atom are emited in respect to each other is always the same. We
don't have any informations on what is the correct order so order
will need to be infered from fglrx command stream.

v2: add comment warning that atom order should not be taken lightly
v3: rebase on top of alphatest atom fix

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-09-06 15:09:17 -04:00
Jerome Glisse
935a729447 r600g: fix num of dwords needed for alphatest_state atom
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-09-06 15:09:14 -04:00
José Fonseca
edc0a00377 llvmpipe: Make driver name more informative.
Such as

  "llvmpipe (LLVM 3.1, 128 bits)"

or

  "llvmpipe (LLVM 3.1, 256 bits)"

when leveraging AVX 8-wide registers.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2012-09-06 16:35:25 +01:00
Michel Dänzer
694617a5b4 radeonsi: Handle more L/I/A format cases.
Fixes piglit fbo-generatemipmap-formats.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-06 16:48:16 +02:00
Michel Dänzer
cfebaf9dbd radeonsi: Enable whole quad mode for pixel shaders.
Fixes wrong mipmap level being sampled at some triangle edges.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-06 16:46:55 +02:00
Michel Dänzer
5edb80cee0 radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-06 16:46:42 +02:00
Michel Dänzer
e7383b74ef radeon/llvm: SI shader vector instructions implicitly use the EXEC register.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-06 16:46:27 +02:00
Michel Dänzer
ab162f80c3 radeon/llvm: Extend SI EXEC register support.
Add 32 bit lo and hi variants, and binary encodings.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-06 16:15:44 +02:00
Tom Stellard
2baaa5c7eb radeon/llvm: Remove R600InstrInfo.td from TD_FILES
Fixes build bug introduced by
cebbdd4ac2
2012-09-06 14:16:59 +00:00
Michel Dänzer
d0f51fe567 radeonsi: Enable NPOT textures again.
Should be at least mostly working now (with the corresponding fixes in
libdrm_radeon).

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:39:20 +02:00
Michel Dänzer
cf697e875c radeonsi: Mipmaps require memory footprint to be padded to powers of two.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:39:13 +02:00
Michel Dänzer
b7d96ca35e radeonsi: Sampler view state simplification.
We can always use the offset and tiling mode from level 0 and restrict the
first and last mipmap level to be used in the sampler resource.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:39:01 +02:00
Michel Dänzer
396af00ffe radeonsi: Untiled textures are linear aligned, not linear general.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:38:45 +02:00
Tom Stellard
cebbdd4ac2 radeon/llvm: Cleanup makefile
Hopefully, this will fix all the parallel make problems people have
been having.
2012-09-06 13:30:42 +00:00
Matt Turner
b6109de34f Remove useless checks for NULL before freeing
Same as earlier commit, except for "FREE"

This patch has been generated by the following Coccinelle semantic
patch:

// Remove useless checks for NULL before freeing
//
// free (NULL) is a no-op, so there is no need to avoid it

@@
expression E;
@@
+ FREE (E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   FREE(E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
type T;
@@
+ FREE ((T) E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   FREE((T) E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
@@
+ FREE (E);
- if (unlikely (E != NULL)) {
-   FREE (E);
- }

@@
expression E;
type T;
@@
+ FREE ((T) E);
- if (unlikely (E != NULL)) {
-   FREE ((T) E);
- }

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:50 -07:00
Matt Turner
5067506ea6 Remove useless checks for NULL before freeing
This patch has been generated by the following Coccinelle semantic
patch:

// Remove useless checks for NULL before freeing
//
// free (NULL) is a no-op, so there is no need to avoid it

@@
expression E;
@@
+ free (E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   free(E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
type T;
@@
+ free ((T) E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   free((T) E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
@@
+ free (E);
- if (unlikely (E != NULL)) {
-   free (E);
- }

@@
expression E;
type T;
@@
+ free ((T) E);
- if (unlikely (E != NULL)) {
-   free ((T) E);
- }

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:50 -07:00
Matt Turner
2b7a972e3f Don't cast the return value of malloc/realloc
This patch has been generated by the following Coccinelle semantic
patch:

// Don't cast the return value of malloc/realloc.
//
// Casting the return value of malloc/realloc only stands to hide
// errors.

@@
type T;
expression E1, E2;
@@
- (T)
(
_mesa_align_calloc(E1, E2)
|
_mesa_align_malloc(E1, E2)
|
calloc(E1, E2)
|
malloc(E1)
|
realloc(E1, E2)
)
2012-09-05 22:28:50 -07:00
Matt Turner
7c7b7b068b Remove Xcalloc/Xmalloc/Xfree calls
These calls allowed Xlib to use a custom memory allocator, but Xlib has
used the standard C library functions since at least its initial import
into git in 2003. It seems unlikely that it will grow a custom memory
allocator. The functions now just add extra overhead. Replacing them
will make future Coccinelle patches simpler.

This patch has been generated by the following Coccinelle semantic
patch:

// Remove Xcalloc/Xmalloc/Xfree calls

@@ expression E1, E2; @@
- Xcalloc (E1, E2)
+ calloc (E1, E2)

@@ expression E; @@
- Xmalloc (E)
+ malloc (E)

@@ expression E; @@
- Xfree (E)
+ free (E)

@@ expression E; @@
- XFree (E)
+ free (E)

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:49 -07:00
Vinson Lee
17a574d7cd Use the correct macro _WIN32 for Windows.
The correct predefined macro for Windows is _WIN32, not WIN32 or
__WIN32__.  _WIN32 is defined for 32-bit and 64-bit version of Windows
by both MSVC and MinGW compilers.

http://sourceforge.net/p/predef/wiki/OperatingSystems
http://msdn.microsoft.com/en-us/library/b0084kay.aspx

This patch also fixes a MinGW automake build error.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:14:32 -07:00
Tom Stellard
d220e2de7f radeon/llvm: Fix operand ordering for V_CNDMASK_B32
This fixes several hundred piglit tests.
2012-09-05 13:17:49 -04:00
Tom Stellard
12d3d6f6ab radeon/llvm: Use correct float->int conversion opcode on SI.
V_CVT_I32_F32 converts floats to signed integers, but we were using
V_CVT_F32_I32 which convertes signed integers to float.
2012-09-05 13:17:17 -04:00
Tom Stellard
446d19c12a radeon/llvm: Fix lowering of SI_V_CNDLT
SREG_LIT_0 is a scalar register, so it can only be used in the
first argument of vector instructoins.
2012-09-04 14:21:10 -04:00
Tom Stellard
f9fede884b radeon/llvm: Fix encoding of V_CNDMASK_B32
The CodeEmitter was not setting the VGPR bit for src0, because the
instruction definition had the VCC register in the src0 slot, instead of
the actual src0 register.  This has been fixed by moving the VCC
register to the end of the operand list.
2012-09-04 14:21:10 -04:00
Vincent Lejeune
8eaa36317a radeon/llvm: do not convert f32 operand of select_cc node
v2:-use camel coding style

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:54:37 +02:00
Vincent Lejeune
a4325b3229 radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)
v2:-wrap line at 80 characters

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:54:01 +02:00
Vincent Lejeune
d9e135e18c radeon/llvm: support setcc on f32
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:52:53 +02:00
Vincent Lejeune
a383142436 radon/llvm: br_cc f32 now lowered without cast
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:50:44 +02:00
Vincent Lejeune
6a85725f13 radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and use
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:44:48 +02:00