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radeon/llvm: Extend SI EXEC register support.

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Add 32 bit lo and hi variants, and binary encodings.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Michel Dänzer 2012-08-29 18:52:53 +02:00 • committed by Michel Dänzer
parent 2baaa5c7eb
commit ab162f80c3
2 changed files with 7 additions and 2 deletions
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3
src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
View file

@ -281,6 +281,9 @@ unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const {
unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
switch (reg) {
case AMDGPU::M0: return 124;
case AMDGPU::EXEC: return 126;
case AMDGPU::EXEC_LO: return 126;
case AMDGPU::EXEC_HI: return 127;
case AMDGPU::SREG_LIT_0: return 128;
case AMDGPU::SI_LITERAL_CONSTANT: return 255;
default: return getHWRegNum(reg);

6
src/gallium/drivers/radeon/SIGenRegisterInfo.pl
View file

@ -88,7 +88,9 @@ class SGPR_256 <bits<8> num, string name, list<Register> subregs> :
SI_256 <name, subregs>;
def VCC : SIReg<"VCC">;
def EXEC : SIReg<"EXEC">;
def EXEC_LO : SIReg<"EXEC LO">;
def EXEC_HI : SIReg<"EXEC HI">;
def EXEC : SI_64<"EXEC", [EXEC_LO,EXEC_HI]>;
def SCC : SIReg<"SCC">;
def SREG_LIT_0 : SIReg <"S LIT 0">;
def SI_LITERAL_CONSTANT : SIReg<"LITERAL CONSTANT">;
@ -141,7 +143,7 @@ for (my $i = 0; $i < $VGPR_COUNT; $i++) {
print <<STRING;
def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
(add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0)
(add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0, EXEC_LO, EXEC_HI)
>;
def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,