Fixes UBSan error with thewitness/005aa77325a11410:
runtime error: left shift of 15 by 28 places cannot be represented in type 'int'
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37055>
Fix UBSan error:
runtime error: signed integer overflow: 2147483647 + 32 cannot be represented in type 'int'
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37055>
It seems GCC+AddressSanitizer calls open and readlink after
destroy_shim(), so those need to still work.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37055>
This is more thread safe.
This is still broken, because another thread could use the global
variables after inited is set but before the shim is fully initialized,
but I guess it's better than before.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37055>
The non-compute end flag should be INTEL_DS_TRACEPOINT_FLAG_END_OF_PIPE.
This fixes the broken anv utrace for anything non-compute that can
potentially overlap (execute in parallel).
Fixes: 6281b207db ("anv: add tracepoints timestamp mode for empty dispatches")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37155>
ENABLE_DRM_AMDGPU must be defined when amdgpu_virtio is enabled;
otherwise, vdrm and amdgpu_virtio will have different definitions of
struct virgl_renderer_capset_drm. As a result, on amdgpu_virtio side,
the content of struct vdrm_device will be corrupted.
Thanks Honglei Huang <honglei1.huang@amd.com> for pointing out the
different definitions of struct virgl_renderer_capset_drm.
Cc: mesa-stable
Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37023>
Layered surfaces (array textures) with video encode/decode usage bits
will have their slices aligned to make them addressable to the media
engine. Multi-planar layered surfaces will be stored with their slices
interleaved so that a relative offset can be programmed between the
gamma and chroma slices.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35651>
Adds support for creating layered surfaces with slices that are addressable
to the media engine for video encoding and decoding.
Co-authored-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35651>
All shaders are allocated in the 32-bit addr space. To avoid an issue
with alignment, and also for future work, there is an unused user SGPR.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37133>
We are going to add 16 mesh shader states, but existing
states run out of all bits of uint64_t. So use bitset to
extend the capacity.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36976>
Pre-rasterization stages need a CS stall if they need to wait on the
flushes from a PIPE_CONTROL.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37132>
Fixes some warnings.
21 | pub fn new(data: &[u8]) -> Reader {
| ^^^^^ ------ the same lifetime is hidden here
| |
| the lifetime is elided here
|
= help: the same lifetime is referred to in inconsistent ways, making the signature confusing
= note: `#[warn(mismatched_lifetime_syntaxes)]` on by default
help: use `'_` for type paths
|
21 | pub fn new(data: &[u8]) -> Reader<'_> {
| ++++
Reviewed-by: David Gilhooley <djgilhooley.gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37097>
With the threaded submit code, there's a small window where
the fence can be signalled but the buffer lists cleanup code
from amdgpu_cs_submit_ib has not executed yet.
This is harmless in general, because num_active_ioctls is
an optimization.
When the glFinish is called though, it's best to avoid this
inconsistencies because it can create odd behavior as shown
by the flakes being fixed by this commit.
The test runs a query, uses glFinish and expect the results
to be available. Since results availability depends on
num_active_ioctls, it made the test flaky.
Fix this by syncing when PIPE_FLUSH_HINT_FINISH is set.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36930>
musl removed the LFS64 APIs like mmap64(), which were intended to be a
transitional measure multiple decades ago, causing a build failure
here. Since virtio-gpu sizes and offsets are 64-bit, we do still want
to make sure that we're using 64-bit mmap here, so I've added
-D_FILE_OFFSET_BITS=64, which will ensure that off_t is always 64-bit
in gfxstream guest, and which is generally the modern solution here.
With this change, I am able to build gfxstream with musl.
Fixes: fec8e296a3 ("Make VirtGpu* interfaces")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37086>
Using __attribute__((overloadable)) when declaring nir ops with
variable-width params in clc results in their symbol names being (IA64)
mangled; this change enables the mangled names to be handled when later
lowering the calls.
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36873>
