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radv/rt: use ACCESS_CAN_REORDER when loading SBT entries

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Totals from 56 (0.07% of 79839) affected shaders: (Navi48)

Instrs: 2790220 -> 2790130 (-0.00%); split: -0.00%, +0.00%
CodeSize: 14704952 -> 14704292 (-0.00%)
Latency: 13994383 -> 13953444 (-0.29%); split: -0.29%, +0.00%
InvThroughput: 2717973 -> 2710748 (-0.27%); split: -0.27%, +0.00%
VClause: 68783 -> 68687 (-0.14%)
SClause: 51910 -> 52007 (+0.19%)
Copies: 223192 -> 223190 (-0.00%); split: -0.01%, +0.01%
VALU: 1557513 -> 1557451 (-0.00%); split: -0.00%, +0.00%
VMEM: 118789 -> 118692 (-0.08%)
SMEM: 66498 -> 66595 (+0.15%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36933>
This commit is contained in:
Daniel Schürmann 2025-08-22 12:16:09 +02:00 • committed by Marge Bot
parent d0b134a71e
commit fcf8899c9e
1 changed files with 4 additions and 2 deletions
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6
src/amd/vulkan/nir/radv_nir_rt_shader.c
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@ -376,9 +376,11 @@ load_sbt_entry(nir_builder *b, const struct rt_variables *vars, nir_def *idx, en
nir_def *addr = nir_iadd(b, desc, nir_u2u64(b, nir_iadd_imm(b, nir_imul(b, idx, stride), offset)));
if (offset == SBT_RECURSIVE_PTR) {
nir_store_var(b, vars->shader_addr, nir_build_load_global(b, 1, 64, addr), 1);
nir_store_var(b, vars->shader_addr,
nir_build_load_global(b, 1, 64, addr, .access = ACCESS_CAN_REORDER | ACCESS_NON_WRITEABLE), 1);
} else {
nir_store_var(b, vars->idx, nir_build_load_global(b, 1, 32, addr), 1);
nir_store_var(b, vars->idx,
nir_build_load_global(b, 1, 32, addr, .access = ACCESS_CAN_REORDER | ACCESS_NON_WRITEABLE), 1);
}
nir_def *record_addr = nir_iadd_imm(b, addr, RADV_RT_HANDLE_SIZE - offset);