Commit graph

14805 commits

Author SHA1 Message Date
Marek Olšák
724b6d667c amd: add gfx12 register definitions
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29007>
2024-05-11 22:14:05 -04:00
Marek Olšák
ff47395757 amd: import gfx12 addrlib
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29007>
2024-05-11 22:14:05 -04:00
Dr. David Alan Gilbert
8b6b327d1b treewide: Cleanup unused structs
vk/wsi: Remove unused struct 'wsi_headless_format'

'wsi_headless_format' appears unused, and seems
to have been since initial commit.

radv: Remove unused struct 'blit_region'

'blit_region' appears unused, I think since initial commit.

r600: Remove unused structs

'eg_interp' and 'r600_shader_src' are unused.
I think they are just leftovers from the cleanup
in 20e6c31ba6.

i915: Remove unused struct 'i915_tracked_hw_state'

'i915_tracked_hw_state' appears unused. I think it's just
a leftover from 179cb58795.

llvmpipe: Remove unused struct 'linear_interp'

'linear_interp' doesn't ever seem to have been used.

radeonsi: Remove unused struct 'texture_orig_info'

'texture_orig_info' seems unused, I think since 46b2b3bda8.

svga: Remove unused struct 'svga_3d_invalidate_gb_image'

'svga_3d_invalidate_gb_image' appears unused since 1942c06f9c.
Remove it.

nir: Remove unused struct 'split_struct_state'

'split_struct_state' looks unused since the original commit.

Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29105>
2024-05-11 17:30:59 +00:00
Eric Engestrom
320c0b44f4 radv/ci: add navi21 flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29141>
2024-05-10 22:52:35 +00:00
Rhys Perry
75532d8687 aco: add wait_imm::unpack and wait_imm::max
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28981>
2024-05-10 11:53:08 +00:00
Rhys Perry
c894c9ab1b aco/stats: refactor for indexable wait_imm
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28981>
2024-05-10 11:53:08 +00:00
Rhys Perry
f3e461d643 aco/waitcnt: refactor for indexable wait_imm
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28981>
2024-05-10 11:53:08 +00:00
Rhys Perry
ff2e3ef5eb aco/waitcnt: add target_info
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28981>
2024-05-10 11:53:08 +00:00
Rhys Perry
20b4e30e25 aco: make wait_imm indexable
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28981>
2024-05-10 11:53:08 +00:00
Rhys Perry
5b1b09ad42 aco/waitcnt: fix DS/VMEM ordered writes when mixed
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28981>
2024-05-10 11:53:08 +00:00
Rhys Perry
16eae62f0d aco/stats: don't use VS counter pre-GFX10
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28981>
2024-05-10 11:53:08 +00:00
Rhys Perry
16a9f6e2a4 aco/stats: fix s_waitcnt parsing
This was broken for GFX11 (s_waitcnt encoding changed) and s_waitcnt_vscnt
(waited for vm/lgkm/exp to be 0).

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28981>
2024-05-10 11:53:07 +00:00
Samuel Pitoiset
43fbbc0732 radv: track and bind more VRS states from the graphics pipeline
This doesn't change anything but this will allow us to emit all
graphics shaders from the cmdbuf.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29103>
2024-05-09 08:15:56 +00:00
Samuel Pitoiset
8c17b05615 radv: do not emit non-context registers to radv_pipeline::ctx_cs
These registers don't cause context rolls.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29103>
2024-05-09 08:15:56 +00:00
Samuel Pitoiset
24814be08a radv: stop recomputing the last VGT API stage when emitting graphics shaders
The last VGT shader is already set correctly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29103>
2024-05-09 08:15:56 +00:00
Samuel Pitoiset
6753f981b6 radv: remove unused parameter to radv_pipeline_emit_pm4()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29103>
2024-05-09 08:15:56 +00:00
Samuel Pitoiset
c6a22dd05c radv: precompute NGG register values
To make emission faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29031>
2024-05-09 06:29:29 +00:00
Samuel Pitoiset
751e5d8bd7 radv: move common registers between VS/GS and NGG
For more clarity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29031>
2024-05-09 06:29:29 +00:00
Faith Ekstrand
ac500495ac radv: Use vk_physical_device_get_spirv_capabilities()
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905>
2024-05-09 01:14:23 +00:00
Faith Ekstrand
c1eaa03904 spirv: Drop the SubgroupUniformControlFlow check
It's just a vtn_fail_if() and there's no actual cap for it.  It's not
really gaining us much to have the check.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905>
2024-05-09 01:14:22 +00:00
Faith Ekstrand
eed3b56402 spirv: Move the old AMD extensions out of capabilities
These aren't real capabilities.  They control whether or not we turn on
the extended instruction sets for these instruction types.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905>
2024-05-09 01:14:22 +00:00
Georg Lehmann
be7c137229 aco/gfx11+: optimize v_fma_mix throughput
Foz-DB Navi31:
Totals from 18677 (23.58% of 79206) affected shaders:
Latency: 83613889 -> 83558801 (-0.07%)
InvThroughput: 12696661 -> 12635199 (-0.48%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29047>
2024-05-08 19:36:07 +00:00
Samuel Pitoiset
1173058002 radv: add a new mechanism for tracking registers per cmdbuf
We already track a couple of registers per cmdbuf and this introduces
a generic mechanism, instead of having a bunch of last_xxx fields.

Loosely based on RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28644>
2024-05-08 11:45:52 +00:00
Sergi Blanch Torne
72b3c2e4ba ci: identify and label S3 buckets
As for the S3 bucket where the kernel image is stored has been identified and
labeled, the other buckets in use can also be identified and labeled.

cc: mesa-stable

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Co-developed-by: Guilherme Gallo <guilherme.gallo@collabora.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28979>
2024-05-07 22:08:07 +00:00
chiachih
da45594c5e amd/vpelib: Bypass de/regam on HLG
- Bypass de/regam on HLG

Reviewed-by: Jesse Agate <jesse.agate@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
---

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28972>
2024-05-07 20:43:02 +00:00
chiachih
88b43f7174 amd/vpelib: Fix blndgam bypass flag assignment
- Fix blndgam bypass flag assignment

Reviewed-by: Tiberiu Visan <Tiberiu.Visan@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
---

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28972>
2024-05-07 20:43:02 +00:00
chiachih
921f0afe42 amd/vpelib: Fix Color Adjustment Failing Test Cases
[Why]
test cases are failing

[How]
Fixed hue range calclation error and add brightness limit like in shader

---------

Co-authored-by: Tiberiu Visan <tiberiu.visan@amd.com>
Reviewed-by: Tiberiu Visan <Tiberiu.Visan@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Ali <nawwar.ali@amd.com>
---

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28972>
2024-05-07 20:43:02 +00:00
chiachih
5027ba64a1 amd/vpelib: Remove checks for pitch alignment
[Why]
Pitch alignment checks are inaccurate, alignment is based on elements
instead of bytes, and byte alignment is assured by addrlib. Results in
failed checks that should pass.

[How]
Remove checks.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Brendan Leder <breleder@amd.com>
---

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28972>
2024-05-07 20:43:02 +00:00
chiachih
0df1054d06 amd/vpelib: adding blend gamma bypass
- added bypass blend
- bypass blnd

Reviewed-by: Jesse Agate <jesse.agate@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Tiberiu Visan <tvisan@amd.com>
---

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28972>
2024-05-07 20:43:02 +00:00
chiachih
0e6df4d458 amd/vpelib: Remove support for non-linear FP16
- Remove support for non-linear FP16

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
---

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28972>
2024-05-07 20:43:02 +00:00
chiachih
acad1328a1 amd/vpelib: Remove gamma cached table
- Remove degam/regam cached tables
- Calculate degam/regam parameters on the fly
- Remove force_tf_calculation debug flag

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
---

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28972>
2024-05-07 20:43:02 +00:00
chiachih
7a41fb59d3 amd/vpelib: Remove linear_0_125 TF
- Remove TRANSFER_FUNC_LINEAR_0_125 transfer function
- Rename TRANSFER_FUNC_LINEAR_0_1 to TRANSFER_FUNC_LINEAR

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
---

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28972>
2024-05-07 20:43:02 +00:00
chiachih
39b08da80a amd/vpelib: Resolve mismatch with shader
Shader in SDR mode with NV12 input bypasses both primary and gamma
conversions. Since in this case for RGB output p601 primary can be
set for the output primary, vpe should be able to set that primary for
output as well.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
---

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28972>
2024-05-07 20:43:02 +00:00
Samuel Pitoiset
31b039d8b7 radv: advertise VK_KHR_dynamic_rendering_local_read
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27263>
2024-05-07 10:35:04 +00:00
Samuel Pitoiset
c533a79878 radv: implement VK_KHR_dynamic_rendering_local_read
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27263>
2024-05-07 10:35:04 +00:00
Samuel Pitoiset
53a142ad23 aco: add support for remapping color attachments
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27263>
2024-05-07 10:35:04 +00:00
Samuel Pitoiset
c9162034bc radv: precompute DB_SHADER_CONTROL for fragment shaders later
To regroup all precomputed register values.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29022>
2024-05-06 18:00:02 +00:00
Samuel Pitoiset
c658ed5136 radv: precompute vertex shader register values
To make emission faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29022>
2024-05-06 18:00:02 +00:00
Samuel Pitoiset
4b53d36f0d radv: precompute legacy GS register values
To make emission faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29022>
2024-05-06 18:00:02 +00:00
Samuel Pitoiset
fa9b0ee86c radv: precompute mesh shader register values
To make emission faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29022>
2024-05-06 18:00:02 +00:00
Samuel Pitoiset
7f7ef10bea radv: precompute fragment shader register values
To make emission faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29022>
2024-05-06 18:00:02 +00:00
Samuel Pitoiset
e5bc4d85bb radv: precompute existing legacy GS register values later
To precompute all registers at the same place.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29022>
2024-05-06 18:00:02 +00:00
Georg Lehmann
e7b942393a aco/tests: simplify small constant copy test
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29045>
2024-05-06 13:38:14 +00:00
Georg Lehmann
44cc0d31b8 aco/gfx10: use v_add_u16 with literal for constant copies
This also means the v_perm_b32 path is now unused.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29045>
2024-05-06 13:38:14 +00:00
Georg Lehmann
7823065f64 aco/gfx11+: use v_cvt_pk_u8_f32 for 8bit constant copies
Foz-DB Navi31:
Totals from 201 (0.25% of 79395) affected shaders:
Instrs: 186869 -> 186857 (-0.01%)
CodeSize: 1026760 -> 1026700 (-0.01%); split: -0.01%, +0.00%
Latency: 2302050 -> 2301969 (-0.00%)
InvThroughput: 739466 -> 739431 (-0.00%)
Copies: 26467 -> 26454 (-0.05%)
VALU: 93529 -> 93516 (-0.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29045>
2024-05-06 13:38:14 +00:00
Samuel Pitoiset
92337aff03 radv: split cmdbuf dirty flags into dirty/dirty_dynamic
We are out of bits.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29039>
2024-05-06 08:33:37 +02:00
Georg Lehmann
603982ea80 nir/opt_16bit_tex_image: optimize packed conversions too
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28730>
2024-05-04 15:01:45 +00:00
Georg Lehmann
e63afdc681 radv: always run nir_opt_16bit_tex_image
The pass can optimize pack_half and constants sources even when
no 16bit instructions exist.

Foz-DB Navi21:
Totals from 3042 (3.83% of 79395) affected shaders:
MaxWaves: 69039 -> 69031 (-0.01%); split: +0.01%, -0.02%
Instrs: 2292054 -> 2291874 (-0.01%); split: -0.03%, +0.02%
CodeSize: 12567868 -> 12544888 (-0.18%); split: -0.23%, +0.05%
VGPRs: 145384 -> 145352 (-0.02%); split: -0.06%, +0.04%
SpillSGPRs: 451 -> 452 (+0.22%)
Latency: 23546543 -> 23536416 (-0.04%); split: -0.07%, +0.03%
InvThroughput: 5180446 -> 5164437 (-0.31%); split: -0.35%, +0.04%
VClause: 50537 -> 50535 (-0.00%); split: -0.05%, +0.04%
SClause: 84726 -> 84750 (+0.03%); split: -0.04%, +0.06%
Copies: 140384 -> 140421 (+0.03%); split: -0.34%, +0.37%
Branches: 40412 -> 40413 (+0.00%)
PreVGPRs: 120213 -> 120262 (+0.04%); split: -0.03%, +0.07%
VALU: 1607545 -> 1607593 (+0.00%); split: -0.03%, +0.03%
SALU: 215846 -> 215837 (-0.00%); split: -0.03%, +0.02%

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28730>
2024-05-04 15:01:44 +00:00
Georg Lehmann
3a35522c8a radv, radeonsi: don't use D16 for f2f16_rtz
D16 rounds towards zero for fp32 -> fp16, but for fixed point it rounds to
nearest even in fp16. MIMG without D16 also rounds to nearest even, but in fp32.
This means D16 and f2f16_rtz(tex@32) can produce different results.

Sadly this also means we can never use d16 if fp16 rounding isn't undefined.

Cc: mesa-stable

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28730>
2024-05-04 15:01:44 +00:00
Georg Lehmann
4287358f59 ac/nir: explicitly use pack_half_2x16_rtz
rtz matters for constant folding.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28730>
2024-05-04 15:01:44 +00:00