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radv: track and bind more VRS states from the graphics pipeline

Browse source 
This doesn't change anything but this will allow us to emit all
graphics shaders from the cmdbuf.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29103>
This commit is contained in:
Samuel Pitoiset 2024-04-30 11:37:13 +02:00 • committed by Marge Bot
parent 8c17b05615
commit 43fbbc0732
4 changed files with 26 additions and 14 deletions
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10
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -7157,7 +7157,9 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
cmd_buffer->state.ia_multi_vgt_param = graphics_pipeline->ia_multi_vgt_param;
cmd_buffer->state.uses_out_of_order_rast = graphics_pipeline->uses_out_of_order_rast;
cmd_buffer->state.uses_vrs = graphics_pipeline->uses_vrs;
cmd_buffer->state.uses_vrs_attachment = graphics_pipeline->uses_vrs_attachment;
cmd_buffer->state.uses_vrs_coarse_shading = graphics_pipeline->uses_vrs_coarse_shading;
cmd_buffer->state.uses_dynamic_vertex_binding_stride =
!!(graphics_pipeline->dynamic_states & (RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE | RADV_DYNAMIC_VERTEX_INPUT));
break;
@ -9544,8 +9546,9 @@ radv_emit_graphics_shaders(struct radv_cmd_buffer *cmd_buffer)
radv_emit_vgt_shader_config(device, cs, &vgt_shader_cfg_key);
if (pdev->info.gfx_level >= GFX10_3) {
gfx103_emit_vgt_draw_payload_cntl(cs, cmd_buffer->state.shaders[MESA_SHADER_MESH], false);
gfx103_emit_vrs_state(device, cs, NULL, false, false, false);
gfx103_emit_vgt_draw_payload_cntl(cs, cmd_buffer->state.shaders[MESA_SHADER_MESH], cmd_buffer->state.uses_vrs);
gfx103_emit_vrs_state(device, cs, cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT],
cmd_buffer->state.uses_vrs_coarse_shading, last_vgt_shader->info.force_vrs_per_vertex);
}
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_GRAPHICS_SHADERS;
@ -12451,6 +12454,9 @@ radv_reset_pipeline_state(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoin
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
}
cmd_buffer->state.uses_vrs = false;
cmd_buffer->state.uses_vrs_coarse_shading = false;
cmd_buffer->state.emitted_graphics_pipeline = NULL;
}
break;

2
src/amd/vulkan/radv_cmd_buffer.h
View file

@ -450,7 +450,9 @@ struct radv_cmd_state {
bool uses_baseinstance;
bool uses_out_of_order_rast;
bool uses_vrs;
bool uses_vrs_attachment;
bool uses_vrs_coarse_shading;
bool uses_dynamic_patch_control_points;
bool uses_dynamic_vertex_binding_stride;
};

20
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -3554,13 +3554,13 @@ gfx103_pipeline_vrs_coarse_shading(const struct radv_device *device, const struc
void
gfx103_emit_vrs_state(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, const struct radv_shader *ps,
bool enable_vrs, bool enable_vrs_coarse_shading, bool force_vrs_per_vertex)
bool enable_vrs_coarse_shading, bool force_vrs_per_vertex)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
uint32_t mode = V_028064_SC_VRS_COMB_MODE_PASSTHRU;
uint8_t rate_x = 0, rate_y = 0;
if (!enable_vrs && enable_vrs_coarse_shading) {
if (enable_vrs_coarse_shading) {
/* When per-draw VRS is not enabled at all, try enabling VRS coarse shading 2x2 if the driver
* determined that it's safe to enable.
*/
@ -3589,9 +3589,7 @@ gfx103_emit_vrs_state(const struct radv_device *device, struct radeon_cmdbuf *ct
}
static void
radv_pipeline_emit_pm4(const struct radv_device *device, struct radv_graphics_pipeline *pipeline,
const struct vk_graphics_pipeline_state *state)
radv_pipeline_emit_pm4(const struct radv_device *device, struct radv_graphics_pipeline *pipeline)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_shader *last_vgt_shader = radv_get_last_vgt_shader(pipeline);
@ -3641,11 +3639,9 @@ radv_pipeline_emit_pm4(const struct radv_device *device, struct radv_graphics_pi
radv_emit_vgt_shader_config(device, ctx_cs, &vgt_shader_key);
if (pdev->info.gfx_level >= GFX10_3) {
const bool enable_vrs = radv_is_vrs_enabled(state);
gfx103_emit_vgt_draw_payload_cntl(ctx_cs, pipeline->base.shaders[MESA_SHADER_MESH], enable_vrs);
gfx103_emit_vrs_state(device, ctx_cs, pipeline->base.shaders[MESA_SHADER_FRAGMENT], enable_vrs,
gfx103_pipeline_vrs_coarse_shading(device, pipeline), pipeline->force_vrs_per_vertex);
gfx103_emit_vgt_draw_payload_cntl(ctx_cs, pipeline->base.shaders[MESA_SHADER_MESH], pipeline->uses_vrs);
gfx103_emit_vrs_state(device, ctx_cs, pipeline->base.shaders[MESA_SHADER_FRAGMENT],
pipeline->uses_vrs_coarse_shading, pipeline->force_vrs_per_vertex);
}
pipeline->base.ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
@ -3965,7 +3961,9 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
pipeline->force_vrs_per_vertex = pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.force_vrs_per_vertex;
pipeline->rast_prim = vgt_gs_out_prim_type;
pipeline->uses_out_of_order_rast = state.rs->rasterization_order_amd == VK_RASTERIZATION_ORDER_RELAXED_AMD;
pipeline->uses_vrs = radv_is_vrs_enabled(&state);
pipeline->uses_vrs_attachment = radv_pipeline_uses_vrs_attachment(pipeline, &state);
pipeline->uses_vrs_coarse_shading = !pipeline->uses_vrs && gfx103_pipeline_vrs_coarse_shading(device, pipeline);
pipeline->base.push_constant_size = pipeline->layout.push_constant_size;
pipeline->base.dynamic_offset_count = pipeline->layout.dynamic_offset_count;
@ -3974,7 +3972,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
radv_pipeline_init_extra(pipeline, extra, &state);
}
radv_pipeline_emit_pm4(device, pipeline, &state);
radv_pipeline_emit_pm4(device, pipeline);
return result;
}

8
src/amd/vulkan/radv_pipeline_graphics.h
View file

@ -117,9 +117,15 @@ struct radv_graphics_pipeline {
/* Whether the pipeline uses out-of-order rasterization. */
bool uses_out_of_order_rast;
/* Whether the pipeline uses VRS. */
bool uses_vrs;
/* Whether the pipeline uses a VRS attachment. */
bool uses_vrs_attachment;
/* Whether the pipeline uses VRS coarse shading internally. */
bool uses_vrs_coarse_shading;
/* For graphics pipeline library */
bool retain_shaders;
@ -634,7 +640,7 @@ void gfx103_emit_vgt_draw_payload_cntl(struct radeon_cmdbuf *ctx_cs, const struc
bool enable_vrs);
void gfx103_emit_vrs_state(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, const struct radv_shader *ps,
bool enable_vrs, bool enable_vrs_coarse_shading, bool force_vrs_per_vertex);
bool enable_vrs_coarse_shading, bool force_vrs_per_vertex);
uint32_t radv_get_vgt_gs_out(struct radv_shader **shaders, uint32_t primitive_topology);