Commit graph

37526 commits

Author SHA1 Message Date
Roland Scheidegger
dded2edf8b gallivm: fix saturated signed add / sub with llvm 9
llvm 8 removed saturated unsigned add / sub x86 sse2 intrinsics, and
now llvm 9 removed the signed versions as well - they were proposed for
removal earlier, but the pattern to recognize those was very complex,
so it wasn't done then. However, instead of these arch-specific
intrinsics, there's now arch-independent intrinsics for saturated
add / sub, both for signed and unsigned, so use these.
They should have only advantages (work with arbitrary vector sizes,
optimal code for all archs), although I don't know how well they work
in practice for other archs (at least for x86 they do the right thing).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110454

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-04-17 17:42:13 +02:00
Erik Faye-Lund
ce1761edab virgl: document potentially failing blit
This blit can fail, but this is not new; in the old version we
didn't even try to blit in this case. So let's just document the
limitation for now, and leave this for another day.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
3fdacf1c39 virgl: do color-conversion during when mapping transfer
When running on OpenGL ES, we can't just map any format for reading,
because of limitations on glReadPixels. So let's fall back to the
blit code-path, and translate the pixels to the correct format in the
end.

This fixes the remaining failures of KHR-GL32.packed_pixels.* apart
from the sRGB tests.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
9e9d9b352e virgl: only blit if resource is read
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
fba03322a2 virgl: get readback-formats from host
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
749bbd39c7 gallium/util: support translating between uint and sint formats
Without this, we can't for instance convert between r8_sint and
r8g8b8a8_sint. But that's pretty useful, so let's support it as well.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
f31b65f1c1 virgl: make sure bind is set for non-buffers
Otherwise, virglrenderer will reject the resource.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
afbd68378a virgl: support write-back with staged transfers
We currently don't support writing to resources that uses a temporary
staging-resource to resolve the pixels. If a write-bit was set, we
forgot to perform a blit back to the old resource, followed by trying to
update the wrong resource, which lacks backing-storage. The end-result
would be that nothing useful happened.

This approach also fixes a few smaller bugs, like using the wrong box
(without x y and z zeroed out), which means a partial update of a
multisampled texture could result in the wrong part of the texture being
updated.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
0bc8683ffa virgl: use pipe_box for blit dst-rect
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
121e366632 virgl: rewrite core of virgl_texture_transfer_map
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
1f27bd3f2b virgl: return error if allocating resolve_tmp fails
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
fc8b1ca33a virgl: wait for the right resource
In case we're resolving, we need to wait for the resolved resource
instead of the original one.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
6263304b2d virgl: check for readback on correct resource
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
ac932ff822 virgl: make unmap queuing a bit more straight-forward
It's hard to read the code that decides if we want to queue up an unmap
or destroy the transfer right away. So let's make it a bit simpler, by
setting a bool in case we want to queue it.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
b08e73308e virgl: simplify virgl_texture_transfer_unmap logic
There's no reason to keep an extra indentation level here, let's merge
the two if-conditions.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
7dd601a399 virgl: track full virgl_resource instead of just virgl_hw_res
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
c62434f106 virgl: tmp_resource -> templ
This isn't the temporary resource itself, it's the template that we'll
create the resource from. So let's name it appropriately.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
18a721fd56 virgl: remove pointless transfer-counter
This is only written to, never read. Let's just get rid of it.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:07 +00:00
Timothy Arceri
3c5a9ab9f0 radeonsi/nir: fix scanning of bindless images
Fixes: d62d434fe9 ("ac/nir_to_llvm: add image bindless support")
2019-04-17 09:56:56 +10:00
Kenneth Graunke
c4478889b7 iris: Add texture cache flushing hacks for blit and resource_copy_region
This is a port of Jason's 8379bff6c4
from i965 to iris.  We can't find anything relevant in the documentation
and no one we've talked to has been able to help us pin down a solution.

Unfortunately, we have to put the hack in both iris_blit() and
iris_copy_region().  st/mesa's CopyImage() implementation sometimes
chooses to use pipe->blit() instead of pipe->resource_copy_region().
For blits, we only do the hack if the blit source format doesn't match
the underlying resource (i.e. it's reinterpreting the bits).  Hopefully
this should not be too common.
2019-04-16 13:04:22 -07:00
Kenneth Graunke
33314cf410 iris: Change vendor and renderer strings
This patch changes the GL_VENDOR string from "Mesa Project" to "Intel".
This makes GLX_MESA_query_renderer report "Vendor: Intel (0x8086)"
instead of "Vendor: Mesa Project (0x8086)" which is arguably wrong.
We now also use a consistent vendor string across Windows and Linux.

It also prepends "Mesa" to the GL_RENDERER string, both to credit the
community and have a distinguishing mark between the two drivers.  We
drop "DRI" compared to i965, as it's not really that important.

Improves performance in Portal by 1.8x.  Iris is now 3.86% faster
than i965 at the portal-d1.dem timedemo on my Kabylake laptop.  One
change is that Portal selects the MapBufferRange path based on the
vendor string, and iris's BufferSubData path is still missing the
storage invalidation optimization.
2019-04-16 10:27:20 -07:00
Kenneth Graunke
4c3c417b00 iris: Move iris_debug_recompile calls before uploading.
Order of operations is important, otherwise we'll find the program we
just uploaded as the "old" compile and get confused why nothing is
different between the two keys.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-04-16 09:01:20 -07:00
Kenneth Graunke
04f97eefa3 iris: Print the reason for shader recompiles.
I was lazy earlier and hadn't bothered typing / refactoring this.
Now I'm hitting some extra recompiles and would like to see why.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-04-16 09:01:18 -07:00
Marek Olšák
4f715868a9 winsys/amdgpu: don't set GTT with GDS & OA placements on APUs
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2019-04-16 10:24:19 -04:00
Marek Olšák
d3ce8a7f6b nir: optimize gl_SampleMaskIn to gl_HelperInvocation for radeonsi when possible
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-04-16 10:24:19 -04:00
suresh guttula
d98f6380cb st/va/enc: Add support for frame_cropping_flag of VAEncSequenceParameterBufferH264
This patch will add support for frame_cropping when the input size is not
matched with aligned size. Currently vaapi driver ignores frame cropping
values provided by client. This change will update SPS nalu with proper
cropping values.

Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2019-04-16 10:15:09 -04:00
suresh guttula
05cc018ae6 radeon/vce:Add support for frame_cropping_flag of VAEncSequenceParameterBufferH264
This patch will add support for frame_cropping when the input size is not
matched with aligned size. Currently vaapi driver ignores frame cropping
values provided by client. This change will update SPS nalu with proper
cropping values.

v2: Moving default crop setting to else when enc_frame_cropping_flag is not set.

Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2019-04-16 10:15:09 -04:00
suresh guttula
8becf5b46d vl: Add cropping flags for H264
This patch adds cropping flags for H264 in pipe_h264_enc_pic_control.

Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2019-04-16 10:15:09 -04:00
Kenneth Graunke
024a57d23c iris: Make shader_perf_log print to stderr if INTEL_DEBUG=perf is set
This matches i965's behavior, and makes sure that shader compiler
messages are visible when setting INTEL_DEBUG=perf.
2019-04-15 23:33:03 -07:00
Chia-I Wu
c45c889f95 virgl: fix fence fd version check
Fixes: d1a1c21e76 ("virgl: native fence fd support")

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-15 23:25:47 +00:00
Chia-I Wu
442e75071b virgl: introduce virgl_drm_fence
virgl_drm_fence can wrap either a fence fd or a virgl_hw_res.  Because a
fence fd is cheaper than a virgl_hw_res, we use it whenever it is
available.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-15 23:25:47 +00:00
Chia-I Wu
334103efbf virgl: hide fence internals from the driver
Fence fds are cheaper than resources.  We want to let winsys make the
decision and use fence fds whenever they are supported.  This commit
prepares the work.

For the moment, we create a resource _and_ a fence fd when
supports_fences is true.  This will be fixed such that we create a
resource _or_ a fence fd.  (And because of a version check bug that we
will fix later, supports_fences is actually never true).

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-15 23:25:47 +00:00
Chia-I Wu
a23c091988 virgl: handle fence_server_sync in winsys
It does not need help from the driver.  This also fixes one issue where
the fence is ignored when the transfer queue is full.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-15 23:25:47 +00:00
Roland Scheidegger
88e0bbf24a gallivm: fix bogus assert in get_indirect_index
0 is a valid value as max index, and the code handles it fine. This isn't
commonly seen, as it will only happen with array declarations of size 1.
Fixes piglit tests/shaders/complex-loop-analysis-bug.shader_test

Fixes: a3c898dc97 "gallivm: fix improper clamping of vertex index when fetching gs inputs"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110441

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-04-16 00:49:38 +02:00
Rhys Perry
6281517f3e vc4: fix build
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 5131b7a43f ('gallium: add support for formatted image loads')
2019-04-15 23:27:21 +01:00
Kenneth Graunke
0f3dc832bc iris: Fix FLUSH_EXPLICIT handling with staging buffers.
I neglected to blit the staging buffer back to the real one at
transfer_flush_region (FlushMappedBufferRange) time.
2019-04-15 14:51:01 -07:00
Kenneth Graunke
62b2ce0592 iris: Preserve all PIPE_TRANSFER flags in xfer->usage
We need to preserve PIPE_TRANSFER_FLUSH_EXPLICIT, DISCARD_RANGE, and
so on, but don't want to pass them to iris_bo_map().  So, keep them all,
but mask them off when calling map.

Chris Wilson told me to do this a long time ago and he was right.
2019-04-15 14:51:01 -07:00
Kenneth Graunke
9c52dce6a9 iris: Actually mark blorp_copy_buffer destinations as written. 2019-04-15 14:51:01 -07:00
Dylan Baker
95aefc94a9 Delete autotools
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Matt Turner <mattst88@gmail.com>
2019-04-15 13:44:29 -07:00
Marek Olšák
de0c97c817 radeonsi: enable GL_EXT_shader_image_load_formatted
no changes - the driver doesn't use the format

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-15 16:18:07 -04:00
Rhys Perry
5131b7a43f gallium: add support for formatted image loads
v3: rebase
v3: make use of u_pipe_screen_get_param_defaults

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-04-15 16:18:07 -04:00
Bas Nieuwenhuizen
af9534b9f3 ac: Move has_local_buffers disable to radeonsi.
In radv we had a separate flag to actually use it + an env option
to experimentally use it.

The common code setting has_local_buffers to false of course broke
that experimental option.

Also the "enable on APU" did not make sense for RADV as it is still
disabled by default.

Fixes: b21a4efb55 "radv/winsys: allow local BOs on APUs"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-04-15 20:39:28 +02:00
Kenneth Graunke
8bf9b7b5b6 intel: Emit 3DSTATE_VF_STATISTICS dynamically
Pipeline statistics queries should not count BLORP's rectangles.

    (23) How do operations like Clear, TexSubImage, etc. affect the
         results of the newly introduced queries?

      DISCUSSION: Implementations might require "helper" rendering
      commands be issued to implement certain operations like Clear,
      TexSubImage, etc.

      RESOLVED: They don't. Only application submitted rendering
      commands should have an effect on the results of the queries.

Piglit's arb_pipeline_statistics_query-vert_adj exposes this bug when
the driver is hacked to always perform glBufferData via a GPU staging
copy (for debugging purposes).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-04-14 19:58:04 -07:00
Karol Herbst
14531d676b nir: make nir_const_value scalar
v2: remove & operator in a couple of memsets
    add some memsets
v3: fixup lima

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)
2019-04-14 22:25:56 +02:00
Karol Herbst
606b74035e lima: use nir_src_as_float
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-04-14 22:25:56 +02:00
Alyssa Rosenzweig
1e2cb3e964 panfrost/midgard: Use shared nir_lower_viewport_transform
v2: Run before lowering I/O.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-04-14 19:16:29 +00:00
Alyssa Rosenzweig
89b02bffcb panfrost: Cleanup indexed draw handling
As part of this cleanup, we use the newly-exposed
u_vbuf_get_minmax_index, deduplicating quite a bit of bookkeeping. We
also centralize the draw_flags tracking to make this code cleaner /
futureproofed; we have already had bugs regarding this field so we might
as well get it right now.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-14 15:25:46 +00:00
Alyssa Rosenzweig
74b17b9a9f panfrost/midgard: Drop dependence on mesa/st
This was used as a workaround for uniform sizing which was fixed in
771adffe ("st: Lower uniforms in st in the...")

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-14 15:25:46 +00:00
Mauro Rossi
1af7701666 draw: fix building error in draw_gs_init()
Fixes the following building error happening with Android build system:

external/mesa/src/gallium/auxiliary/draw/draw_gs.c:740:79:
error: address of array 'draw->gs.tgsi.machine->PrimitiveOffsets' will always evaluate to 'true' [-Werror,-Wpointer-bool-conversion]
         if (!draw->gs.tgsi.machine->Primitives[i] || !draw->gs.tgsi.machine->PrimitiveOffsets)
                                                      ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~
1 error generated.

Fixes: 7720ce3 ("draw: add support to tgsi paths for geometry streams. (v2)")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-04-14 18:07:02 +10:00
Qiang Yu
b46b661f53 lima/gpir: fix alu check miss last store slot
Fixes: 92d7ca4b1c "gallium: add lima driver"
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-04-14 12:10:23 +08:00