When a resource is un-referenced, the reference count is decremented,
and intentionally no lock is acquired. This can result in the following
race condition when a resource is created from a handle:
```
[Thread] Operation
[0] Create resource from handle for the first time, refcount set to 1
[0] resource is unreferenced, refcount is decremented to 0 (intentionally
no mutex is locked)
[0] before entering virgl_hw_res_destroy to lock
virgl_drm_winsys::bo_handles_mutex the thread yields
[1] Create resource from handle pulls the resource from
virgl_drm_winsys::bo_handles, refcount is incremented to 1
[1] resource is unreferenced, refcount is decremented to 0
[1] Enter virgl_hw_res_destroy,
[1] acquire the lock on virgl_drm_winsys::bo_handles_mutex
[1] check reference count to be 0, yes -> the resource is destroyed
[1] release the lock on virgl_drm_winsys::bo_handles_mutex
[0] Enter virgl_hw_res_destroy,
[0] acquire the lock on virgl_drm_winsys::bo_handles_mutex
[0] Here the res pointer already points to freed memory
[0] check reference count to be 0, yes -> the resource is destroyed (again!)
double free or corruption (!prev)
```
To work around this race condition, keep track of the number of times
the resource was pulled from virgl_drm_winsys::bo_handles to see whether
it has to be kept alive despite the reference count being zero.
This can be reproduced with the `spec@ext_image_dma_buf_import@ext_image_dma_buf_import-refcount-multithread`
piglit test.
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34809>
We move pan_raw_format_mask_midgard to pan_format.c instead making
pan_shader.c not depending on any GENX.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34895>
Also move bifrost_blend_type_from_nir to pan_blend.c, rename it and
makes it not GENX.
This part is related to blend so it makes more sense to have it there
and this will allow us to make pan_shader.c not GENX.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34895>
This was added in v6+ and never changed.
This will allow us to remove GENX code logic that is identical.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34895>
On v11+, because FROUND.v2f16 is gone we end up with precision issues.
We now lower ffract in bifrost_nir_algebraic instead of during common
algebraic to ensure lower_bit_size has been performed.
This fixes
"dEQP-GLES3.functional.shaders.builtin_functions.common.fract.vec2_lowp_vertex"
and
"dEQP-GLES31.functional.shaders.builtin_functions.common.fract.vec2_lowp_compute".
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Backport-to: 25.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34970>
FROUND on v11+ does not flush subnormals to zero even when configured in
the shader program header.
We now use FLUSH.ftz on the input of FROUND to ensure proper
behavior when rounding up and down with FTZ enabled.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Backport-to: 25.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34970>
Similar to indirect draw barrier, need similar fixups for conditional
rendering access.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34956>
When the hardware doesn't natively support 32-bit predication, the
driver has a fallback which allocates a 64-bit predicate to the upload
BO in order to copy the original value.
But when conditional rendering is enabled in the stateCommandBuffer
which is used by preprocess() and the execute() is recorded also in the
stateCommandBuffer. If the preprocess() is recorded in a different
cmdbuf which is submitted before the cmdbuf that contains execute(),
the fallback (ie. alloc + COPY_DATA) will be performed after. This would
cause the predicate value to be always 0.
To fix that, keep track of the user predication VA which is the only
VA that needs to be used by DGC because it reads 32-bit from the shader.
This fixes a very weird corner case with vkd3d-proton.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13143
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34953>
Only the bottom 16 bits matter of the select source matter so we can
throw away the top 16 bits and avoid any i20 encoding issues. All of
the back-ends were already doing this except SM70 which has 32-bit
immediates anyway. However, doing it in a common place where it's
documented is better than skattering it everywhere. Also, doing it as
part of legalization ensures that we see the same thing in the
post-legalize IR as gets encoded.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34678>
Every back-end has code to mask these because the hardware only has
limited encoding space. However, this can be done as a common
legalization operation and doing so means that our post-legalize IR
matches what actually gets encoded.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34678>
SM20 was smart enough to reduce shift immediates instead of just
detecting i20 overflow and adding copies. This adds helpers to make
this easier and propagates the improvement out to all the back-ends.
Even though it isn't necessary on Volta+, we might as well do it there
for consistency and because smaller shift values are easier to read in
the final assembly.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34678>
The checked_shr wasn't returning the correct value if .wrap was not set.
We also weren't checking this case in the unit tests so we missed it.
While we're here, get rid of a bunch of pointhess `as u64` as well.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34678>
As other video memories for AV1 are already allocated for the maximum
sizes, now it does the same for MV buffers too.
This fixes a bunch of artifacts of AV1 playing.
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34866>
Reduction ops don't return anything, including predicates. On Turing
through Hopper, this doesn't matter because these bits are ignored.
However, Blackwell uses those bits to adjust address calculations for
reduction ops.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34910>
We had a bool for most of them and an enum for OpTld4. Now we have an
enum for all of them and we just reserve PerPx for OpTld4. While we're
here, rework printing to put the "." in the enum display method.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34910>
Pre-blackwell, it's ignored so we can set whatever. On Blackwell+, it
seems to be take into account somehow (more RE needed?) so we need to
set it to rZ to get the old behavior.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34910>
I can't see this in traces on Blackwell and it causes hangs.
These regs are in the hopper class headers so should be fine there.
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34910>
Now that it is possible to have more than one initrd, let's switch to
the common b2c kernel which requires two additional initrds:
* The GPU initrd which contains amdgpu, i915, nouveau, radeon, and xe,
along with their necessary firmware
* The depmod initrd which contains what's necessary to modprobe the
modules of the GPU initrd
Since the GPU initrd is huge (73 MB), let's reduce the size by dropping
all the firmware that is not related to AMD.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34881>
This saves a bit of bandwidth when we're not going to use the value.
Improves renderpass times across 4 affected traces I tested (bioshock,
stranded deep, transport fever, and godot material testers) on sysmem by
.3% +/- .1%.
A similar change for avoiding stencil reads showed no change on the one
app affected among all of our renderdoc traces, so that's left out.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34964>
The driconf options were leaked when the panvk instance was destroyed.
Fixes: aa8fec638f ("panvk: add basic driconf infrastructure")
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34986>
