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nak/sm70: Properly encode ldc on Blackwell+
Also add nvdisasm tests for ldc because it's pretty important and has lots of subtle per-SM differences. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34910>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
0b142182cb
commit
8c3ebddba3
3 changed files with 140 additions and 9 deletions
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@ -5138,7 +5138,7 @@ impl fmt::Display for LdcMode {
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}
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#[repr(C)]
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#[derive(SrcsAsSlice, DstsAsSlice)]
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#[derive(Clone, SrcsAsSlice, DstsAsSlice)]
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pub struct OpLdc {
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pub dst: Dst,
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@ -169,6 +169,101 @@ pub fn test_nop() {
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}
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}
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#[test]
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pub fn test_ldc() {
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let reg_files = [RegFile::GPR, RegFile::UGPR];
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let ur2_4 = RegRef::new(RegFile::UGPR, 2, 2);
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let cbufs = [
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(CBuf::Binding(5), "c[0x5]"),
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(CBuf::BindlessUGPR(ur2_4), "cx[ur2]"),
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];
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let mem_types = [
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(MemType::U8, ".u8"),
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(MemType::I8, ".s8"),
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(MemType::U16, ".u16"),
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(MemType::I16, ".s16"),
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(MemType::B32, ""),
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(MemType::B64, ".64"),
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(MemType::B128, ".128"),
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];
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for sm in SM_LIST {
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let mut c = DisasmCheck::new();
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for reg_file in reg_files {
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if reg_file == RegFile::UGPR && sm < 73 {
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continue;
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}
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let ldc_op_str = match reg_file {
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RegFile::GPR => "ldc",
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RegFile::UGPR => {
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if sm >= 100 {
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"ldcu"
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} else {
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"uldc"
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}
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}
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_ => panic!("Unsupported register file"),
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};
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for (cbuf, cbuf_str) in &cbufs {
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if matches!(cbuf, CBuf::BindlessUGPR(_)) && sm < 73 {
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continue;
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}
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for (mem_type, mem_type_str) in mem_types {
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if mem_type == MemType::B128
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&& (reg_file == RegFile::GPR || sm < 100)
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{
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continue;
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}
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let dst_regs = mem_type.bits().div_ceil(32);
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let r4 = RegRef::new(reg_file, 4, dst_regs as u8);
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let r4_str = format!("{}4", reg_file.fmt_prefix());
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let cb = CBufRef {
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buf: cbuf.clone(),
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offset: 0x248,
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};
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let mut instr = OpLdc {
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dst: r4.into(),
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cb: cb.into(),
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offset: 0.into(),
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mode: LdcMode::Indexed,
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mem_type,
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};
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c.push(
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instr.clone(),
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format!(
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"{ldc_op_str}{mem_type_str} {r4_str}, {cbuf_str}[0x248];"
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),
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);
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if reg_file == RegFile::GPR
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|| (sm >= 100 && matches!(cbuf, CBuf::Binding(_)))
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|| sm >= 120
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{
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let r6 = RegRef::new(reg_file, 6, 1);
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instr.offset = r6.into();
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c.push(
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instr.clone(),
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format!(
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"{ldc_op_str}{mem_type_str} {r4_str}, {cbuf_str}[{r6}+0x248];"
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),
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);
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}
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}
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}
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}
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c.check(sm);
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}
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}
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#[test]
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pub fn test_ld_st_atom() {
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let r0 = RegRef::new(RegFile::GPR, 0, 1);
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@ -105,6 +105,15 @@ impl SM70Encoder<'_> {
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}
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}
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fn set_ureg_src(&mut self, range: Range<usize>, src: &Src) {
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assert!(src.src_mod.is_none());
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match src.src_ref {
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SrcRef::Zero => self.set_ureg(range, self.zero_reg(RegFile::UGPR)),
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SrcRef::Reg(reg) => self.set_ureg(range, reg),
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_ => panic!("Not a register"),
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}
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}
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fn set_pred_dst(&mut self, range: Range<usize>, dst: &Dst) {
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match dst {
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Dst::None => self.set_pred_reg(range, self.true_reg(RegFile::Pred)),
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@ -2875,10 +2884,16 @@ impl SM70Op for OpLdc {
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match cb.buf {
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CBuf::Binding(idx) => {
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if self.is_uniform() {
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e.set_opcode(0xab9);
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if e.sm >= 100 {
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e.set_opcode(0x7ac);
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e.set_bit(91, true);
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e.set_ureg_src(24..32, &self.offset);
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} else {
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e.set_opcode(0xab9);
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e.set_bit(91, false);
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assert!(self.offset.is_zero());
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}
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e.set_udst(&self.dst);
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assert!(self.offset.is_zero());
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assert!(self.mode == LdcMode::Indexed);
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} else {
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e.set_opcode(0xb82);
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@ -2894,16 +2909,28 @@ impl SM70Op for OpLdc {
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LdcMode::IndexedSegmentedLinear => 3_u8,
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},
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);
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e.set_bit(91, false); // Bound
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}
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e.set_field(54..59, idx);
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e.set_bit(91, false); // Bound
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}
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CBuf::BindlessUGPR(handle) => {
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if self.is_uniform() {
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e.set_opcode(0xab9);
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if e.sm >= 100 {
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e.set_opcode(0xbac);
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} else {
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e.set_opcode(0xab9);
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}
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e.set_udst(&self.dst);
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assert!(self.offset.is_zero());
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if e.sm >= 120 {
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e.set_ureg_src(64..72, &self.offset);
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} else if e.sm >= 100 {
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// Blackwell A adds the source but it has to be zero
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assert!(self.offset.is_zero());
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e.set_ureg_src(64..72, &self.offset);
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} else {
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assert!(self.offset.is_zero());
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}
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} else {
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e.set_opcode(0x582);
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e.set_dst(&self.dst);
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@ -2912,15 +2939,24 @@ impl SM70Op for OpLdc {
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}
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e.set_ureg(24..32, handle);
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e.set_reg_src(64..72, &self.offset);
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assert!(self.mode == LdcMode::Indexed);
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e.set_bit(91, true); // Bindless
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}
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CBuf::BindlessSSA(_) => panic!("SSA values must be lowered"),
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}
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e.set_field(38..54, cb.offset);
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if e.sm >= 100 && self.is_uniform() {
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e.set_field(37..54, cb.offset);
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} else {
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e.set_field(38..54, cb.offset);
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}
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e.set_mem_type(73..76, self.mem_type);
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if e.sm >= 120 {
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e.set_field(80..82, 0_u8); // tex/hdr_unpack
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} else if e.sm >= 100 {
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e.set_bit(80, false); // tex_unpack
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}
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}
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}
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