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Author SHA1 Message Date
Kenneth Graunke
6151eb4372 nir: Drop writemask from all Intel memory store intrinsics 
The backend has been fully ignoring all writemasks for a long time,
so it really doesn't make sense to have them on our custom intrinsics.

I'm not sure they even make sense for some of the block intrinsics.

Also, the store_ssbo -> store_ssbo_intel pass was not setting writemask
at all, leaving it at the default value of 0 (aka write nothing, if it
had been respected...)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38343>
 2025-11-11 10:55:41 +00:00
Lars-Ivar Hesselberg Simonsen
b3b6fba548 nir: Add pan intrinsics for texel buffer access 
Will be used by panfrost to access texel buffers.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37007>
 2025-11-07 17:03:53 +00:00
Konstantin Seurer
3f3faa82b8 nir/from_ssa: Stop using nir_parallel_copy_instr 
nir_parallel_copy_instr can be emulated using an intrinsic for each
entry and an array of arrays that is used by the pass to remember which
copies belong together.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36483>
 2025-11-04 18:51:50 +00:00
Marek Olšák
3e2c11597a nir: add nir_intrinsic_ssbo_descriptor_amd for lowering get_ssbo_size 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38097>
 2025-11-02 01:42:07 +00:00
Aitor Camacho
f711c3afed nir: Add KosmicKrisp required utilities 
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37520>
 2025-10-20 16:22:00 +00:00
Mary Guillemard
6f73533094 asahi,nir: Stop relying on zero and scratch page in GS/TESS code 
Introduce new NIR intrinsics to handle getting a "sink" read-only
address and another intrinsic to handle conversion of address to
read-write (allowing implementation to replace the "sink" read-only with
another address like required for Asahi)

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Mary Guillemard
1e0c18d6cf nir: Rename stat_query_address_agx to stat_query_address_poly 
This is used by the geometry lowering that we are going to move to
common code.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>
 2025-10-16 19:25:35 +00:00
Marek Olšák
3fe651f607 nir: remove load_smem_amd 
replaced by load_global_amd + ACCESS_SMEM_AMD

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:54:11 +00:00
Rhys Perry
0dd09a292b nir: add ACCESS_ATOMIC 
This is so that passes and backends can tell if a coherent load/store is
atomic or not, instead of having to assume it could be either.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36602>
 2025-10-07 17:41:30 +00:00
Simon Perretta
a1acd6f8d1 pvr, pco: add primitive support for VK_KHR_robustness2.nullDescriptor 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37512>
 2025-09-30 12:15:54 +00:00
Simon Perretta
6dc5e1e109 pco: fully support Vulkan 1.2 image atomics 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37512>
 2025-09-30 12:15:48 +00:00
Simon Perretta
b111b8a844 pvr, pco: implement prerequisites for sampleRateShading 
- Implement load_interpolated_input and friends.
- Optimize load_barycentric_* cases that can be simplified.
- Initial support for non-standard sample locations.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37540>
 2025-09-27 23:45:54 +01:00
Simon Perretta
7b7fb811ab pvr, pco: switch to clc load/store sr and idfwdf shaders 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37439>
 2025-09-22 14:52:05 +01:00
Simon Perretta
c2127bf4f7 pvr, pco: switch to usc generated clear attachment shaders 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37439>
 2025-09-22 14:52:04 +01:00
Simon Perretta
6dd0a5ee2d pvr, pco: switch to clc query shaders 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37439>
 2025-09-22 14:52:04 +01:00
Simon Perretta
3fd3d7ee69 pvr, pco: switch to clc vertex passthrough shaders 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37439>
 2025-09-22 14:52:04 +01:00
Ella Stanforth
753af683b5 pco: Switch to common alpha_to_coverage intrinsic 
Signed-off-by: Ella Stanforth <ella@igalia.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:43 +00:00
Simon Perretta
6edb72d28b pco: replace {un,}packing alu ops with intrinsics 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:19 +00:00
Simon Perretta
c3325b22d8 pco: image atomics support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:12 +00:00
Simon Perretta
a67120cda3 pvr, pco: full support for tile buffer eot handling 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:12 +00:00
Simon Perretta
59dc07e02c pco: improve image write using pck.prog 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:12 +00:00
Simon Perretta
5fa1bb9194 pvr, pco: alpha to coverage support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
22c67a3c4e pvr, pco: add dummy stores for tilebuffer-only loadops 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
297a0c269a pvr, pco: tile buffer support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
de4dd8e9ea pvr, pco: fragment shader metadata boilerplate code 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
0c7dc07c93 pvr, pco: add support for gl_FrontFacing 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
0ff8f57392 pvr, pco: simple end-of-tile/render nir shader gen 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:10 +00:00
Simon Perretta
46c9239c11 pvr, pco: initial texture gather support with gather sampler 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:10 +00:00
Simon Perretta
ac41e9dd18 pco: support combined depth/discard isp feedback 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:10 +00:00
Simon Perretta
0367dc1e42 pco, pvr: sample mask out support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:10 +00:00
Simon Perretta
486ca8bbc1 pvr, pco: basic depth feedback/discard/terminate support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:09 +00:00
Simon Perretta
3af73ef199 pco: initial image support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:09 +00:00
Simon Perretta
8b634881f8 pco: add intrinsic for loading instance num in slot 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:09 +00:00
Simon Perretta
4ca0e4991e pco, pygen: add mutex op 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:09 +00:00
Simon Perretta
5088429170 pco: basic arrayed image/sampler descriptor support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:08 +00:00
Simon Perretta
7df32ba09d pco: initial texture/sampler compiler support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:08 +00:00
Mel Henning
eba08245a8 treewide: Spell indices correctly
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
LOLed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36184>
 2025-09-08 23:03:13 +00:00
Lionel Landwerlin
afea98593e nir: add a new intrinsic for load dynamic tessellation config 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:15 +00:00
Georg Lehmann
f8633511be nir: make ballot find_lsb/msb/bit_count 32bit only 
The lowering is 32bit only too.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37178>
 2025-09-04 14:03:58 +00:00
Georg Lehmann
b8db8f877d nir: make ballot_bitfield_extract 1bit only 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37178>
 2025-09-04 14:03:57 +00:00
Georg Lehmann
ef8c364d3d nir: make inverse_ballot 1bit only 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37178>
 2025-09-04 14:03:56 +00:00
Dave Airlie
c38170452d nir: add nir_intrinsic_cmat_load_shared_nv 
This maps to NAK's OpLdsm

Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36363>
 2025-08-28 16:09:07 +02:00
Job Noorman
513412c893 nir,ir3: add offset_shift index to SSBO access intrinsics 
In ir3, SSBO offsets are in units of the accessed type size so we want
to start using the new offset_shift index.

Even though the shift is implicit for the ir3 intrinsics, we use
nir_intrinsic_copy_const_indices when creating them so we need to make
sure our indices match the ones used by the generic intrinsics.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092>
 2025-08-20 07:51:30 +00:00
Job Noorman
7cc09e9952 nir: add offset_shift intrinsic index 
For load/store intrinsics that take an offset, this specifies the amount
the offset is shifted left to calculate the final offset:

offset = (offset_src + base) << offset_shift

This is useful for backends that have memory operations that use offset
units other than bytes (i.e., where the shift is implicit).

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35092>
 2025-08-20 07:51:30 +00:00
Gert Wollny
8c65da0c9d r600/sfn: cleanup GS shader emission
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
Now that we lower all load_per_vertex_input to
r600_load_per_vertex_input we can remove some dead code
and also change the intrinsic to use only one source value.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
 2025-08-12 14:30:17 +00:00
Georg Lehmann
cd687e277f nir: add access for scratch loads 
To be able to use ACCESS_SKIP_HELPERS.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36610>
 2025-08-12 08:56:37 +00:00
John Anthony
000bd3046d nir,spirv: Add support for SPV_ARM_core_builtins 
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36019>
 2025-08-07 11:46:33 +02:00
John Anthony
a68a825aad nir,agx: unvendor core_id_agx 
core_id will be used by SPV_ARM_core_builtins

Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36019>
 2025-08-07 11:46:33 +02:00
Alyssa Rosenzweig
4f1bafa6d5 nir: drop load_sample_id_no_per_sample 
unused now.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36429>
 2025-07-30 22:13:23 +00:00
Marek Olšák
ad1cfcc841 nir: mark inverse_ballot & is_subgroup_invocation_lt_amd as CAN_REORDER 
nir_can_move_instr already ignores that this flag isn't set.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36357>
 2025-07-29 16:20:39 -04:00