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nir: add a new intrinsic for load dynamic tessellation config

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
This commit is contained in:
Lionel Landwerlin 2025-04-22 18:27:47 +03:00 • committed by Marge Bot
parent 7f12f98741
commit afea98593e
2 changed files with 5 additions and 1 deletions
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1
src/compiler/nir/nir_divergence_analysis.c
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@ -362,6 +362,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_core_count_arm:
case nir_intrinsic_load_core_max_id_arm:
case nir_intrinsic_load_warp_max_id_arm:
case nir_intrinsic_load_tess_config_intel:
is_divergent = false;
break;

5
src/compiler/nir/nir_intrinsics.py
View file

@ -2474,7 +2474,10 @@ intrinsic("load_inline_data_intel", [], dest_comp=0,
indices=[BASE],
flags=[CAN_ELIMINATE, CAN_REORDER])
# Dynamic fragment shader parameters.
# Dynamic tesselation parameters (see intel_tess_config).
system_value("tess_config_intel", 1)
# Dynamic fragment shader parameters (see intel_msaa_flags) .
system_value("fs_msaa_intel", 1)
# Per primitive remapping table offset.