Commit graph

51506 commits

Author SHA1 Message Date
Samuel Pitoiset
5bb72ff750 zink: update the CI lists for RADV
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13726>
2021-11-09 16:41:13 +00:00
Jesse Natalie
1ab906d17f d3d12: Handle non-infinite wait timeouts > 49.7 days as infinite
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12268>
2021-11-09 04:05:55 +00:00
Jesse Natalie
accd8326c5 d3d12: Fix Linux fence wait return value
zero is for success, nonzero is failure.

Fixes: 0b60d6a2 ("d3d12: Support Linux eventfds for fences")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12268>
2021-11-09 04:05:55 +00:00
Jesse Natalie
e7502c5404 d3d12: Fully init primconvert config
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13670>
2021-11-09 00:44:52 +00:00
Jesse Natalie
c151e9d087 d3d12: Hook up threaded context
Reviewed By: Bill Kristiansen <billkris@microsoft.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13670>
2021-11-09 00:44:52 +00:00
Jesse Natalie
2c90fa19a8 d3d12: Pass explicit context to pre/post draw surface blits
Reviewed By: Bill Kristiansen <billkris@microsoft.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13670>
2021-11-09 00:44:52 +00:00
Jesse Natalie
cd41ed53b2 d3d12: Use thread safe slab allocators in transfer_map handling
Reviewed By: Bill Kristiansen <billkris@microsoft.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13670>
2021-11-09 00:44:52 +00:00
Jesse Natalie
17a46e2cf9 d3d12: Inherit from threaded_transfer
Reviewed By: Bill Kristiansen <billkris@microsoft.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13670>
2021-11-09 00:44:52 +00:00
Jesse Natalie
e9a1e1c21e d3d12: Resources inherit from threaded_resource
Reviewed By: Bill Kristiansen <billkris@microsoft.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13670>
2021-11-09 00:44:52 +00:00
Jesse Natalie
a463aa0099 d3d12: Inherit from threaded_query
Reviewed By: Bill Kristiansen <billkris@microsoft.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13670>
2021-11-09 00:44:52 +00:00
Jesse Natalie
00016b4251 u_threaded_context: Support including from C++
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed By: Bill Kristiansen <billkris@microsoft.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13670>
2021-11-09 00:44:52 +00:00
Jordan Justen
7eb13fc2f2 anv,blorp,iris: Set MOCS for COMPUTE_WALKER post-sync operation
We don't current enable post sync operations, but it is probably
better to set them to "internal" MOCS than to remove the non-zero
checking for this genxml field.

Reworks:
 * Fix COMPUTE_WALKER in cmd_buffer_trace_rays (s-b Jason)

Fixes: 7b78b2fcac ("intel/genxml: Assert that all MOCS fields are non-zero on Gfx7+")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13624>
2021-11-08 23:29:51 +00:00
Jason Ekstrand
419b02c90c anv,iris: Advertise a max 3D workgroup size of 1024^3
On GFX version 12.5+ with COMPUTE_WALKER, this is the limit based on the
size of the HW packet.  On older HW, we can technically go a bit bigger
but there's not much point.  Technically, some hardware can support a
scalar workgroup size up to 2048 but most apps don't go any bigger than
1024.

As discussed on the merge request page, the current limit assumes
SIMD32, but it is unclear if we want to encourage applications to use
SIMD32 if it may lead to additional register spilling in shader
programs. Many applications have likely tuned for a limit of 1024
based on the OpenGL minimum limit, so it might not gain much by
advertising more than 1024.

Reworks:
 * Jordan: Use MIN2 and limit total invocations as well.
 * Jordan: Add second paragraph to commit message based on merge
   request discussion.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13538>
2021-11-08 23:07:42 +00:00
Mike Blumenkrantz
8626949f07 zink: flatten out draw templates a bit
having this be super granular was a neat idea, but really I don't care
even a little bit about a driver that's weirdly implementing *only*
dynamic vertex input or *only* dynamic state2

this massively cuts down the combinatorics and provides a more accurate
gauge of driver feature levels, since this is the general level of support
that they're likely to have

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13715>
2021-11-08 21:49:40 +00:00
Marek Olšák
3d80d6b696 radeonsi: enable nir_group_loads for better performance
The best case I have is one viewperf subtest getting +9% performance.

56979 shaders in 34726 tests
Totals:
SGPRS: 2667522 -> 2669178 (0.06 %)
VGPRS: 1543608 -> 1553472 (0.64 %)
Spilled SGPRs: 4090 -> 4100 (0.24 %)
Spilled VGPRs: 1600 -> 1791 (11.94 %)
Private memory VGPRs: 256 -> 256 (0.00 %)
Scratch size: 1872 -> 2076 (10.90 %) dwords per thread
Code Size: 59443980 -> 59479804 (0.06 %) bytes
Max Waves: 867280 -> 865634 (-0.19 %)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>

v2: No change in pixels but the hash changed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13604>
2021-11-08 21:20:11 +00:00
Mike Blumenkrantz
acddf83c95 zink: update radv ci passes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13716>
2021-11-08 20:02:26 +00:00
Gert Wollny
63c4c559cb virgl: obtain supported number of shader sampler views from host
Modern games may use more than 16 sampler views, so get what the host
actually supports, and default to 16 on old hosts that don't pass the
value.

Since the possible maximal value of PIPE_MAX_SHADER_SAMPLER_VIEWS doesn't
fit into an uint32_t remove the binding flags, they were only used for
releasing the sampler views, and this can be achieved differently.

v2: Fix compilation error

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: John Bates <jbates@chromium.org> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13646>
2021-11-08 19:34:30 +00:00
Pierre-Eric Pelloux-Prayer
5358d8a110 radeonsi/sqtt: reserve a vmid when sqtt is enabled
Based on https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13695

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13696>
2021-11-08 17:16:11 +00:00
Pierre-Eric Pelloux-Prayer
e26dd92957 radeonsi/sqtt: fix FINISH_DONE / BUSY usage
They're using more than a single bit so use the proper mask.

Based on https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13694

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13696>
2021-11-08 17:16:11 +00:00
Pierre-Eric Pelloux-Prayer
3de072aaec radeonsi/sqtt: fix shader stage values
shader_stages_mask and others expect MESA_SHADER_* based values,
not PIPE_SHADER_*...

Without this the fragment shader wouldn't appear in the "Pipelines"
pane of RGP.

Fixes: c276bde34a ("radeonsi/sqtt: export shader code to RGP")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13696>
2021-11-08 17:16:11 +00:00
Lionel Landwerlin
361b3fee3c intel: move away from booleans to identify platforms
v2: Drop changes around GFX_VERx10 == 75 (Luis)

v3: Replace
   (GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT)
   by
   (devinfo->platform == INTEL_PLATFORM_IVB)
   Replace
   (devinfo->ver >= 5 || devinfo->platform == INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 >= 45)
   Replace
   (devinfo->platform != INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 != 45)

v4: Fix crocus typo

v5: Rebase

v6: Add GFX3, ILK & I965 platforms (Jordan)
    Move ifdef to code expressions (Jordan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12981>
2021-11-08 16:48:06 +00:00
Mike Blumenkrantz
fbd61d2b02 zink: set new point/line caps
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13676>
2021-11-08 14:37:49 +00:00
Marek Olšák
78337728d1 radeonsi: set correct point and line limits
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13676>
2021-11-08 14:37:49 +00:00
Marek Olšák
cf9afc7b0c gallium: add missing point and line CAPs
The returned values are the same as the GL frontend.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13676>
2021-11-08 14:37:49 +00:00
Marek Olšák
b80dca86c3 gallium: rename PIPE_CAPF_MAX_POINT_WIDTH -> MAX_POINT_SIZE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13676>
2021-11-08 14:37:49 +00:00
Mike Blumenkrantz
c4d904101c aux/trace: add pipe_context::render_condition_mem
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13582>
2021-11-05 14:37:25 -04:00
Mike Blumenkrantz
f579401099 aux/trace: fix vertex state tracing
Fixes: e8cad57aa7 ("gallium/trace: add pipe_vertex_state support")

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13582>
2021-11-05 14:37:25 -04:00
Mike Blumenkrantz
810305fbed aux/trace: trace pipe_screen::is_format_supported better
storage_sample_count is important

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13582>
2021-11-05 14:37:25 -04:00
Mike Blumenkrantz
d2f3aba5f0 aux/trace: support pipe_context::get_query_result_resource
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13582>
2021-11-05 14:37:24 -04:00
Mike Blumenkrantz
58ba18474b aux/trace: fix PIPE_QUERY_PIPELINE_STATISTICS_SINGLE tracing
don't just crash, dump!

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13582>
2021-11-05 14:36:54 -04:00
Lionel Landwerlin
a543a94404 intel/dev: fix subslice/eu total computations with some fused configurations
When a device has its first slice/subslice fused off, we can't use the
number of slices/subslices to iterate the mask array.

v2: Fix spelling (Marcin)
    Use size_t for iterator (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Matt Roper <matthew.d.roper@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5601
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10015>
2021-11-05 10:22:18 +00:00
orbea
0a6f079afe build: add sha1_h for lp_texture.c
../mesa-9999/src/gallium/drivers/llvmpipe/lp_texture.c:55:10: fatal error: git_sha1.h: No such file or directory

Fixes: 1608a815e3 ("llvmpipe: add support for EXT_memory_object(_fd)")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: orbea <orbea@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13665>
2021-11-05 05:54:20 +00:00
Jordan Justen
6ffdcc335e iris: Use mi_builder in iris_load_indirect_location()
For example, this allows us to take advantage of command-streamer
based register offsets in mi_builder.

Ref: 06cf838cbd ("intel/mi_builder: Support gen11 command-streamer based register offsets")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13652>
2021-11-04 21:23:21 -07:00
Mike Blumenkrantz
833c0394e0 Revert "gallium/u_blitter: work around broken sample shading in llvmpipe and zink"
This reverts commit 8b287c3f92.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13679>
2021-11-05 02:36:32 +00:00
Mike Blumenkrantz
60a8d68285 gallivm: handle TGSI SampleId sysval
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13679>
2021-11-05 02:36:32 +00:00
Mike Blumenkrantz
64cee33984 lavapipe: add some asserts for descriptor dynamic offsets
ensure that this explodes if there aren't enough offsets

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13677>
2021-11-05 02:21:01 +00:00
Mike Blumenkrantz
8c37cd8860 zink: rework cached fbfetch descriptor fallback
this ended up being a little trickier than I thought; lazy
descriptors don't use dynamic ubo types for the push set,
which means drivers that (correctly) assert dynamic offset existence
explode because the descriptor template will never work with the
push set

the better, though slightly more annoying, option here is to use the
lazy manager's faster descriptor allocation and lesser complexity to
quickly grab a push set, then tweak the existing cached codepath slightly
in order to update a raw vkdescriptorset

Fixes: 417477f60e ("zink: always use lazy (non-push) updating for fbfetch descriptors")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13677>
2021-11-05 02:21:01 +00:00
Jesse Natalie
2d1f5e3dcb d3d12: Don't accumulate timestamp queries
If an app re-issues a timestamp query a lot, but doesn't ever ask
for the results, we could end up running off the end of our query
heap. But we don't actually need to advance/accumulate, so just
use a single entry in the heap.

Reviewed By: Bill Kristiansen <billkris@microsoft.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12920>
2021-11-05 00:44:15 +00:00
Emma Anholt
b0f2b0e980 freedreno/a5xx: Clean up a little bit of blitter array pitch setup.
We have a nice helper function for determining an array pitch.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13668>
2021-11-04 22:49:29 +00:00
Emma Anholt
b26e0cdf44 freedreno/a5xx: Try to fix drawing to z/s miplevel/layer offsets.
Terrifyingly, no testcases are fixed by this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13668>
2021-11-04 22:49:29 +00:00
Emma Anholt
99f5b7ba1e freedreno/a5xx: Remove bogus assertion about BO size.
The slice->size0 temp is being used as both the array stride (incorrectly)
and as the size of the slice (for this assert).  This assert doesn't seem
to be in the right place to me, if you want to check that offset+slice
size is < bo size, you could just do that at the end of layout setup.

This caused troubles when fixing the temp to be the actual array stride
for filling out the HW state, since then rendering to nonzero levels would
think that the rendering overflowed the BO when it doesn't.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13668>
2021-11-04 22:49:29 +00:00
Emma Anholt
03d8677bca freedreno/a6xx: Try to fix drawing to z/s miplevel/layer offsets.
Terrifyingly, no testcases are fixed by this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13668>
2021-11-04 22:49:29 +00:00
Caio Oliveira
8fc6a11f0e intel/blorp: Add option to emit packets that disable Mesh
If a driver doesn't support Mesh, don't emit anything.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13660>
2021-11-04 14:41:06 -07:00
Jesse Natalie
b34fed64fa u_prim_restart: Fix index scanning with start offset
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13681>
2021-11-04 20:39:25 +00:00
Mike Blumenkrantz
bc345281ab aux/primconvert: handle singular incomplete restarts
if no restart indices are found, this draw must be discarded to avoid
crashing later on

Fixes: 583070748c ("util/primconvert: handle rewriting of prim-restart draws with unsupported primtype")

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13630>
2021-11-04 20:12:32 +00:00
Emma Anholt
1e869e3fb4 freedreno/a5xx+: Fix missing LA formats.
GL_ARB_texture_buffer_object uses these formats, and we expose it.  Since
we didn't have the formats in the table, we we were using bad HW
texture/color formats for them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13666>
2021-11-04 19:07:54 +00:00
Emma Anholt
0e4fcda7e0 freedreno/a6xx: Don't try to generate mipmaps for SNORM with our blitter.
Since we're casting to unorm, the linear filtering will give bad results.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13666>
2021-11-04 19:07:54 +00:00
Jason Ekstrand
953a4ca6fe intel: Add has_bit6_swizzle to devinfo
There's no good reason to have this rather complex check in three
drivers.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13636>
2021-11-04 18:51:04 +00:00
Marek Olšák
74adf22a0a radeonsi: fix a typo preventing a fast depth-stencil clear
Fixes: 9defe8aca9 - radeonsi: implement fast Z/S clears using clear_buffer on HTILE

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13603>
2021-11-04 17:36:26 +00:00
Marek Olšák
c0f723ce2b radeonsi: allow and finish TC-compatible MSAA HTILE
This improves perf for Catia by 4%.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13603>
2021-11-04 17:36:26 +00:00