Commit graph

171088 commits

Author SHA1 Message Date
Alyssa Rosenzweig
55f7fd6d0d nir/opt_uniform_atomics: Handle unified atomics
This is the one place where using nir_atomic_op instead of nir_op directly is a
little annoying, since we need to translate between the two enums, but it's not
a big deal.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
b1fd8d27fc nir/lower_ssbo: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
66f1633ffd nir/lower_io: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
1609b41303 nir/lower_task_shader: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Jesse Natalie
ca5c869b6d nir: Load/store atomic op indices when lowering image intrinsics
They might not be stored in the same const index after lowering

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
97857731ce nir: Handle unified atomics in simple cases
Lots of passes can be made unified-atomics-aware simply by adding extra cases in
their switch statements. This commit fixes a bunch of passes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
ee6ddce636 ir3: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Karol Herbst
6ff97776b7 nv50/ir: Use unified atomics
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
b98b7f4d85 zink: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
ce638eafe2 aco,radv: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
0241d8894e ac/llvm: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
1e9c01523a ac/llvm: Don't handle atomic derefs
Should not be seen, already would be stubbed out.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
d0d2292ac0 ntt: Use unified atomics
Nice deduplication of the NIR->TGSI enum translation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
bd0a2b1608 gallivm: Use unified atomics
This is a huge win because gallivm duplicated the translations in a zillion
places.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
3c823351c0 pan/mdg: Use unified atomics
This doesn't actually save anything, since Italo already introduced magic macros
for this, but it ticks off one more driver on the list to convert. It's also
more legible, so that's nice :-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
133af0d6c9 pan/mdg: Fix icky formatting
clang-format butchered this initializer pretty badly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
e258083e07 pan/bi: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
f5d73a9989 agx: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
5c99507028 nir: Add pass to lower atomics to unified
In the future, we'd like to have all drivers only ingest unified atomics, and
all frontends only produce unified atomics, and garbage collect the existing
non-unified atomics. To get to that future, it's a lot nicer to convert drivers
one-by-one. Add a pass to translate old-style atomics to new-style atomics so
drivers can opt-in to the new form one-by-one. Once all drivers are converted,
we can convert producers one-by-one. Finally, we can just drop the calls to the
pass and garbage collect this pass and the old atomics. That's probably a while
out, though, so this will be out bridge to get there.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
d51bc95837 nir: Add unified atomics
Currently, we have an atomic intrinsic for each combination of memory type
(global, shared, image, etc) and atomic operation (add, sub, etc). So for m
types of memory supported by the driver and n atomic opcodes, the driver has to
handle O(mn) intrinsics. This makes a total mess in every single backend I've
looked at, without fail.

It would be a lot nicer to unify the intrinsics. There are two obvious ways:

1. Make the memory type a constant index, keep different intrinsics for
   different operations. The problem with this is that different memory types
   imply different intrinsic signatures (number of sources, etc).  As an
   example, it doesn't make sense to unify global_atomic_amd with
   global_atomic_2x32, as an example. The first takes 3 scalar sources, the
   second takes 1 vector and 1 scalar. Also, in any single backend, there are a
   lot more operations than there are memory types.

2. Make the opcode a constant index, keep different intrinsics for different
   operations. This works well, with one exception: compswap and fcompswap
   take an extra argument that other atomics don't, so there's an extra axis of
   variation for the intrinsic signatures.

So, the solution is to have 2 intrinsics for each memory type -- for atomics
taking 1 argument and atomics taking 2 respectively. Both of these intrinsics
take an nir_atomic_op enum to describe its operation. We don't use a nir_op for
this purpose, as there are some atomics (cmpxchg, inc_wrap, etc) that don't
cleanly map to any ALU op and it would be weird to force it.

The plan is to transition to these new opcodes gradually. This series adds a
lowering pass producing these opcodes from the existing opcodes, so that
backends can opt-in to the new forms one-by-one. Then we can convert backends
separately without any cross-tree flag day. Once everything is converted, we can
convert the producers and core NIR as a flag day, but we have far fewer
producers than backends so this should be fine. Finally we can drop the old
stuff.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Rhys Perry
88f6d7f4bd aco/gfx11: fix VMEM/DS->VALU WaW/RaW hazard
Previously, we could safely read/write unused lanes of VMEM/DS
destination VGPRs without waiting for the load to finish. That doesn't
seem to be the case on GFX11.

fossil-db (gfx1100):
Totals from 6698 (4.94% of 135636) affected shaders:
Instrs: 11184274 -> 11199420 (+0.14%); split: -0.00%, +0.14%
CodeSize: 57578344 -> 57638928 (+0.11%); split: -0.00%, +0.11%
Latency: 198348808 -> 198382472 (+0.02%); split: -0.00%, +0.02%
InvThroughput: 24376324 -> 24378439 (+0.01%); split: -0.00%, +0.01%
VClause: 192420 -> 192559 (+0.07%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8722
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8239
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22965>
2023-05-12 20:19:21 +00:00
Dmitry Rogozhkin
8fc5dd935f meson/vaon12: fix driver file name for mingw build
This fixes vaon12 driver file name to be consistent with libva
expectation - vaon12_drv_video.dll - without lib prefix.

Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22995>
2023-05-12 19:31:26 +00:00
Yiwei Zhang
aa57e8ef18 lvp: avoid accessing member of NULL ptr for global entries
Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22979>
2023-05-12 19:05:23 +00:00
Yiwei Zhang
5b31039033 pipe-loader: avoid undefined memcpy behavior
If either dest or src is an invalid or null pointer, the behavior is
undefined, even if count is zero.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22979>
2023-05-12 19:05:23 +00:00
Mike Blumenkrantz
d5cf6f7d2f zink: disable dynamic state exts if the previous ones aren't present
this would be weird if a driver did it

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22996>
2023-05-12 17:53:02 +00:00
Mike Blumenkrantz
6debee51f3 zink: disable have_EXT_vertex_input_dynamic_state without EDS2
this is disabled already in the draw paths but not the pipeline paths

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22996>
2023-05-12 17:53:02 +00:00
Jesse Natalie
edcecfa817 nir_lower_system_values: Add ASSERTED to assert-only variable
Fixes: 1e0e4657 ("spirv/nir: wire ray interection triangle position fetch")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22994>
2023-05-12 17:09:29 +00:00
Eric Engestrom
ef831c137f ci: replace write + cat with tee
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22945>
2023-05-12 16:36:57 +00:00
Eric Engestrom
07a8fdb9bb ci: stop marking environment variable list as executable
We're only going to read it, not execute it.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22945>
2023-05-12 16:36:57 +00:00
Eric Engestrom
0a45f9c999 ci: drop GENERATE_ENV_SCRIPT
Added in 16b417b8d6 ("ci, valve: Add the dEQP runners for
Valve CI") but never used.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22945>
2023-05-12 16:36:56 +00:00
Alyssa Rosenzweig
7dfa98abc6 nir: Use nir_block_last_phi_instr more
We have a helper, don't open code it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
2023-05-12 14:02:23 +00:00
Alyssa Rosenzweig
82430b91bb ac/llvm: Use nir_foreach_phi
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
2023-05-12 14:02:23 +00:00
Alyssa Rosenzweig
5a0223a2d4 dxil: Use nir_foreach_phi_safe
This should be faster, since we're not iterating pointlessly over all the
non-phis after the phi.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
2023-05-12 14:02:23 +00:00
Alyssa Rosenzweig
aa6bdbd54a nir: Use nir_foreach_phi(_safe)
The pattern shows up all the time open-coded. Use the macro instead.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
2023-05-12 14:02:23 +00:00
Alyssa Rosenzweig
7dc297cc14 nir: Add nir_foreach_phi(_safe) macro
Serious preprocessor voodoo here. There are two tricks here.

1. Iterating only phis. We know that phis come only at the beginning of a block,
   so all over the tree, we open-code iteration like:

      nir_foreach_instr(instr, block) {
         if (instr->type != phi)
            break;

         /* do stuff */
      }

   We can express this equivalently as

      nir_foreach_instr(instr, block)
         if (instr->type != phi)
            break;
         else {
            /* do stuff */
         }

   So, we can define a macro

      #define nir_foreach_phi(instr, block)
         if (instr->type != phi)
            break;
         else

   and then

      nir_foreach_phi(..)
         statement;

   and

      nir_foreach_phi(..) {
         ...
      }

   will expand to the right thing.

2. Automatically getting the phi as a phi. We want the instruction to go to some
   hidden variable, and then automatically insert nir_phi_instr *phi =
   nir_instr_as_phi(instr_internal); We can't do that directly, since we need to
   express the assignment implicitly in the control flow for the above trick to
   work. But we can do it indirectly with a loop initializer.

      for (nir_phi_instr *phi = nir_instr_as_phi(instr_internal); ...)

   That loop needs to break after exactly one iteration. We know that phi
   will always be non-null on its first iteration, since the original
   instruction is non-null, so we can use phi==NULL as a sentinel and express a
   one-iteration loop as for (phi = nonnull; phi != NULL; phi = NULL).

Putting these together gives the macros implemented used.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
2023-05-12 14:02:23 +00:00
Georg Lehmann
04976beac7 aco: don't apply dpp if the alu instr uses the operand twice
CP77 has a ton of fma(dpp(a), dpp(a), b).

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
2023-05-12 13:31:16 +00:00
Georg Lehmann
151bcc1e8b aco: use VOP3+DPP
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
2023-05-12 13:31:16 +00:00
Georg Lehmann
41b0eafc4b aco/ra: convert VOPC_DPP instructions without vcc to VOP3
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
2023-05-12 13:31:16 +00:00
Georg Lehmann
d32526caf2 aco: add assembler tests for VOP3(P) with DPP
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
2023-05-12 13:31:15 +00:00
Georg Lehmann
984bdc0fb1 aco/builder: support VOP3(P) with dpp
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
2023-05-12 13:31:15 +00:00
Georg Lehmann
2548f28ab3 aco/assembler: support VOP3P with DPP
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
2023-05-12 13:31:15 +00:00
Georg Lehmann
d0e73cb313 aco/optimizer: copy pass flags for newly created valu instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
2023-05-12 13:31:15 +00:00
Georg Lehmann
d27e03d719 aco/optimizer: don't use pass_flags for mad idx
fma can use DPP on GFX11+, so we want to keep the exec id in pass_flags

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
2023-05-12 13:31:15 +00:00
Georg Lehmann
7c5e8dedab aco/vn: compare all valu modifers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 9b4ea9ff90 ("aco/vn: hash opsel for VOP12C")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
2023-05-12 13:31:15 +00:00
Mike Blumenkrantz
0f5a27ca8d zink: add back some anv qbo flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22987>
2023-05-12 09:10:04 -04:00
Alyssa Rosenzweig
86a053f7b9 docs: Include ALU opcode descriptions
If we have a description for an ALU opcode in NIR, include it with our generated
HTML documentation so people don't need to go to nir_opcodes.py anyway because
the documentation is missing the documentation ;-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Tested-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22929>
2023-05-12 12:11:38 +00:00
Alyssa Rosenzweig
bd466195b9 nir: Make ALU descriptions machine-readable
We already document a lot of ALU opcodes, let's make this machine-readable so we
can put the descriptions in our generated HTML documentation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22929>
2023-05-12 12:11:38 +00:00
Alyssa Rosenzweig
6b4f00a3ac nir: Allow adding descriptions to ALU opcodes
This will let us generate nicer documentation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22929>
2023-05-12 12:11:38 +00:00
Juan A. Suarez Romero
72a84ebbd6 vc4/ci: re-enable VC4 testing
But keeps piglit's quick_gl disabled, as it contains the test causing
the GPU resets.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22982>
2023-05-12 11:10:41 +02:00
Bas Nieuwenhuizen
0a87f1b7ed amd/drm-shim: Update docs for more devices.
We don't have to update the docs for every new entry.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22975>
2023-05-12 07:44:32 +00:00