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nir: Make ALU descriptions machine-readable
We already document a lot of ALU opcodes, let's make this machine-readable so we can put the descriptions in our generated HTML documentation. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22929>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
6b4f00a3ac
commit
bd466195b9
1 changed files with 131 additions and 102 deletions
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@ -199,25 +199,28 @@ unop("mov", tuint, "src0")
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unop("ineg", tint, "-src0")
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unop("fneg", tfloat, "-src0")
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unop("inot", tint, "~src0") # invert every bit of the integer
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unop("inot", tint, "~src0", description = "Invert every bit of the integer")
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# nir_op_fsign roughly implements the OpenGL / Vulkan rules for sign(float).
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# The GLSL.std.450 FSign instruction is defined as:
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#
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# Result is 1.0 if x > 0, 0.0 if x = 0, or -1.0 if x < 0.
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#
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# If the source is equal to zero, there is a preference for the result to have
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# the same sign, but this is not required (it is required by OpenCL). If the
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# source is not a number, there is a preference for the result to be +0.0, but
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# this is not required (it is required by OpenCL). If the source is not a
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# number, and the result is not +0.0, the result should definitely **not** be
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# NaN.
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#
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# The values returned for constant folding match the behavior required by
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# OpenCL.
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unop("fsign", tfloat, ("bit_size == 64 ? " +
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"(isnan(src0) ? 0.0 : ((src0 == 0.0 ) ? src0 : (src0 > 0.0 ) ? 1.0 : -1.0 )) : " +
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"(isnan(src0) ? 0.0f : ((src0 == 0.0f) ? src0 : (src0 > 0.0f) ? 1.0f : -1.0f))"))
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"(isnan(src0) ? 0.0f : ((src0 == 0.0f) ? src0 : (src0 > 0.0f) ? 1.0f : -1.0f))"),
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description = """
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Roughly implements the OpenGL / Vulkan rules for ``sign(float)``.
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The ``GLSL.std.450 FSign`` instruction is defined as:
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Result is 1.0 if x > 0, 0.0 if x = 0, or -1.0 if x < 0.
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If the source is equal to zero, there is a preference for the result to have
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the same sign, but this is not required (it is required by OpenCL). If the
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source is not a number, there is a preference for the result to be +0.0, but
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this is not required (it is required by OpenCL). If the source is not a
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number, and the result is not +0.0, the result should definitely **not** be
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NaN.
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The values returned for constant folding match the behavior required by
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OpenCL.
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""")
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unop("isign", tint, "(src0 == 0) ? 0 : ((src0 > 0) ? 1 : -1)")
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unop("iabs", tint, "(src0 < 0) ? -src0 : src0")
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unop("fabs", tfloat, "fabs(src0)")
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@ -286,17 +289,23 @@ for src_t in [tint, tuint, tfloat, tbool]:
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dst_bit_size),
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dst_t + str(dst_bit_size), src_t, conv_expr)
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# Special opcode that is the same as f2f16, i2i16, u2u16 except that it is safe
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# to remove it if the result is immediately converted back to 32 bits again.
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# This is generated as part of the precision lowering pass. mp stands for medium
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# precision.
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unop_numeric_convert("f2fmp", tfloat16, tfloat32, opcodes["f2f16"].const_expr)
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unop_numeric_convert("i2imp", tint16, tint32, opcodes["i2i16"].const_expr)
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def unop_numeric_convert_mp(base, src_t, dst_t):
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op_like = base + "16"
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unop_numeric_convert(base + "mp", src_t, dst_t, opcodes[op_like].const_expr,
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description = """
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Special opcode that is the same as :nir:alu-op:`{}` except that it is safe to
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remove it if the result is immediately converted back to 32 bits again. This is
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generated as part of the precision lowering pass. ``mp`` stands for medium
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precision.
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""".format(op_like))
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unop_numeric_convert_mp("f2f", tfloat16, tfloat32)
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unop_numeric_convert_mp("i2i", tint16, tint32)
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# u2ump isn't defined, because the behavior is equal to i2imp
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unop_numeric_convert("f2imp", tint16, tfloat32, opcodes["f2i16"].const_expr)
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unop_numeric_convert("f2ump", tuint16, tfloat32, opcodes["f2u16"].const_expr)
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unop_numeric_convert("i2fmp", tfloat16, tint32, opcodes["i2f16"].const_expr)
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unop_numeric_convert("u2fmp", tfloat16, tuint32, opcodes["u2f16"].const_expr)
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unop_numeric_convert_mp("f2i", tint16, tfloat32)
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unop_numeric_convert_mp("f2u", tuint16, tfloat32)
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unop_numeric_convert_mp("i2f", tfloat16, tint32)
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unop_numeric_convert_mp("u2f", tfloat16, tuint32)
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# Unary floating-point rounding operations.
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@ -320,15 +329,16 @@ unop_convert("frexp_exp", tint32, tfloat, "frexp(src0, &dst);")
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unop_convert("frexp_sig", tfloat, tfloat, "int n; dst = frexp(src0, &n);")
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# Partial derivatives.
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deriv_template = """
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Calculate the screen-space partial derivative using {} derivatives of the input
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with respect to the {}-axis. The constant folding is trivial as the derivative
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of a constant is 0.
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"""
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unop("fddx", tfloat, "0.0") # the derivative of a constant is 0.
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unop("fddy", tfloat, "0.0")
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unop("fddx_fine", tfloat, "0.0")
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unop("fddy_fine", tfloat, "0.0")
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unop("fddx_coarse", tfloat, "0.0")
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unop("fddy_coarse", tfloat, "0.0")
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for mode, suffix in [("either fine or coarse", ""), ("fine", "_fine"), ("coarse", "_coarse")]:
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for axis in ["x", "y"]:
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unop(f"fdd{axis}{suffix}", tfloat, "0.0",
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description = deriv_template.format(mode, axis.upper()))
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# Floating point pack and unpack operations.
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@ -372,16 +382,18 @@ unpack_2x16("unorm")
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unpack_4x8("unorm")
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unpack_2x16("half")
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# Convert two unsigned integers into a packed unsigned short (clamp is applied).
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unop_horiz("pack_uint_2x16", 1, tuint32, 2, tuint32, """
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dst.x = _mesa_unsigned_to_unsigned(src0.x, 16);
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dst.x |= _mesa_unsigned_to_unsigned(src0.y, 16) << 16;
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""", description = """
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Convert two unsigned integers into a packed unsigned short (clamp is applied).
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""")
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# Convert two signed integers into a packed signed short (clamp is applied).
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unop_horiz("pack_sint_2x16", 1, tint32, 2, tint32, """
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dst.x = _mesa_signed_to_signed(src0.x, 16) & 0xffff;
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dst.x |= _mesa_signed_to_signed(src0.y, 16) << 16;
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""", description = """
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Convert two signed integers into a packed signed short (clamp is applied).
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""")
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unop_horiz("pack_uvec2_to_uint", 1, tuint32, 2, tuint32, """
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@ -560,8 +572,8 @@ if (src0.z >= 0 && absZ >= absX && absZ >= absY) dst.x = 4;
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if (src0.z < 0 && absZ >= absX && absZ >= absY) dst.x = 5;
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""")
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# Sum of vector components
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unop_reduce("fsum", 1, tfloat, tfloat, "{src}", "{src0} + {src1}", "{src}")
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unop_reduce("fsum", 1, tfloat, tfloat, "{src}", "{src0} + {src1}", "{src}",
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description = "Sum of vector components")
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def binop_convert(name, out_type, in_type, alg_props, const_expr, description=""):
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opcode(name, 0, out_type, [0, 0], [in_type, in_type],
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@ -683,10 +695,6 @@ if (nir_is_rounding_mode_rtz(execution_mode, bit_size)) {
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}
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""")
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# Unlike fmul, anything (even infinity or NaN) multiplied by zero is always zero.
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# fmulz(0.0, inf) and fmulz(0.0, nan) must be +/-0.0, even if
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# SIGNED_ZERO_INF_NAN_PRESERVE is not used. If SIGNED_ZERO_INF_NAN_PRESERVE is used, then
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# the result must be a positive zero if either operand is zero.
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binop("fmulz", tfloat32, _2src_commutative + associative, """
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if (src0 == 0.0 || src1 == 0.0)
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dst = 0.0;
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@ -694,21 +702,27 @@ else if (nir_is_rounding_mode_rtz(execution_mode, 32))
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dst = _mesa_double_to_float_rtz((double)src0 * (double)src1);
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else
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dst = src0 * src1;
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""", description = """
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Unlike :nir:alu-op:`fmul`, anything (even infinity or NaN) multiplied by zero is
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always zero. ``fmulz(0.0, inf)`` and ``fmulz(0.0, nan)`` must be +/-0.0, even
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if ``SIGNED_ZERO_INF_NAN_PRESERVE`` is not used. If
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``SIGNED_ZERO_INF_NAN_PRESERVE`` is used, then the result must be a positive
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zero if either operand is zero.
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""")
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# low 32-bits of signed/unsigned integer multiply
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binop("imul", tint, _2src_commutative + associative, """
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/* Use 64-bit multiplies to prevent overflow of signed arithmetic */
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dst = (uint64_t)src0 * (uint64_t)src1;
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""")
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""", description = "Low 32-bits of signed/unsigned integer multiply")
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# Generate 64 bit result from 2 32 bits quantity
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binop_convert("imul_2x32_64", tint64, tint32, _2src_commutative,
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"(int64_t)src0 * (int64_t)src1")
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"(int64_t)src0 * (int64_t)src1",
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description = "Multiply signed 32-bit integers, 64-bit result")
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binop_convert("umul_2x32_64", tuint64, tuint32, _2src_commutative,
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"(uint64_t)src0 * (uint64_t)src1")
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"(uint64_t)src0 * (uint64_t)src1",
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description = "Multiply unsigned 32-bit integers, 64-bit result")
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# high 32-bits of signed integer multiply
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binop("imul_high", tint, _2src_commutative, """
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if (bit_size == 64) {
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/* We need to do a full 128-bit x 128-bit multiply in order for the sign
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@ -735,9 +749,8 @@ if (bit_size == 64) {
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* potential overflow of signed multiply */
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dst = ((uint64_t)(int64_t)src0 * (uint64_t)(int64_t)src1) >> bit_size;
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}
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""")
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""", description = "High 32-bits of signed integer multiply")
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# high 32-bits of unsigned integer multiply
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binop("umul_high", tuint, _2src_commutative, """
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if (bit_size == 64) {
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/* The casts are kind-of annoying but needed to prevent compiler warnings. */
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@ -749,31 +762,33 @@ if (bit_size == 64) {
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} else {
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dst = ((uint64_t)src0 * (uint64_t)src1) >> bit_size;
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}
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""")
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""", description = "High 32-bits of unsigned integer multiply")
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# low 32-bits of unsigned integer multiply
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binop("umul_low", tuint32, _2src_commutative, """
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uint64_t mask = (1 << (bit_size / 2)) - 1;
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dst = ((uint64_t)src0 & mask) * ((uint64_t)src1 & mask);
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""")
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""", description = "Low 32-bits of unsigned integer multiply")
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# Multiply 32-bits with low 16-bits.
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binop("imul_32x16", tint32, "", "src0 * (int16_t) src1")
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binop("umul_32x16", tuint32, "", "src0 * (uint16_t) src1")
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binop("imul_32x16", tint32, "", "src0 * (int16_t) src1",
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description = "Multiply 32-bits with low 16-bits, with sign extension")
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binop("umul_32x16", tuint32, "", "src0 * (uint16_t) src1",
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description = "Multiply 32-bits with low 16-bits, with zero extension")
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binop("fdiv", tfloat, "", "src0 / src1")
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binop("idiv", tint, "", "src1 == 0 ? 0 : (src0 / src1)")
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binop("udiv", tuint, "", "src1 == 0 ? 0 : (src0 / src1)")
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# returns an integer (1 or 0) representing the carry resulting from the
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# addition of the two unsigned arguments.
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binop_convert("uadd_carry", tuint, tuint, _2src_commutative,
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"src0 + src1 < src0",
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description = """
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Return an integer (1 or 0) representing the carry resulting from the
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addition of the two unsigned arguments.
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""")
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binop_convert("uadd_carry", tuint, tuint, _2src_commutative, "src0 + src1 < src0")
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# returns an integer (1 or 0) representing the borrow resulting from the
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# subtraction of the two unsigned arguments.
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binop_convert("usub_borrow", tuint, tuint, "", "src0 < src1")
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binop_convert("usub_borrow", tuint, tuint, "", "src0 < src1", description = """
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Return an integer (1 or 0) representing the borrow resulting from the
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subtraction of the two unsigned arguments.
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""")
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# hadd: (a + b) >> 1 (without overflow)
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# x + y = x - (x & ~y) + (x & ~y) + y - (~x & y) + (~x & y)
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@ -862,15 +877,21 @@ binop("sge", tfloat, "", "(src0 >= src1) ? 1.0f : 0.0f") # Set on Greater or Equ
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binop("seq", tfloat, _2src_commutative, "(src0 == src1) ? 1.0f : 0.0f") # Set on Equal
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binop("sne", tfloat, _2src_commutative, "(src0 != src1) ? 1.0f : 0.0f") # Set on Not Equal
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# SPIRV shifts are undefined for shift-operands >= bitsize,
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# but SM5 shifts are defined to use only the least significant bits.
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# The NIR definition is according to the SM5 specification.
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shift_note = """
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SPIRV shifts are undefined for shift-operands >= bitsize,
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but SM5 shifts are defined to use only the least significant bits.
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The NIR definition is according to the SM5 specification.
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"""
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opcode("ishl", 0, tint, [0, 0], [tint, tuint32], False, "",
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"(uint64_t)src0 << (src1 & (sizeof(src0) * 8 - 1))")
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"(uint64_t)src0 << (src1 & (sizeof(src0) * 8 - 1))",
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description = "Left shift." + shift_note)
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opcode("ishr", 0, tint, [0, 0], [tint, tuint32], False, "",
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"src0 >> (src1 & (sizeof(src0) * 8 - 1))")
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"src0 >> (src1 & (sizeof(src0) * 8 - 1))",
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description = "Signed right-shift." + shift_note)
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opcode("ushr", 0, tuint, [0, 0], [tuint, tuint32], False, "",
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"src0 >> (src1 & (sizeof(src0) * 8 - 1))")
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"src0 >> (src1 & (sizeof(src0) * 8 - 1))",
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description = "Unsigned right-shift." + shift_note)
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opcode("urol", 0, tuint, [0, 0], [tuint, tuint32], False, "", """
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uint32_t rotate_mask = sizeof(src0) * 8 - 1;
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@ -883,15 +904,16 @@ opcode("uror", 0, tuint, [0, 0], [tuint, tuint32], False, "", """
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(src0 << (-src1 & rotate_mask));
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""")
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# bitwise logic operators
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#
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# These are also used as boolean and, or, xor for hardware supporting
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# integers.
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bitwise_description = """
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Bitwise {0}, also used as a boolean {0} for hardware supporting integers.
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"""
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binop("iand", tuint, _2src_commutative + associative, "src0 & src1")
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binop("ior", tuint, _2src_commutative + associative, "src0 | src1")
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binop("ixor", tuint, _2src_commutative + associative, "src0 ^ src1")
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binop("iand", tuint, _2src_commutative + associative, "src0 & src1",
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description = bitwise_description.format("AND"))
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binop("ior", tuint, _2src_commutative + associative, "src0 | src1",
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description = bitwise_description.format("OR"))
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binop("ixor", tuint, _2src_commutative + associative, "src0 ^ src1",
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description = bitwise_description.format("XOR"))
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binop_reduce("fdot", 1, tfloat, tfloat, "{src0} * {src1}", "{src0} + {src1}",
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@ -931,13 +953,14 @@ opcode("pack_32_4x8_split", 0, tuint32, [0, 0, 0, 0], [tuint8, tuint8, tuint8, t
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False, "",
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"src0 | ((uint32_t)src1 << 8) | ((uint32_t)src2 << 16) | ((uint32_t)src3 << 24)")
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# bfm implements the behavior of the first operation of the SM5 "bfi" assembly
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# and that of the "bfi1" i965 instruction. That is, the bits and offset values
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# are from the low five bits of src0 and src1, respectively.
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binop_convert("bfm", tuint32, tint32, "", """
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int bits = src0 & 0x1F;
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int offset = src1 & 0x1F;
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dst = ((1u << bits) - 1) << offset;
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""", description = """
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Implements the behavior of the first operation of the SM5 "bfi" assembly
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and that of the "bfi1" i965 instruction. That is, the bits and offset values
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are from the low five bits of src0 and src1, respectively.
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""")
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opcode("ldexp", 0, tfloat, [0, 0], [tfloat, tint32], False, "", """
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@ -947,11 +970,11 @@ if (!isnormal(dst))
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dst = copysignf(0.0f, src0);
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""")
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# Combines the first component of each input to make a 2-component vector.
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binop_horiz("vec2", 2, tuint, 1, tuint, 1, tuint, """
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dst.x = src0.x;
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dst.y = src1.x;
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""", description = """
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Combines the first component of each input to make a 2-component vector.
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""")
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# Byte extraction
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@ -992,10 +1015,6 @@ if (nir_is_rounding_mode_rtz(execution_mode, bit_size)) {
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}
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""")
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# Unlike ffma, anything (even infinity or NaN) multiplied by zero is always zero.
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# ffmaz(0.0, inf, src2) and ffmaz(0.0, nan, src2) must be +/-0.0 + src2, even if
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# SIGNED_ZERO_INF_NAN_PRESERVE is not used. If SIGNED_ZERO_INF_NAN_PRESERVE is used, then
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# the result must be a positive zero plus src2 if either src0 or src1 is zero.
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triop("ffmaz", tfloat32, _2src_commutative, """
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if (src0 == 0.0 || src1 == 0.0)
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dst = 0.0 + src2;
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@ -1003,29 +1022,40 @@ else if (nir_is_rounding_mode_rtz(execution_mode, 32))
|
|||
dst = _mesa_float_fma_rtz(src0, src1, src2);
|
||||
else
|
||||
dst = fmaf(src0, src1, src2);
|
||||
""", description = """
|
||||
Floating-point multiply-add with modified zero handling.
|
||||
|
||||
Unlike :nir:alu-op:`ffma`, anything (even infinity or NaN) multiplied by zero is
|
||||
always zero. ``ffmaz(0.0, inf, src2)`` and ``ffmaz(0.0, nan, src2)`` must be
|
||||
``+/-0.0 + src2``, even if ``SIGNED_ZERO_INF_NAN_PRESERVE`` is not used. If
|
||||
``SIGNED_ZERO_INF_NAN_PRESERVE`` is used, then the result must be a positive
|
||||
zero plus src2 if either src0 or src1 is zero.
|
||||
""")
|
||||
|
||||
triop("flrp", tfloat, "", "src0 * (1 - src2) + src1 * src2")
|
||||
|
||||
# Ternary addition
|
||||
triop("iadd3", tint, _2src_commutative + associative, "src0 + src1 + src2")
|
||||
triop("iadd3", tint, _2src_commutative + associative, "src0 + src1 + src2",
|
||||
description = "Ternary addition")
|
||||
|
||||
# Conditional Select
|
||||
#
|
||||
# A vector conditional select instruction (like ?:, but operating per-
|
||||
# component on vectors). There are two versions, one for floating point
|
||||
# bools (0.0 vs 1.0) and one for integer bools (0 vs ~0).
|
||||
|
||||
triop("fcsel", tfloat32, selection, "(src0 != 0.0f) ? src1 : src2")
|
||||
csel_description = """
|
||||
A vector conditional select instruction (like ?:, but operating per-
|
||||
component on vectors). The condition is {} bool ({}).
|
||||
"""
|
||||
|
||||
triop("fcsel", tfloat32, selection, "(src0 != 0.0f) ? src1 : src2",
|
||||
description = csel_description.format("a floating point", "0.0 vs 1.0"))
|
||||
opcode("bcsel", 0, tuint, [0, 0, 0],
|
||||
[tbool1, tuint, tuint], False, selection, "src0 ? src1 : src2")
|
||||
[tbool1, tuint, tuint], False, selection, "src0 ? src1 : src2",
|
||||
description = csel_description.format("a 1-bit", "0 vs 1"))
|
||||
opcode("b8csel", 0, tuint, [0, 0, 0],
|
||||
[tbool8, tuint, tuint], False, selection, "src0 ? src1 : src2")
|
||||
[tbool8, tuint, tuint], False, selection, "src0 ? src1 : src2",
|
||||
description = csel_description.format("an 8-bit", "0 vs ~0"))
|
||||
opcode("b16csel", 0, tuint, [0, 0, 0],
|
||||
[tbool16, tuint, tuint], False, selection, "src0 ? src1 : src2")
|
||||
[tbool16, tuint, tuint], False, selection, "src0 ? src1 : src2",
|
||||
description = csel_description.format("a 16-bit", "0 vs ~0"))
|
||||
opcode("b32csel", 0, tuint, [0, 0, 0],
|
||||
[tbool32, tuint, tuint], False, selection, "src0 ? src1 : src2")
|
||||
[tbool32, tuint, tuint], False, selection, "src0 ? src1 : src2",
|
||||
description = csel_description.format("a 32-bit", "0 vs ~0"))
|
||||
|
||||
triop("i32csel_gt", tint32, selection, "(src0 > 0) ? src1 : src2")
|
||||
triop("i32csel_ge", tint32, selection, "(src0 >= 0) ? src1 : src2")
|
||||
|
|
@ -1033,7 +1063,6 @@ triop("i32csel_ge", tint32, selection, "(src0 >= 0) ? src1 : src2")
|
|||
triop("fcsel_gt", tfloat32, selection, "(src0 > 0.0f) ? src1 : src2")
|
||||
triop("fcsel_ge", tfloat32, selection, "(src0 >= 0.0f) ? src1 : src2")
|
||||
|
||||
# SM5 bfi assembly
|
||||
triop("bfi", tuint32, "", """
|
||||
unsigned mask = src0, insert = src1, base = src2;
|
||||
if (mask == 0) {
|
||||
|
|
@ -1046,7 +1075,7 @@ if (mask == 0) {
|
|||
}
|
||||
dst = (base & ~mask) | (insert & mask);
|
||||
}
|
||||
""")
|
||||
""", description = "SM5 bfi assembly")
|
||||
|
||||
|
||||
triop("bitfield_select", tuint, "", "(src0 & src1) | (~src0 & src2)")
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue