Commit graph

73068 commits

Author SHA1 Message Date
Tomeu Vizoso
15f0c245c8 ethosu: Set test baseline for the Corstone 1000 (U85)
Some checks are pending
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:59 +00:00
Tomeu Vizoso
ac0d6e7b7c ethosu: Properly emit IFM_BROADCAST and IFM2_BROADCAST on U85
On U85, both NPU_SET_IFM_BROADCAST and NPU_SET_IFM2_BROADCAST must be
emitted for elementwise operations, matching Vela's GenerateInputBroadcast.

Add calc_broadcast_mode() matching Vela's CalculateBroadcast(): broadcasts
a dimension of shape1 when it is 1 and shape2 is larger, producing a
broadcast_mode bitmask (H=1, W=2, C=4, SCALAR=8).

Split emit_ifm2_broadcast into U65 (legacy bitfields) and U85 paths.
The U85 path emits both IFM_BROADCAST and IFM2_BROADCAST using
calc_broadcast_mode in each direction.

Also fix emit_eltwise to call emit_ifm2_precision instead of
emit_ifm_broadcast for U85, which was emitting 0 instead of the
required IFM2_PRECISION register.

Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:59 +00:00
Tomeu Vizoso
2a6d181bc6 ethosu: Fix scalar ADD on U85
They added new registers tot he command stream, with a new bitfield
layout.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:59 +00:00
Tomeu Vizoso
818e1835d7 ethosu: map BOs at creation time and unmap at destruction
Map DRM buffer objects once at resource_create and unmap at
resource_destroy, instead of mapping them in buffer_map where they
were never unmapped. This fixes a virtual memory leak that caused
SIGBUS under heavy workloads by exhausting CMA.

Also remove unused phys_addr and obj_addr fields from ethosu_resource,
and add asserts on pipe_buffer_create return values.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:58 +00:00
Tomeu Vizoso
f9cd399eb0 ethosu: Fix ublock selection for 8-bit depthwise/pooling on U85-256
For U85-256 with 8-bit IFM, Vela's _uBlockToOpTable restricts which
microblocks are valid per operation type:

  {2,2,8}  and {4,1,8}:  conv, matmul, vectorprod, reducesum, eltwise, resize
  {2,1,16}:              depthwise, pool, eltwise, reduceminmax, argmax, resize

Mesa's find_ublock() was not enforcing these constraints, allowing
{4,1,8} or {2,2,8} to be selected for depthwise/pooling based on
minimum waste. For depthwise ops with OFM shapes that aligned better
to {4,1,8}, the wrong ublock was chosen, causing incorrect weight
encoding and NPU hangs.

Fix by skipping {4,1,8} and {2,2,8} for depthwise/pooling operations,
matching Vela's operation-validity table.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:58 +00:00
Tomeu Vizoso
dc36a32214 ethosu: Implement simplified scaling for U85
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:58 +00:00
Tomeu Vizoso
dbfbc6eff4 ethosu: Emission changes for U85
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:58 +00:00
Tomeu Vizoso
42082266f0 ethosu: Refactor ethosu_allocate_feature_map to return the new offset
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:58 +00:00
Tomeu Vizoso
fc70406bdd ethosu: Expand pooling to U85
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:57 +00:00
Tomeu Vizoso
a735fe040b ethosu: Improve parallelism by detecting overlaps for BLOCKDEP
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:57 +00:00
Tomeu Vizoso
2cf3d0b273 ethosu: Add a separate scheduler for the U85
As the performance details have changed quite a bit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:57 +00:00
Tomeu Vizoso
82d4f21106 ethosu: Don't emit redundant state changes
Keep track of the state and only emit meaningful changes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:56 +00:00
Tomeu Vizoso
8872f5eea4 ethosu: Add debug option for forcing U85 generation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:56 +00:00
Tomeu Vizoso
45fb8b99df ethosu: Invert lowering order of concatenation suboperations
Just so we match the order in which Vela assigns offsets to the FMs so
it's easier to diff cmdstream dumps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:56 +00:00
Tomeu Vizoso
d66d2c05d3 ethosu: Switch to the weight encoder from Regor
We vendor the encoder used in the Regor compiler in Vela, and replace
the previous one that was used by the Python compiler and doesn't
support U85.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:55 +00:00
Tomeu Vizoso
410d74e078 ethosu: Compute is_partkernel during scheduling
As we need it for encoding the weights.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:55 +00:00
Tomeu Vizoso
3ade0a4dd6 ethosu: Make the UBlock sizes arch-specific
As U85 has a different configuration.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:55 +00:00
Tomeu Vizoso
91137a9327 ethosu: Let maxblockdeps be arch-specific
As U85 can have up to 7.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:54 +00:00
Tomeu Vizoso
0af37552a7 ethosu: Add U85 fields, these are compatible with the U65
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:54 +00:00
Tomeu Vizoso
4388f602ed teflon: Fix leak of tensor structs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:53 +00:00
Tomeu Vizoso
47aa30276e ethosu: Update test expectations
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
2026-03-23 07:45:53 +00:00
Marek Olšák
fa5175023b Final rename of sha1 names to blake3
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:28 +00:00
Marek Olšák
ae9ea27e0d Rename *_sha1 names to *_blake3
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:28 +00:00
Marek Olšák
353fe94c0e Rename SHA1 words to BLAKE3
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:28 +00:00
Marek Olšák
102d41799b Rename more sha and sha1 names to blake3
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:28 +00:00
Marek Olšák
282bd2e6db Rename sha words to blake3
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:28 +00:00
Marek Olšák
d4831aaf5f Rename sha1_* and sha_* names to blake3_*
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:28 +00:00
Marek Olšák
c0ac992a2a Remove mesa-sha1.h
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
53c64973e8 Inline _mesa_sha1_compute/format, remove the other unused ones
_mesa_sha1_format has a few remaining uses, so it's moved to build_id.c,
which is its last user.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
699f9d7066 Inline _mesa_sha1_init/update/final functions
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
3ae8f910ad Inline SHA1* functions, remove sha1.h
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
a965ada6ee Inline mesa_sha1, SHA1_CTX
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
0da88d237a Inline SHA1_DIGEST_STRING_LENGTH
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
110632f702 Inline SHA1_DIGEST_LENGTH
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
2283244975 nir: change export_amd intrinsics to use target instead of base
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40415>
2026-03-23 06:10:49 +00:00
Rob Herring (Arm)
6b26cc2df3 ethosu: Fix buffer overrun in stridedslice
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
The slice.begin array length matches the tensor depth which may be less
than 4.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
5e93ab5477 ethosu: Support ReLU activation for ADD ops
ReLU activations require the minimum to be set to the zero point.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
69d1da3518 teflon: Support ReLU activation for ADD ops
ADD operations can have fused ReLU activations. Add the setting to the
operation state.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
3780fb8494 ethosu: Handle IFM2 H/W/D broadcast
If the IFM and IFM2 dimensions are not the same, then the H/W/D broadcast
needs to be enabled.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
1cb46e9304 ethosu: Handle reversing IFM and IFM2 operands
IFM2 must be scalar or smaller than IFM. If not, then the operands need
to be swapped.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:19 +00:00
Rob Herring (Arm)
d962160e95 ethosu: Add scalar ADD support
An input tensor can contain a single scalar value to add to the IFM.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:19 +00:00
Rob Herring (Arm)
5606fd1ea6 ethosu: Add support for 16-bit tensors
Ethos-U can support 16-bit tensors. So far the driver just assumed 8-bit
tensors.

There's a few cases where 32-bit tensors are supported, but exactly what
those are hasn't been determined, so just reject them for now.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:19 +00:00
Rob Herring (Arm)
7613788f06 teflon: Add support for setting the tensor type size
Drivers supporting different element sizes need to know the element type
size.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:18 +00:00
Rob Herring (Arm)
c29860e9e9 test_teflon: Add 32-bit integer output comparison
Add support for 32-bit integer output comparison. This fixes several
test failures for movenetlightning and movenetthunder.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:18 +00:00
Rob Herring (Arm)
ac9bb98991 test_teflon: Fix missing UInt16/Int16 output size
The output comparison expects number of elements, not bytes. Adjusting the
size was missed when adding UInt16/Int16 output comparisons.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:18 +00:00
Rob Herring (Arm)
6375db3fd3 test_teflon: Fix crash with read-only buffers
Some decomposed models have read-only input buffers which already have
data and don't need to be initialized.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:17 +00:00
Daniel Schürmann
53f2c405e1 lavapipe/rt: add and lower loop continue construct in traversal shaders
We are going to disallow continue statements without
loop continue constructs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
ebfb9b9479 tgsi_to_nir: Add and lower loop continue constructs
We are going to disallow continue statements without
loop continue constructs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Mike Blumenkrantz
4b2022a8f5 llvmpipe: fix color fbfetch
with the unlowering pass, there is no longer a separate gl_LastFragData variable,
so this workaround just breaks color outputs

fixes dEQP-GLES31.functional.shaders.framebuffer_fetch.basic.last_frag_data

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40437>
2026-03-20 20:02:35 +00:00
Lorenzo Rossi
caf5a2640b panvk,panfrost: Always emit ld_var_buf when possible
Previously the driver decided when the backend should use
LD_VAR_BUF[_IMM] instructions based on the total number of varyings
read, falling back to LD_VAR[_IMM] + descriptors when the varying index
could overflow the immediate index in the instructions.  That means that
even adding a single varying read could overflow the index and make
everything fall back to LD_VAR.

With this patch the backend decides when to use LD_VAR_BUF for each
varying load, reporting that decision to the driver.  This helps with
index overflows because only the instruction that actually overflow the
immediate use the LD_VAR fallback, leaving all other instructions on the
fast path.

Signed-off-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40515>
2026-03-20 18:47:11 +00:00