Commit graph

3788 commits

Author SHA1 Message Date
Samuel Pitoiset
51ff50ef30 radv,aco: fix shifting input VGPRs for the LS VGPR init bug on GFX9
We were incorrectly shifting the input VGPRs for the instance ID
for chips affected by the LS VGPR init bug (ie. Vega10 and Raven).

When there is no HS threads, the hardware loads the LS VGPR
starting from VGPR 0, so they should be shifted by two.

This fixes some sort of vertex explosion with Squad, Visage, Barn
Finders and probably more titles that use tessellation. Note that
only Vega10 and Raven were affected by this bug.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4129
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3311
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Diego Viola <diego.viola@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8694>
(cherry picked from commit bb8f87088c)
2021-01-25 10:07:15 -08:00
Samuel Pitoiset
c849e15c44 radv: fix separate depth/stencil layout in render pass
We used to select the stencil layout even if we should have selected
the depth/stencil one.

Fixes: e4c8491bdf ("radv: implement VK_KHR_separate_depth_stencil_layouts")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8552>
(cherry picked from commit 3ef89b245e)
2021-01-22 09:02:46 -08:00
Samuel Pitoiset
291eebfaa4 radv: inhibit clock gating when tracing with SQTT
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8616>
(cherry picked from commit 5b5cd18853)
2021-01-22 09:01:42 -08:00
Samuel Pitoiset
acfd179fe3 radv: fix overflow when computing the SQTT buffer size
With RADV_THREAD_TRACE_BUFFER_SIZE=1073741824, the computed size
will overflow and be 4096 instead of 4294967296.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8616>
(cherry picked from commit c40ea24ee0)
2021-01-22 09:01:41 -08:00
Samuel Pitoiset
eaefaa9610 radv: fix a sync issue with geometry shader primitives query on GFX10+
When NGG is used, the hw can't know the number of geometry shader
primitives. To fix that, the NGG geometry shader accumulates itself
the number of primitives by using an atomic operation directly to GDS.

Then, begin/query copy the start/stop values from GDS to the
query pool buffer using a PS_DONE event. This was actually wrong
because PS_DONE is completely asynchronous to everything and executed
when the preceding draws finish pixel shaders.

Fix this by using a COPY_DATA packet which is synced with CP. This
fixes random failures on Sienna Cichlid with
dEQP-VK.query_pool.statistics_query.*.geometry_shader_primitives.*.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8590>
(cherry picked from commit 085e2ce3d4)
2021-01-21 13:26:36 -08:00
Rhys Perry
8ba9bb139c radv,aco: don't use MUBUF for multi-channel loads on GFX8 with robustness2
Fixes several dEQP-VK.robustness.robustness2.* tests on GFX8. Generations
other than GFX8 don't fail the tests because bounds-checking is done using
the index (making it per-vertex).

fossil-db (Polaris):
Totals from 1387 (0.99% of 140385) affected shaders:
(no statistics affected)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 03a0d39366 ("aco: use MUBUF in some situations instead of splitting vertex fetches")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7834>
(cherry picked from commit 914c61d6c0)
2021-01-21 13:26:34 -08:00
Samuel Pitoiset
664f6976b2 radv: flush L2 for images affected by the pipe misaligned issue on GFX10+
In some rare cases, L2 needs to be flushed if an image is affected
by the pipe misaligned issue. This is roughly based on AMDVLK.

I confirmed that disabling TC-compat HTILE, and respectively DCC,
for the relevant images also fixes the regressions below.

This fixes some regressions introduced with L2 coherency for
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_* and for
dEQP-VK.renderpass2.suballocation.multisample_resolve.*.

Fixes: 4a783a3c78 ("radv: Use L2 coherency on GFX9+.")
Co-Authored-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8557>
(cherry picked from commit 4c99d6ff54)
2021-01-20 11:11:03 -08:00
Samuel Pitoiset
0acff8c6f2 radv: restore invalidating the vector cache for internal meta operations
The driver used to invalidate the vector cache for meta operations
but this has been removed and I think it should be restored to fix
a bunch of regressions on GFX8.

This probably needs to be cleaned up but this is a hotfix.

This fixes a bunch of regressions and flakes on GFX8 like
dEQP-VK.pipeline.multisample.sample_locations_ext.draw.color.samples_4.*.

Fixes: 8f8d72af55 ("radv: Use access helpers for flushing with meta operations.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8573>
(cherry picked from commit 8882abe47e)
2021-01-20 11:11:03 -08:00
Samuel Pitoiset
3994f5db48 radv: flush L2 metadata as part of CB/DB flush instead of CS_DONE on GFX9
This restores the previous logic because L2 coherency was fully
implemented. It appears that flushing L2 metadata with a CS_DONE
event hangs.

This fixes GPU hangs with Monster Hunter World.

Fixes: 4a783a3c ("radv: Use L2 coherency on GFX9+.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8566>
(cherry picked from commit c3ac6f7cd7)
2021-01-20 09:22:16 -08:00
Bas Nieuwenhuizen
380c7edbc2 radv: Do not use a pipe offset for aliased sparse images.
Otherwise the offset might not match between the images that are
aliased.

Fixes: e553ea51e8 ("radv: Create sparse images.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4072
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8535>
(cherry picked from commit af1aef10f9)
2021-01-20 09:22:16 -08:00
Samuel Pitoiset
73ea60139d radv: do not invalidate the L2 metadata cache on compute queues
The flush VA space was only allocated for command buffers on the
graphics queue. Also, the ZPASS_DONE event should never be emitted
on compute queues because it hangs.

Invalidating the L2 metadata cache is only required for coherency
between the RBs and L2, so only on the graphics queue.

The L2 cache is invalidated at beginning of any IBs and that should
also invalidate the L2 metadata cache for compute anyways.

Fixes: 4a783a3c ("radv: Use L2 coherency on GFX9+.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8494>
(cherry picked from commit c6849f9687)
2021-01-15 09:19:51 -08:00
Rhys Perry
82e845ba67 nir/loop_unroll: unroll more aggressively if it can improve load scheduling
Significantly improves performance of a Control compute shader. Also seems
to increase FPS at the very start of the game by ~5% (RX 580, 1080p,
medium settings, no MSAA).

fossil-db (Sienna):
Totals from 81 (0.06% of 139391) affected shaders:
SGPRs: 3848 -> 4362 (+13.36%); split: -0.99%, +14.35%
VGPRs: 4132 -> 4648 (+12.49%)
CodeSize: 275532 -> 659188 (+139.24%)
MaxWaves: 986 -> 906 (-8.11%)
Instrs: 54422 -> 126865 (+133.11%)
Cycles: 1057240 -> 750464 (-29.02%); split: -42.61%, +13.60%
VMEM: 26507 -> 61829 (+133.26%); split: +135.56%, -2.30%
SMEM: 4748 -> 5895 (+24.16%); split: +31.47%, -7.31%
VClause: 1933 -> 6802 (+251.89%); split: -0.72%, +252.61%
SClause: 1179 -> 1810 (+53.52%); split: -3.14%, +56.66%
Branches: 1174 -> 1157 (-1.45%); split: -23.94%, +22.49%
PreVGPRs: 3219 -> 3387 (+5.22%); split: -0.96%, +6.18%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6538>
(cherry picked from commit dfe429eb41)
2021-01-13 11:24:15 -08:00
Daniel Schürmann
12c0bfaaf9 radv: vectorize 16bit instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit fcd2ef23e5)
2021-01-13 11:24:11 -08:00
Samuel Pitoiset
3c1275ccae radv: enable DCC for MSAA on GFX10+
It should work fine now.

This gives +1-2% improvements with Control MSAA (2x and 4x)
on Sienna.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8413>
2021-01-13 17:24:31 +00:00
Bas Nieuwenhuizen
4a783a3c78 radv: Use L2 coherency on GFX9+.
Especially on GFX10 we can avoid pretty much all L2 flushes.

However, instead of that we have to do L2_METADATA invalidations. We
do that every time we could possibly be reading new DCC/HTILE info
from the L2 cache in shaders.

Benchmark results, basemark on high preset with a navi10 on profile_standard
(which is slower than a navi10 on default settings, please don't compare
 to random navi10 results you find)

before:
  5932
  5928
  5937

after:
  6011
  6013
  6009

So this looks like a >1% increase.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
0af86341a2 radv: Use L2 for CP DMA on GFX9+.
This enables assuming that the L2 is always up to date for barriers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
8f8d72af55 radv: Use access helpers for flushing with meta operations.
This way we're properly using the vulkan barrier paradigm instead
of adhoc guessing what caches need to be flushed. This is more robust
for cache policy changes as we now don't have to revisit all the meta
operations all the time.

Note that a barrier has both a src and dst part though. So

barrier:
   flush src
   meta op
   flush dst

becomes

barrier:
  flush barrier src
  flush meta op dst
  meta op
  flush meta op src
  flush barrier dst

And there are some places where we've been able to replace a CB flush
with a shader flush because that is what we'd need according to vulkan rules
(and it turns out that in the cases the CB flush mattered the app will set the
bit in one of the relevant flushes or it was needed as a result of an optimization
that we counter-acted in the previous patch.)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
dba0a523a0 radv: Do dst invalidations for write accesses.
For write-after-write hazards.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
9026f10cda radv: Invalidate CB on SHADER_WRITE for meta operations.
To cancel the optimization in radv_dst_access_flush if these helpers
get used by meta operations.

We could also remove that optimization but I think this triggers less
often as all SHADER_WRITE flushes on images not supporting STORAGE should
be meta

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
3d7713b5a2 radv: Remove redundant WB_L2 flush.
INV_L2 already does that.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
2021-01-13 16:27:19 +00:00
Samuel Pitoiset
afad13700a radv: disable VK_EXT_sample_locations again on GFX10+
I attempted to enable it for 21.0, only 2x and 4x were supported
but there is new failures if DCC+MSAA is enabled.

Disable it again because DCC is more important than this feature and
no Mesa releases have it on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8472>
2021-01-13 15:04:56 +00:00
Samuel Pitoiset
001c1105f1 radv: enable DCC for mipmaps on GFX10+
Seems to work fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8468>
2021-01-13 13:42:04 +00:00
Samuel Pitoiset
825e2386dc radv: do not enable DCC for 3D images with mipmaps on GFX10+
This is broken for some reasons, and probably rare enough to
care for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8468>
2021-01-13 13:42:04 +00:00
Samuel Pitoiset
755a8313fc radv: add support for fast-clearing DCC levels on GFX10+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8468>
2021-01-13 13:42:04 +00:00
Samuel Pitoiset
5537c9de73 radv: prevent fast-clearing uncompressed DCC levels
When size is 0, this means the level can't be compressed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8468>
2021-01-13 13:42:04 +00:00
Samuel Pitoiset
fcd5925612 radv: skip fast-clear eliminate for CMASK based on a predicate
If we have CMASK, we can also skip FCE like we do for DCC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8332>
2021-01-13 12:24:32 +01:00
Samuel Pitoiset
697c93abc1 radv: update the FCE predicate for fast clears using CMASK
Fast clearing with CMASK should always be eliminated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8332>
2021-01-13 12:24:30 +01:00
Samuel Pitoiset
051e2bfe80 radv: allocate and initialize the FCE predicate value for CMASK too
In case we don't have DCC, we can still predicate FCE with CMASK.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8332>
2021-01-13 12:24:29 +01:00
Samuel Pitoiset
735b808639 radv: only use predication if the FCE value is allocated
The FCE predicate value is only allocated if DCC is enabled.
We only want to use predication for DCC decompressions and for FCE
but not having FMASK doesn't mean the predicate is allocated.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4075
Fixes: 6e7008e94b ("radv: do not predicate FMASK decompression when DCC+MSAA is used")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8441>
2021-01-13 11:13:47 +00:00
Samuel Pitoiset
dbe845624b radv: fix clearing DCC on GFX9
dcc_slice_size is in DWORD on GFX9... Also, layers aren't supported
because they might be interleaved. Fix this by clearing the entire
DCC buffer.

Fixes: 5e8f6967b1 ("radv: add support for fast-clearing DCC layers on GFX9+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8443>
2021-01-13 08:33:40 +01:00
Bas Nieuwenhuizen
4956f6d0bf radv: Add Android module info to linker script.
The Android Vulkan loader needs this symbol, so the addition of the
linker script broke Vulkan for Android.

(For non-Android builds: I checked that having a non-existent symbol in
 the linker script works ok and doesn't put the symbol in the library)

Fixes: 41bb6459d3 ("radv: restrict exported symbols with static llvm")
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8437>
2021-01-12 20:17:52 +00:00
Daniel Schürmann
d495a5c183 radv: enable .lower_ineg
We already emit ineg as isub most of the time.

The results are a bit mixed, but shouldn't really make a difference.
A couple of additional copies are needed as isub writes scc.

Totals from 5975 (4.29% of 139391) affected shaders:
CodeSize: 31508648 -> 31509264 (+0.00%); split: -0.00%, +0.00%
Instrs: 6073379 -> 6073531 (+0.00%); split: -0.00%, +0.00%
Cycles: 47186280 -> 47187116 (+0.00%); split: -0.00%, +0.00%
VMEM: 2528515 -> 2529139 (+0.02%); split: +0.03%, -0.01%
SMEM: 596842 -> 596924 (+0.01%); split: +0.02%, -0.00%
SClause: 280596 -> 280594 (-0.00%)
Copies: 288554 -> 288669 (+0.04%); split: -0.00%, +0.04%
PreSGPRs: 240390 -> 240397 (+0.00%)
PreVGPRs: 349630 -> 349749 (+0.03%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
2021-01-12 16:14:00 +00:00
Daniel Schürmann
e92bd57008 radv: don't lower_pack() after load-store-vectorization
Totals from 7 (0.01% of 139391) affected shaders:
CodeSize: 282900 -> 283324 (+0.15%); split: -0.01%, +0.16%
Instrs: 45287 -> 45338 (+0.11%); split: -0.01%, +0.12%
Cycles: 11496332 -> 11510396 (+0.12%); split: -0.00%, +0.12%
VMEM: 2355 -> 2335 (-0.85%)
Copies: 15506 -> 15561 (+0.35%)

A bit of noise in some parallel-rdp shaders.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
2021-01-12 16:14:00 +00:00
Daniel Schürmann
987a0e6a67 radv: call nir_opt_algebraic_late() after lowering idiv for small bitsizes
This is needed because lower_idiv() introduces ineg again
which we'll remove next.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
2021-01-12 16:14:00 +00:00
Daniel Schürmann
1ab9dd22a2 radv: optimize idiv_const for small bitsizes
No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
2021-01-12 16:14:00 +00:00
Samuel Pitoiset
20af07d089 radv: fix color resolves if the dest image has DCC
Using the graphics resolve path when DCC is enabled should only be
a hint to avoid DCC fixup.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3388
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
2021-01-12 16:03:36 +00:00
Samuel Pitoiset
3e781056b9 radv: fixup DCC after color resolves using the compute path
If the dest image has DCC it should be re-initialized to the
uncompressed state.

Note that the driver always selects the graphics path if the dest
image has DCC, so this has no effect for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
2021-01-12 16:03:36 +00:00
Samuel Pitoiset
1f548b7670 radv: decompress DCC for partial resolves using the compute path
Because DCC is re-initialized to the uncompressed state after the
resolve, so if the app does a partial resolve it should be
decompressed first.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
2021-01-12 16:03:36 +00:00
Samuel Pitoiset
095a428844 radv: set depth to 1 for subpass resolves using the compute path
To match Vulkan convention.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
2021-01-12 16:03:36 +00:00
Rhys Perry
255ca7ecda radv: set invariantgeom for Shadow of the Tomb Raider
Work around flickering foliage on GFX10.3

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4064
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8104>
2021-01-12 15:11:49 +00:00
Rhys Perry
f17de6a803 radv: add RADV_DEBUG=invariantgeom
This can be used to work around a common class of bugs appearing as
flickering.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8104>
2021-01-12 15:11:49 +00:00
Daniel Schürmann
bd8e84eb8d nir: replace .lower_sub with .has_fsub and .has_isub
This allows a more fine-grained control about whether
a backend supports one of these instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6597>
2021-01-11 19:13:51 +00:00
Samuel Pitoiset
d2524ed4a0 radv: mark VK_IMAGE_CREATE_SPARSE_RESIDENCY_BIT as unsupported on GFX6-7
This is only supported on GFX8+, this fixes a ton of CTS failures
on my Pitcairn (GFX6).

Fixes: af7fb4df50 ("radv: Add sparse image queries.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8415>
2021-01-11 17:17:42 +00:00
Samuel Pitoiset
7d44ba7217 radv: enable DCC for layered color images on GFX10+
There is still some CTS failures on GFX9.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
2021-01-11 15:42:22 +00:00
Samuel Pitoiset
8754f9e8f9 radv: do not use predication when the range doesn't cover the whole image
The predication is based on the mip level, so if the image has layers
and DCC is enabled, it should only be used if the range of layers
covers the whole image.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
2021-01-11 15:42:22 +00:00
Samuel Pitoiset
5420ab9cdf radv: clean up radv_decompress_dcc_compute()
Remove one old comment because it supports decompressing layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
2021-01-11 15:42:22 +00:00
Samuel Pitoiset
5e8f6967b1 radv: add support for fast-clearing DCC layers on GFX9+
Layers are contiguous in memory.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
2021-01-11 15:42:22 +00:00
Bas Nieuwenhuizen
9f43b44bf0 radv: Enable sparse buffer and image support.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen
af7fb4df50 radv: Add sparse image queries.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
2021-01-11 12:01:34 +00:00
Bas Nieuwenhuizen
3ac8804829 radv: Add image sparse memory update implementation.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
2021-01-11 12:01:34 +00:00