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radv: allocate and initialize the FCE predicate value for CMASK too

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In case we don't have DCC, we can still predicate FCE with CMASK.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8332>
This commit is contained in:
Samuel Pitoiset 2021-01-05 15:07:47 +01:00
parent 735b808639
commit 051e2bfe80
2 changed files with 6 additions and 4 deletions
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6
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2135,7 +2135,7 @@ radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
uint32_t level_count = radv_get_levelCount(image, range);
uint32_t count = 2 * level_count;
assert(radv_dcc_enabled(image, range->baseMipLevel));
assert(image->fce_pred_offset != 0);
radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
@ -6210,12 +6210,12 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
}
radv_initialize_dcc(cmd_buffer, image, range, value);
radv_update_fce_metadata(cmd_buffer, image, range, false);
}
if (radv_image_has_cmask(image) ||
radv_dcc_enabled(image, range->baseMipLevel)) {
radv_update_fce_metadata(cmd_buffer, image, range, false);
uint32_t color_values[2] = {0};
radv_set_color_clear_metadata(cmd_buffer, image, range,
color_values);

4
src/amd/vulkan/radv_image.c
View file

@ -1272,10 +1272,12 @@ radv_image_alloc_single_sample_cmask(const struct radv_device *device,
static void
radv_image_alloc_values(const struct radv_device *device, struct radv_image *image)
{
if (radv_image_has_dcc(image)) {
if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
image->fce_pred_offset = image->size;
image->size += 8 * image->info.levels;
}
if (radv_image_has_dcc(image)) {
image->dcc_pred_offset = image->size;
image->size += 8 * image->info.levels;
}