Commit graph

684 commits

Author SHA1 Message Date
Mike Blumenkrantz
4fe6c85526 gallium: rename pipe_draw_start_count -> pipe_draw_start_count_bias
and add an index_bias member

no functional changes yet, just the rename and unused struct member

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166>
2021-04-30 03:59:19 +00:00
Anuj Phogat
8acf361db4 intel: Fix GEN_GEN macro checks
Fixes: 9da8a55b08 - intel: Rename GEN_GEN macro to GFX_VER
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10365>
2021-04-21 16:05:29 +00:00
Anuj Phogat
61e8636557 intel: Rename gen_device prefix to intel_device
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen_device" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device/intel_device/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
2021-04-20 20:06:33 +00:00
Francisco Jerez
20e2c7308f iris/gen12: Work around push constant corruption on context switch.
This has been confirmed to fix sporadic graphics corruption on Gen12
platforms for a number of workloads (including Heaven, Valley and
CS:GO among others).  Corruption seems to occur during context switch
fairly consistently, but unfortunately this problem doesn't seem to be
documented.  Until the hardware team comes up with a better
workaround, fix the problem by reemitting constants at the beginning
of each batch.

No corruption has been observed so far in GL due to preemption,
however this is a possibility to keep in mind, it may be necessary to
disable preemption in addition to this patch in order to fully address
this problem (see also 81201e4617).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4412
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4454
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2021-04-16 12:41:40 -07:00
Michel Dänzer
d200f45875 Use explicit break instead of fall-through to break-only case
clang generates a warning if there's no explicit break or fall-through
annotation. The latter would be kind of silly in this case, and not
robust against any future changes turning the fall-through invalid.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
2021-04-15 16:01:22 +00:00
Michel Dänzer
8d4c31b3c7 iris: Drop unneeded default switch case
Avoids clang warning about the fall-through annotation.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
2021-04-15 16:01:22 +00:00
Michel Dänzer
2928c21eb7 Convert most remaining free-form fall-through comments to FALLTHROUGH
One exception is src/amd/addrlib/, for which -Wimplicit-fallthrough is
explicitly disabled.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
2021-04-15 16:01:22 +00:00
Felix DeGrood
c85ea824bc iris: reduce redundant tile cache flushes
We are flushing tile cache more often than is necessary. In
unified cache mode, tile cache flushing is expensive, evicting all
depth/pixel data from the L3$. This is only need for a handful of
cases, such as: making cpu or gpu changes globally visible
(e.g. map), fast color clears, or slow depth clears. Tile cache
flushing is a gen12+ feature.

Remove blanket flushing of tile cache on all depth/RT flushes.
Replace with selective tile cache flushing.

Improves performance in several workloads:
AztecRuins.ogl-high-offscreen-1440p 1%
UnigineValley.ogl-g2                1%
Dota 2 (replay Jul 2020).ogl-g2     1%
Counter-Strike GO.ogl-g2            1%
Manhattan.ogl-Off-19x10             2%
CarChase.ogl-Off-19x10              1%
Bioshock Infinite.ogl-g2            1%

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10217>
2021-04-15 04:54:40 +00:00
Felix DeGrood
ed8f2c4cbe iris: Cache VB/IB in L3$ for Gen12
Gen12 enables caching of Vertex and Index Buffers in L3.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10217>
2021-04-15 04:54:40 +00:00
Anuj Phogat
051b7e1925 intel: Rename WA_### to Wa_###
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "WA_[[:digit:]]{10}" -rIl $SEARCH_PATH | xargs sed -ie "s/WA_\([[:digit:]]\{10\}\)/Wa_\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat
f96c3b8b63 intel: Rename GEN:BUG:### to Wa_###
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN:BUG:" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\(:BUG:\)/Wa_/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat
1d296484b4 intel: Rename Genx keyword to Gfxx
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "Gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/Gen\([[:digit:]]\+\)/Gfx\1/g"

Exclude changes in src/intel/perf/oa-*.xml:
find src/intel/perf -type f \( -name "*.xml" \) | xargs sed -ie "s/Gfx/Gen/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat
b75f095bc7 intel: Rename genx keyword to gfxx in source files
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/gen\([[:digit:]]\+\)/gfx\1/g"

Exclude pack.h and xml changes in this patch:
grep -E "gfx[[:digit:]]+_pack\.h" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g"
grep -E "gfx[[:digit:]]+\.xml" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+\.xml\)/gen\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat
abe9a71a09 intel: Rename gen field in gen_device_info struct to ver
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)gen" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)gen/info\1\2ver/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat
99331f6deb intel: Rename genx10 field in gen_device_info struct to verx10
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)genx10" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)genx10/info\1\2verx10/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat
9da8a55b08 intel: Rename GEN_GEN macro to GFX_VER
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_GEN" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_GEN/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:06 +00:00
Anuj Phogat
295bb3c263 intel: Rename GEN_VERSIONx10 macro to GFX_VERx10
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_VERSION" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_VERSION/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:06 +00:00
Tapani Pälli
b2af419391 iris: clamp PointWidth in 3DSTATE_SF like i965 does
Values match how MinimumPointWidth, MaximumPointWidth is setup. This
fixes assert hit in debug build when packing the struct with too large
value for genxml.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9942>
2021-04-01 10:18:23 +03:00
Eric Anholt
57e00aed8e iris: Flag for resolves when stencil enable changes, too.
The watcher of this dirty flag looks at this state, so it sure seems like
it needs it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9768>
2021-03-24 20:38:38 +00:00
Jordan Justen
16d453da7f genxml/gen12: 3D_MODE bits 31:16 are no longer must-be-one
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9505>
2021-03-19 09:07:37 +00:00
Lionel Landwerlin
33bc2977e5 intel/mi_builder: use device info to use the right CS prefetch size
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9679>
2021-03-18 20:08:45 +00:00
Vinson Lee
7e412a5d33 iris: Fix typos.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9382>
2021-03-15 00:01:30 +00:00
Jason Ekstrand
6d16d929f3 iris: Add an iris_write_reg macro
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9537>
2021-03-12 04:17:39 +00:00
Anuj Phogat
96e251bde7 intel: Rename "GEN_" prefix used in common code to "INTEL_"
This patch renames all macros with "GEN_" prefix defined in
common code.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>
2021-03-10 22:23:51 +00:00
Anuj Phogat
65d7f52098 intel: Fix broken alignment due to gen_ prefix renaming
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>
2021-03-10 22:23:51 +00:00
Anuj Phogat
692472a376 intel: Rename "gen_" prefix used in common code to "intel_"
This patch renames functions, structures, enums etc. with "gen_"
prefix defined in common code.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>
2021-03-10 22:23:51 +00:00
Anuj Phogat
733b0ee8cb intel: Rename files with gen_ prefix in common code to intel_
Changes in this patch include:
- Rename all files in src/intel/common path
- Update the filenames used in source and build files

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>
2021-03-10 22:23:51 +00:00
Dave Airlie
8027a7ba8a shader_info: convert textures_used to a bitset.
For now keep it a bitset of 1 32-bit dword.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9456>
2021-03-10 06:16:09 +10:00
Kenneth Graunke
1b1c857248 iris: Make various classes inherit from u_threaded_context base classes
u_threaded_context requires various objects to inherit from a new
threaded_foo base class rather than directly from pipe_foo.  This
patch does most of the mechanical changes required for that.

It also initializes the new threaded_resource fields.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8964>
2021-03-04 13:59:21 -08:00
Kenneth Graunke
ec0d61c14c iris: Support rebinding of stream output targets
This enables us to replace the backing storage of resources that have
been used as stream output targets, in case we're invalidating their
entire contents.  This can avoid stalls.  We simply hadn't supported it
because it was going to be tricky to re-emit 3DSTATE_SO_BUFFER without
screwing up "reset offset to zero" vs. "keep appending".  But that
should be working fine with the previous patch's refactor.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8964>
2021-03-04 13:59:21 -08:00
Kenneth Graunke
08e04ddd2c iris: Rework zeroing of stream output buffer offsets
The previous mechanism was a bit fragile.  We stored the zero offset
in the pre-baked packet, and used an flag to override 0xFFFFFFFF
(append) offsets until our first emit - then prohibited anyone from
trying to re-emit the packet by flagging IRIS_DIRTY_SO_BUFFERS,
because that would re-emit the version with the zeroing of the offset.

Now, we always store 0xFFFFFFFF in the pre-baked packet, and use a
flag to override it to zero on the first emit.  That way, we can
re-emit that packet at any time, and it'll just keep appending.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8964>
2021-03-04 13:59:21 -08:00
Kenneth Graunke
e40fafa991 iris: Defer stream output target space allocation until set time
In the future, Marek is planning to make u_threaded_context call
create_stream_output_target() from a different thread than the main
driver thread, which means that we can't safely use uploaders there.

To prepare for this eventual future, just defer the allocation of
the offset BO 'til later.  It's a very small amount of overhead.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8964>
2021-03-04 13:59:20 -08:00
Kenneth Graunke
5659460af4 iris: Defer uploading of surface states
With u_threaded_context, create_surface and create_sampler_view will
be called from a different thread than the driver thread.  They aren't
allowed to access the context, which means that they can't use the
uploaders there to upload our SURFACE_STATE entries.

Thanks to backing-storage replacement and iris_rebind_buffer, we already
reworked things to maintain CPU-side copies of the SURFACE_STATE entries
and added the ability to upload or re-upload them later.  So we can skip
the upload at object creation time, and add a simple resource-is-NULL
check at binding table upload time to ensure that they get uploaded by
the time we need them.  (They might get uploaded earlier due to rebinds
or clear color updates, but this is the last moment to do so.)

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8964>
2021-03-04 13:59:20 -08:00
Jason Ekstrand
1e53e0d2c7 intel/mi_builder: Drop the gen_ prefix
mi_ is already a unique prefix in Mesa so the gen_ isn't really gaining
us anything except extra characters.  It's possible that MI_ may
conflict a tiny bit with GenXML but it doesn't seem to be a problem
today and we can deal with that in the future if it's ever an issue.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9393>
2021-03-04 15:14:27 +00:00
Jordan Justen
d846901d9d intel/dev: Add devinfo genx10 field
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9329>
2021-03-01 22:00:08 -08:00
Jordan Justen
36dd7c44f6 intel: Use GEN_VERSIONx10 in more places
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9329>
2021-03-01 22:00:08 -08:00
Kenneth Graunke
b9133e48a6 iris: Pin surface state buffers after possibly updating the clear color
On Gen8, updating the clear color will end up allocating new
SURFACE_STATE entries.  These might end up living in a different BO
than the original copies, which means that we have to pin _after_
updating the clear color, not before.

Found by inspection.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9257>
2021-02-24 18:32:29 +00:00
Francisco Jerez
17add74dec iris/gen12: Implement programming of pixel pipe hashing tables.
Straightforward by using the pixel hashing table computation helper
previously introduced, assuming we know the fraction of work that
needs to be submitted to each pixel pipe.  Note that AFAIA the
hardware maps indices in the table to pixel pipes from largest to
smallest, so it shouldn't be necessary to permute indices based on the
physical IDs of the pixel pipes as we are doing on Gen11.

Improves performance of most non-trivial graphics workloads I've tried
on an 80 EU TGL.  E.g. the following testcases improve performance
significantly with sample size 27 and statistical significance 1%:

  gputest/pixmark_piano:      62.89% ±0.10%
  gputest/pixmark_volplosion: 61.51% ±0.06%
  unigine/valley:             26.72% ±0.25%
  gfxbench/gl_5_high:         24.70% ±0.19%
  unigine/heaven:             23.54% ±0.17%
  steam/csgo:                 22.75% ±4.36%
  gfxbench/gl_manhattan31:    22.43% ±0.29%
  gfxbench/gl_4:              20.92% ±0.35%
  warsow/benchsow:            19.15% ±2.53%
  gfxbench/gl_trex_off:       18.84% ±0.27%

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8749>
2021-02-23 21:15:25 -08:00
Francisco Jerez
f9bcdc5bc7 iris/gen11+: Calculate pixel hashing tables instead of hardcoding.
Pixel hashing tables are a pain to type in, review and maintain IMHO.
In order to obtain satisfactory load balancing on all Gen12 parts
currently in production this series would need to add 5 different
additional tables.  Instead this introduces a simple algorithm able to
calculate a table on the fly based on a handful of parameters.

Note that the Gen11 tables generated with this algorithm are not
identical to the hardcoded ones, however the only difference should be
a phase shift that isn't expected to have any effect on performance,
since it shouldn't change the fraction of work submitted to each pixel
pipe.

The CPU overhead from this change is negligible since the tables only
need to be programmed once at context init time.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8749>
2021-02-23 21:15:16 -08:00
Kenneth Graunke
4c4a91abe5 iris: Reference the shader variant for last_vue_map as well
We call update_last_vue_map after updating the shaders, which compares
the new and old VUE maps.  Except...updating the shaders may have
dropped the last reference to the variant that ice->shaders.last_vue_map
belonged to, leading to a classic use-after-free.

Fix this by taking a reference to the variant for the last VUE stage,
so it stays around until we're done with it.

Fixes: 1afed51445 ("iris: Store a list of shader variants in the shader itself")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4311
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9143>
2021-02-19 18:49:19 +00:00
Lionel Landwerlin
207ee2b6a9 isl: add external parameter to isl_mocs()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9127>
2021-02-18 11:20:59 +02:00
Kenneth Graunke
e7dc48c309 iris: Make a pin_scratch_space() helper
We need to (re-)pin the scratch buffer in four different places, and
it's going to get slightly more complicated on future platforms.  So,
make a helper function, allowing us to add the complexity in one spot.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9023>
2021-02-12 21:14:26 +00:00
Kenneth Graunke
4256f7ed58 iris: Fill out scratch base address dynamically
Now that shaders are shared between contexts, we can't pre-bake the
shader scratch address into the derived 3DSTATE_XS packets.  Scratch
buffers are and must be per-context, as multiple contexts could be
executing shaders using scratch at the same time.

So instead, we leave that field blank when pre-filling those packets
up-front, and merge in the actual address when emitting them.  It's
a little more overhead, but only in the case where scratch is used.

Fixes: 84a38ec133 ("iris: Enable PIPE_CAP_SHAREABLE_SHADERS.")
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8922>
2021-02-11 20:51:18 +00:00
Nanley Chery
0079b8543a iris: Fix aux usage of depth buffer prepare/finish
Prepare/finish a framebuffer's depth buffer with the aux usage that's
appropriate for the given miplevel instead of wrongly assuming that
compression is always enabled. Enables code simplifications later on.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8853>
2021-02-10 20:48:01 +00:00
Nanley Chery
a0908d0c91 iris: Drop a stale comment about HiZ sampling
With commit 7339660e80, this comment is no
longer needed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8853>
2021-02-10 20:48:01 +00:00
Kenneth Graunke
f7d4ebbf86 iris: add hooks to call INTEL_MEASURE
These hooks were written in the initial IRIS_MEASURE implementation.
Minor changes by Mark Janes <markjanes@swizzler.org> to adapt to the
INTEL_MEASURE reimplementation.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
2021-02-01 17:24:57 -08:00
Mark Janes
b338bb70e0 iris: add a iris_context reference to iris_batch
This eliminates the need to use container_of in error handling code.
INTEL_MEASURE will need to access the iris context from each batch.

suggested-by: Kenneth Graunke <kenneth@whitecape.org>

Acked-by:     Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
2021-02-01 17:24:57 -08:00
Kenneth Graunke
9d63547f2f iris: Properly handle new unbind_num_trailing_slots parameters
Commits 0278d1fa323cf1f289..b688ea31fcf7e20436 added a new parameter
to set_vertex_buffers(), set_shader_images(), and set_sampler_views()
which specifies a number of trailing slots to unbind.  They updated
the iris functions to do the unbinding, but didn't update the code
to mark which things are bound in the bitfields.  This meant that
later code would assume those unbound slots were bound, and crash
on a NULL dereference.  All that's needed is to add that slot count
when unbinding things in the bitfield.

Fixes: 0278d1fa32 ("gallium: add unbind_num_trailing_slots to set_vertex_buffers")
Fixes: 72ff66c3d7 ("gallium: add unbind_num_trailing_slots to set_shader_images")
Fixes: b688ea31fc ("gallium: add unbind_num_trailing_slots to set_sampler_views")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8758>
2021-01-28 00:54:22 -08:00
Marek Olšák
27dcb46629 gallium: add take_ownership param into set_vertex_buffers to eliminate atomics
There are a few places (mainly u_threaded_context) that do:
   set_vertex_buffers(...);
   for (i = 0; i < count; i++)
      pipe_resource_reference(&buffers[i].resource.buffer, NULL);

set_vertex_buffers increments the reference counts while the loop
decrements them.

This commit eliminates those reference count changes by adding a parameter
into set_vertex_buffers that tells the callee to accept all buffers
without incrementing the reference counts.

AMD Zen benefits from this because it has slow atomics if they come from
different CCXs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8298>
2021-01-27 23:53:35 +00:00
Marek Olšák
b688ea31fc gallium: add unbind_num_trailing_slots to set_sampler_views
Instead of calling this functions again to unbind trailing slots,
extend it to do it when binding. This reduces CPU overhead.

A lot of drivers ignore "start" and always unbind all slots after "count".
Such drivers don't need any changes here.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8298>
2021-01-27 23:53:35 +00:00