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intel: Rename gen field in gen_device_info struct to ver

Browse source 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)gen" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)gen/info\1\2ver/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
This commit is contained in:
Anuj Phogat 2021-03-29 14:41:58 -07:00 • committed by Marge Bot
parent 99331f6deb
commit abe9a71a09
166 changed files with 1904 additions and 1904 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/gallium/drivers/iris/iris_blit.c
View file

@ -302,7 +302,7 @@ tex_cache_flush_hack(struct iris_batch *batch,
* Icelake (Gen11+) claims to fix this issue, but seems to still have
* issues with ASTC formats.
*/
bool need_flush = devinfo->gen >= 11 ?
bool need_flush = devinfo->ver >= 11 ?
is_astc(surf_format) != is_astc(view_format) :
view_format != surf_format;
if (!need_flush)
@ -590,7 +590,7 @@ get_copy_region_aux_settings(struct iris_context *ice,
* blorp_copy isn't guaranteed to access the same components as the
* original format (e.g. A8_UNORM/R8_UINT).
*/
*out_clear_supported = (devinfo->gen >= 11 && !is_render_target) ||
*out_clear_supported = (devinfo->ver >= 11 && !is_render_target) ||
(res->aux.clear_color.u32[0] == 0 &&
res->aux.clear_color.u32[1] == 0 &&
res->aux.clear_color.u32[2] == 0 &&

2
src/gallium/drivers/iris/iris_bufmgr.c
View file

@ -1866,7 +1866,7 @@ iris_bufmgr_create(struct gen_device_info *devinfo, int fd, bool bo_reuse)
* - Color Calc State Pointer
*/
const uint64_t dynamic_pool_size =
(devinfo->gen >= 12 ? _2GB : _4GB_minus_1) - IRIS_BORDER_COLOR_POOL_SIZE;
(devinfo->ver >= 12 ? _2GB : _4GB_minus_1) - IRIS_BORDER_COLOR_POOL_SIZE;
util_vma_heap_init(&bufmgr->vma_allocator[IRIS_MEMZONE_DYNAMIC],
IRIS_MEMZONE_DYNAMIC_START + IRIS_BORDER_COLOR_POOL_SIZE,
dynamic_pool_size);

2
src/gallium/drivers/iris/iris_clear.c
View file

@ -54,7 +54,7 @@ iris_is_color_fast_clear_compatible(struct iris_context *ice,
continue;
}
if (devinfo->gen < 9 &&
if (devinfo->ver < 9 &&
color.f32[i] != 0.0f && color.f32[i] != 1.0f) {
return false;
}

2
src/gallium/drivers/iris/iris_draw.c
View file

@ -267,7 +267,7 @@ iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,
iris_update_draw_info(ice, info);
if (devinfo->gen == 9)
if (devinfo->ver == 9)
gen9_toggle_preemption(ice, batch, info);
iris_update_compiled_shaders(ice);

4
src/gallium/drivers/iris/iris_formats.c
View file

@ -112,7 +112,7 @@ iris_is_format_supported(struct pipe_screen *pscreen,
{
struct iris_screen *screen = (struct iris_screen *) pscreen;
const struct gen_device_info *devinfo = &screen->devinfo;
uint32_t max_samples = devinfo->gen == 8 ? 8 : 16;
uint32_t max_samples = devinfo->ver == 8 ? 8 : 16;
if (sample_count > max_samples ||
!util_is_power_of_two_or_zero(sample_count))
@ -213,7 +213,7 @@ iris_is_format_supported(struct pipe_screen *pscreen,
* a complex sampler workaround (see i965's gen9_apply_astc5x5_wa_flush).
* Without it, st/mesa will emulate ASTC 5x5 via uncompressed textures.
*/
if (devinfo->gen == 9 && (format == ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 ||
if (devinfo->ver == 9 && (format == ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 ||
format == ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB))
return false;

38
src/gallium/drivers/iris/iris_program.c
View file

@ -65,7 +65,7 @@ iris_to_brw_vs_key(const struct gen_device_info *devinfo,
const struct iris_vs_prog_key *key)
{
return (struct brw_vs_prog_key) {
BRW_KEY_INIT(devinfo->gen, key->vue.base.program_string_id),
BRW_KEY_INIT(devinfo->ver, key->vue.base.program_string_id),
/* Don't tell the backend about our clip plane constants, we've
* already lowered them in NIR and don't want it doing it again.
@ -79,7 +79,7 @@ iris_to_brw_tcs_key(const struct gen_device_info *devinfo,
const struct iris_tcs_prog_key *key)
{
return (struct brw_tcs_prog_key) {
BRW_KEY_INIT(devinfo->gen, key->vue.base.program_string_id),
BRW_KEY_INIT(devinfo->ver, key->vue.base.program_string_id),
.tes_primitive_mode = key->tes_primitive_mode,
.input_vertices = key->input_vertices,
.patch_outputs_written = key->patch_outputs_written,
@ -93,7 +93,7 @@ iris_to_brw_tes_key(const struct gen_device_info *devinfo,
const struct iris_tes_prog_key *key)
{
return (struct brw_tes_prog_key) {
BRW_KEY_INIT(devinfo->gen, key->vue.base.program_string_id),
BRW_KEY_INIT(devinfo->ver, key->vue.base.program_string_id),
.patch_inputs_read = key->patch_inputs_read,
.inputs_read = key->inputs_read,
};
@ -104,7 +104,7 @@ iris_to_brw_gs_key(const struct gen_device_info *devinfo,
const struct iris_gs_prog_key *key)
{
return (struct brw_gs_prog_key) {
BRW_KEY_INIT(devinfo->gen, key->vue.base.program_string_id),
BRW_KEY_INIT(devinfo->ver, key->vue.base.program_string_id),
};
}
@ -113,7 +113,7 @@ iris_to_brw_fs_key(const struct gen_device_info *devinfo,
const struct iris_fs_prog_key *key)
{
return (struct brw_wm_prog_key) {
BRW_KEY_INIT(devinfo->gen, key->base.program_string_id),
BRW_KEY_INIT(devinfo->ver, key->base.program_string_id),
.nr_color_regions = key->nr_color_regions,
.flat_shade = key->flat_shade,
.alpha_test_replicate_alpha = key->alpha_test_replicate_alpha,
@ -134,7 +134,7 @@ iris_to_brw_cs_key(const struct gen_device_info *devinfo,
const struct iris_cs_prog_key *key)
{
return (struct brw_cs_prog_key) {
BRW_KEY_INIT(devinfo->gen, key->base.program_string_id),
BRW_KEY_INIT(devinfo->ver, key->base.program_string_id),
};
}
@ -484,7 +484,7 @@ iris_setup_uniforms(const struct brw_compiler *compiler,
patch_vert_idx * sizeof(uint32_t));
break;
case nir_intrinsic_image_deref_load_param_intel: {
assert(devinfo->gen < 9);
assert(devinfo->ver < 9);
nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
nir_variable *var = nir_deref_instr_get_variable(deref);
@ -813,7 +813,7 @@ iris_setup_binding_table(const struct gen_device_info *devinfo,
/* Setup render target read surface group in order to support non-coherent
* framebuffer fetch on Gen8
*/
if (devinfo->gen == 8 && info->outputs_read) {
if (devinfo->ver == 8 && info->outputs_read) {
bt->sizes[IRIS_SURFACE_GROUP_RENDER_TARGET_READ] = num_render_targets;
bt->used_mask[IRIS_SURFACE_GROUP_RENDER_TARGET_READ] =
BITFIELD64_MASK(num_render_targets);
@ -857,7 +857,7 @@ iris_setup_binding_table(const struct gen_device_info *devinfo,
break;
case nir_intrinsic_load_output:
if (devinfo->gen == 8) {
if (devinfo->ver == 8) {
mark_used_with_src(bt, &intrin->src[0],
IRIS_SURFACE_GROUP_RENDER_TARGET_READ);
}
@ -988,7 +988,7 @@ iris_setup_binding_table(const struct gen_device_info *devinfo,
break;
case nir_intrinsic_load_output:
if (devinfo->gen == 8) {
if (devinfo->ver == 8) {
rewrite_src_with_bti(&b, bt, instr, &intrin->src[0],
IRIS_SURFACE_GROUP_RENDER_TARGET_READ);
}
@ -1446,7 +1446,7 @@ iris_update_compiled_tcs(struct iris_context *ice)
.tes_primitive_mode = tes_info->tess.primitive_mode,
.input_vertices =
!tcs || compiler->use_tcs_8_patch ? ice->state.vertices_per_patch : 0,
.quads_workaround = devinfo->gen < 9 &&
.quads_workaround = devinfo->ver < 9 &&
tes_info->tess.primitive_mode == GL_QUADS &&
tes_info->tess.spacing == TESS_SPACING_EQUAL,
};
@ -1769,7 +1769,7 @@ iris_compile_fs(struct iris_screen *screen,
* and do not need a binding table entry with a null surface. Earlier
* generations need an entry for a null surface.
*/
int null_rts = devinfo->gen < 11 ? 1 : 0;
int null_rts = devinfo->ver < 11 ? 1 : 0;
struct iris_binding_table bt;
iris_setup_binding_table(devinfo, nir, &bt,
@ -2168,21 +2168,21 @@ iris_get_scratch_space(struct iris_context *ice,
* in the base configuration.
*/
unsigned subslice_total = screen->subslice_total;
if (devinfo->gen == 12)
if (devinfo->ver == 12)
subslice_total = (devinfo->is_dg1 || devinfo->gt == 2 ? 6 : 2);
else if (devinfo->gen == 11)
else if (devinfo->ver == 11)
subslice_total = 8;
else if (devinfo->gen < 11)
else if (devinfo->ver < 11)
subslice_total = 4 * devinfo->num_slices;
assert(subslice_total >= screen->subslice_total);
if (!*bop) {
unsigned scratch_ids_per_subslice = devinfo->max_cs_threads;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
/* Same as ICL below, but with 16 EUs. */
scratch_ids_per_subslice = 16 * 8;
} else if (devinfo->gen == 11) {
} else if (devinfo->ver == 11) {
/* The MEDIA_VFE_STATE docs say:
*
* "Starting with this configuration, the Maximum Number of
@ -2437,7 +2437,7 @@ iris_create_fs_state(struct pipe_context *ctx,
struct iris_fs_prog_key key = {
KEY_ID(base),
.nr_color_regions = util_bitcount(color_outputs),
.coherent_fb_fetch = devinfo->gen >= 9,
.coherent_fb_fetch = devinfo->ver >= 9,
.input_slots_valid =
can_rearrange_varyings ? 0 : info->inputs_read | VARYING_BIT_POS,
};
@ -2697,7 +2697,7 @@ iris_bind_fs_state(struct pipe_context *ctx, void *state)
(new_ish->nir->info.outputs_written & color_bits))
ice->state.dirty |= IRIS_DIRTY_PS_BLEND;
if (devinfo->gen == 8)
if (devinfo->ver == 8)
ice->state.dirty |= IRIS_DIRTY_PMA_FIX;
bind_shader_state((void *) ctx, state, MESA_SHADER_FRAGMENT);

2
src/gallium/drivers/iris/iris_resolve.c
View file

@ -215,7 +215,7 @@ iris_predraw_resolve_framebuffer(struct iris_context *ice,
}
}
if (devinfo->gen == 8 && nir->info.outputs_read != 0) {
if (devinfo->ver == 8 && nir->info.outputs_read != 0) {
for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
if (cso_fb->cbufs[i]) {
struct iris_surface *surf = (void *) cso_fb->cbufs[i];

16
src/gallium/drivers/iris/iris_resource.c
View file

@ -82,12 +82,12 @@ modifier_is_supported(const struct gen_device_info *devinfo,
case I915_FORMAT_MOD_Y_TILED:
break;
case I915_FORMAT_MOD_Y_TILED_CCS:
if (devinfo->gen <= 8 || devinfo->gen >= 12)
if (devinfo->ver <= 8 || devinfo->ver >= 12)
return false;
break;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (devinfo->gen != 12)
if (devinfo->ver != 12)
return false;
break;
case DRM_FORMAT_MOD_INVALID:
@ -295,7 +295,7 @@ iris_image_view_get_format(struct iris_context *ice,
* limited number of formats), and if not possible, fall back
* to untyped reads.
*/
if (devinfo->gen == 8 &&
if (devinfo->ver == 8 &&
!isl_has_matching_typed_storage_image_format(devinfo, isl_fmt))
return ISL_FORMAT_RAW;
else
@ -354,7 +354,7 @@ iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
switch (target) {
case PIPE_TEXTURE_1D:
case PIPE_TEXTURE_1D_ARRAY:
return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ?
return (devinfo->ver >= 9 && tiling == ISL_TILING_LINEAR ?
ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D);
case PIPE_TEXTURE_2D:
@ -365,7 +365,7 @@ iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
return ISL_DIM_LAYOUT_GEN4_2D;
case PIPE_TEXTURE_3D:
return (devinfo->gen >= 9 ?
return (devinfo->ver >= 9 ?
ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D);
case PIPE_MAX_TEXTURE_TYPES:
@ -481,7 +481,7 @@ static unsigned
iris_get_aux_clear_color_state_size(struct iris_screen *screen)
{
const struct gen_device_info *devinfo = &screen->devinfo;
return devinfo->gen >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0;
return devinfo->ver >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0;
}
static void
@ -489,7 +489,7 @@ map_aux_addresses(struct iris_screen *screen, struct iris_resource *res,
enum isl_format format, unsigned plane)
{
const struct gen_device_info *devinfo = &screen->devinfo;
if (devinfo->gen >= 12 && isl_aux_usage_has_ccs(res->aux.usage)) {
if (devinfo->ver >= 12 && isl_aux_usage_has_ccs(res->aux.usage)) {
void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
assert(aux_map_ctx);
const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ?
@ -678,7 +678,7 @@ iris_resource_configure_aux(struct iris_screen *screen,
res->aux.possible_usages |= 1 << ISL_AUX_USAGE_STC_CCS;
} else if (has_ccs) {
if (want_ccs_e_for_format(devinfo, res->surf.format)) {
res->aux.possible_usages |= devinfo->gen < 12 ?
res->aux.possible_usages |= devinfo->ver < 12 ?
1 << ISL_AUX_USAGE_CCS_E : 1 << ISL_AUX_USAGE_GEN12_CCS_E;
} else if (isl_format_supports_ccs_d(devinfo, res->surf.format)) {
res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;

10
src/gallium/drivers/iris/iris_screen.c
View file

@ -269,9 +269,9 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
return devinfo->gen >= 9;
return devinfo->ver >= 9;
case PIPE_CAP_DEPTH_BOUNDS_TEST:
return devinfo->gen >= 12;
return devinfo->ver >= 12;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
return 1;
case PIPE_CAP_MAX_RENDER_TARGETS:
@ -399,7 +399,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
* version 8 and 9, because generated VERTEX_BUFFER_STATEs are cached
* separately.
*/
return devinfo->gen >= 11;
return devinfo->ver >= 11;
default:
return u_pipe_screen_get_param_defaults(pscreen, param);
@ -786,7 +786,7 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
p_atomic_set(&screen->refcount, 1);
if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
if (screen->devinfo.ver < 8 || screen->devinfo.is_cherryview)
return NULL;
bool bo_reuse = false;
@ -836,7 +836,7 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
screen->compiler->supports_pull_constants = false;
screen->compiler->supports_shader_constants = true;
screen->compiler->compact_params = false;
screen->compiler->indirect_ubos_use_sampler = screen->devinfo.gen < 12;
screen->compiler->indirect_ubos_use_sampler = screen->devinfo.ver < 12;
screen->l3_config_3d = iris_get_default_l3_config(&screen->devinfo, false);
screen->l3_config_cs = iris_get_default_l3_config(&screen->devinfo, true);

2
src/gallium/drivers/iris/iris_state.c
View file

@ -2397,7 +2397,7 @@ fill_surface_state(struct isl_device *isl_dev,
iris_resource_get_clear_color(res, &clear_bo, &clear_offset);
if (clear_bo) {
f.clear_address = clear_bo->gtt_offset + clear_offset;
f.use_clear_address = isl_dev->info->gen > 9;
f.use_clear_address = isl_dev->info->ver > 9;
}
}

8
src/intel/blorp/blorp.c
View file

@ -138,7 +138,7 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
/* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
* layered rendering.
*/
if (is_render_target && blorp->isl_dev->info->gen <= 6)
if (is_render_target && blorp->isl_dev->info->ver <= 6)
info->view.array_len = MIN2(info->view.array_len, 512);
if (surf->tile_x_sa || surf->tile_y_sa) {
@ -210,7 +210,7 @@ blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
nir_remove_dead_variables(nir, nir_var_shader_in, NULL);
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
if (blorp->compiler->devinfo->gen < 6) {
if (blorp->compiler->devinfo->ver < 6) {
if (nir->info.fs.uses_discard)
wm_key->iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
@ -281,7 +281,7 @@ blorp_ensure_sf_program(struct blorp_batch *batch,
assert(params->wm_prog_data);
/* Gen6+ doesn't need a strips and fans program */
if (blorp->compiler->devinfo->gen >= 6)
if (blorp->compiler->devinfo->ver >= 6)
return true;
struct blorp_sf_key key = {
@ -400,7 +400,7 @@ blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
/* TODO: What about MSAA? */
params.depth.surf.logical_level0_px.width = params.x1;
params.depth.surf.logical_level0_px.height = params.y1;
} else if (devinfo->gen >= 8 && devinfo->gen <= 9 &&
} else if (devinfo->ver >= 8 && devinfo->ver <= 9 &&
op == ISL_AUX_OP_AMBIGUATE) {
/* On some platforms, it's not enough to just adjust the clear
* rectangle when the LOD is greater than 0.

30
src/intel/blorp/blorp_blit.c
View file

@ -1205,7 +1205,7 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp, void *mem_ctx,
/* Render target and texture hardware don't support W tiling until Gen8. */
const bool rt_tiled_w = false;
const bool tex_tiled_w = devinfo->gen >= 8 && key->src_tiled_w;
const bool tex_tiled_w = devinfo->ver >= 8 && key->src_tiled_w;
/* The address that data will be written to is determined by the
* coordinates supplied to the WM thread and the tiling and sample count of
@ -1360,7 +1360,7 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp, void *mem_ctx,
*/
src_pos = nir_f2i32(&b, nir_channels(&b, src_pos, 0x3));
if (devinfo->gen == 6) {
if (devinfo->ver == 6) {
/* Because gen6 only supports 4x interleved MSAA, we can do all the
* blending we need with a single linear-interpolated texture lookup
* at the center of the sample. The texture coordinates to be odd
@ -1642,12 +1642,12 @@ blorp_surf_retile_w_to_y(const struct isl_device *isl_dev,
*
* TODO: Are we sure we don't also need to fake it on gen6?
*/
if (isl_dev->info->gen > 6 &&
if (isl_dev->info->ver > 6 &&
info->surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
blorp_surf_fake_interleaved_msaa(isl_dev, info);
}
if (isl_dev->info->gen == 6) {
if (isl_dev->info->ver == 6) {
/* Gen6 stencil buffers have a very large alignment coming in from the
* miptree. It's out-of-bounds for what the surface state can handle.
* Since we have a single layer and level, it doesn't really matter as
@ -1697,7 +1697,7 @@ static unsigned
get_max_surface_size(const struct gen_device_info *devinfo,
const struct brw_blorp_surface_info *surf)
{
const unsigned max = devinfo->gen >= 7 ? 16384 : 8192;
const unsigned max = devinfo->ver >= 7 ? 16384 : 8192;
if (split_blorp_blit_debug && can_shrink_surface(surf))
return max >> 4; /* A smaller restriction when debug is enabled */
else
@ -1805,7 +1805,7 @@ try_blorp_blit(struct blorp_batch *batch,
const struct gen_device_info *devinfo = batch->blorp->isl_dev->info;
if (params->dst.surf.usage & ISL_SURF_USAGE_DEPTH_BIT) {
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
/* We can render as depth on Gen5 but there's no real advantage since
* it doesn't support MSAA or HiZ. On Gen4, we can't always render
* to depth due to issues with depth buffers and mip-mapping. On
@ -1819,7 +1819,7 @@ try_blorp_blit(struct blorp_batch *batch,
}
} else if (params->dst.surf.usage & ISL_SURF_USAGE_STENCIL_BIT) {
assert(params->dst.surf.format == ISL_FORMAT_R8_UINT);
if (devinfo->gen >= 9) {
if (devinfo->ver >= 9) {
wm_prog_key->dst_usage = ISL_SURF_USAGE_STENCIL_BIT;
} else {
wm_prog_key->dst_usage = ISL_SURF_USAGE_RENDER_TARGET_BIT;
@ -1866,7 +1866,7 @@ try_blorp_blit(struct blorp_batch *batch,
coords->y.mirror);
if (devinfo->gen == 4) {
if (devinfo->ver == 4) {
/* The MinLOD and MinimumArrayElement don't work properly for cube maps.
* Convert them to a single slice on gen4.
*/
@ -1881,7 +1881,7 @@ try_blorp_blit(struct blorp_batch *batch,
}
}
if (devinfo->gen > 6 &&
if (devinfo->ver > 6 &&
!isl_surf_usage_is_depth_or_stencil(wm_prog_key->dst_usage) &&
params->dst.surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
assert(params->dst.surf.samples > 1);
@ -1984,7 +1984,7 @@ try_blorp_blit(struct blorp_batch *batch,
}
}
if (devinfo->gen < 8 && params->src.surf.tiling == ISL_TILING_W) {
if (devinfo->ver < 8 && params->src.surf.tiling == ISL_TILING_W) {
/* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
* Broadwell adds support for sampling from stencil.
*
@ -2024,7 +2024,7 @@ try_blorp_blit(struct blorp_batch *batch,
if ((wm_prog_key->filter == BLORP_FILTER_AVERAGE ||
wm_prog_key->filter == BLORP_FILTER_BILINEAR) &&
batch->blorp->isl_dev->info->gen <= 6) {
batch->blorp->isl_dev->info->ver <= 6) {
/* Gen4-5 don't support non-normalized texture coordinates */
wm_prog_key->src_coords_normalized = true;
params->wm_inputs.src_inv_size[0] =
@ -2073,7 +2073,7 @@ try_blorp_blit(struct blorp_batch *batch,
params->dst.view.format = ISL_FORMAT_R32_UINT;
}
if (devinfo->gen <= 7 && !devinfo->is_haswell &&
if (devinfo->ver <= 7 && !devinfo->is_haswell &&
!isl_swizzle_is_identity(params->src.view.swizzle)) {
wm_prog_key->src_swizzle = params->src.view.swizzle;
params->src.view.swizzle = ISL_SWIZZLE_IDENTITY;
@ -2341,7 +2341,7 @@ blorp_blit(struct blorp_batch *batch,
if (dst_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) {
assert(src_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT);
/* Prior to Broadwell, we can't render to R8_UINT */
if (batch->blorp->isl_dev->info->gen < 8) {
if (batch->blorp->isl_dev->info->ver < 8) {
src_format = ISL_FORMAT_R8_UNORM;
dst_format = ISL_FORMAT_R8_UNORM;
}
@ -2673,7 +2673,7 @@ blorp_copy(struct blorp_batch *batch,
params.src.view.format = params.src.surf.format;
params.dst.view.format = params.src.surf.format;
} else if ((params.dst.surf.usage & ISL_SURF_USAGE_DEPTH_BIT) &&
isl_dev->info->gen >= 7) {
isl_dev->info->ver >= 7) {
/* On Gen7 and higher, we use actual depth writes for blits into depth
* buffers so we need the real format.
*/
@ -2849,7 +2849,7 @@ blorp_buffer_copy(struct blorp_batch *batch,
uint64_t copy_size = size;
/* This is maximum possible width/height our HW can handle */
uint64_t max_surface_dim = 1 << (devinfo->gen >= 7 ? 14 : 13);
uint64_t max_surface_dim = 1 << (devinfo->ver >= 7 ? 14 : 13);
/* First, we compute the biggest format that can be used with the
* given offsets and size.

20
src/intel/blorp/blorp_clear.c
View file

@ -242,9 +242,9 @@ get_fast_clear_rect(const struct isl_device *dev,
/* The line alignment requirement for Y-tiled is halved at SKL and again
* at TGL.
*/
if (dev->info->gen >= 12)
if (dev->info->ver >= 12)
y_align *= 8;
else if (dev->info->gen >= 9)
else if (dev->info->ver >= 9)
y_align *= 16;
else
y_align *= 32;
@ -436,7 +436,7 @@ blorp_clear(struct blorp_batch *batch,
use_simd16_replicated_data = false;
/* Replicated clears don't work yet before gen6 */
if (batch->blorp->isl_dev->info->gen < 6)
if (batch->blorp->isl_dev->info->ver < 6)
use_simd16_replicated_data = false;
/* Constant color writes ignore everyting in blend and color calculator
@ -480,7 +480,7 @@ blorp_clear(struct blorp_batch *batch,
/* The MinLOD and MinimumArrayElement don't work properly for cube maps.
* Convert them to a single slice on gen4.
*/
if (batch->blorp->isl_dev->info->gen == 4 &&
if (batch->blorp->isl_dev->info->ver == 4 &&
(params.dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT)) {
blorp_surf_convert_to_single_slice(batch->blorp->isl_dev, &params.dst);
}
@ -763,9 +763,9 @@ blorp_can_hiz_clear_depth(const struct gen_device_info *devinfo,
uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1)
{
/* This function currently doesn't support any gen prior to gen8 */
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
if (devinfo->gen == 8 && surf->format == ISL_FORMAT_R16_UNORM) {
if (devinfo->ver == 8 && surf->format == ISL_FORMAT_R16_UNORM) {
/* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
* block with the following property: as the number of samples increases,
* the number of pixels representable by this block decreases by a factor
@ -1108,11 +1108,11 @@ blorp_ccs_resolve(struct blorp_batch *batch,
params.x1 = ALIGN(params.x1, x_scaledown) / x_scaledown;
params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
if (batch->blorp->isl_dev->info->gen >= 10) {
if (batch->blorp->isl_dev->info->ver >= 10) {
assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE ||
resolve_op == ISL_AUX_OP_AMBIGUATE);
} else if (batch->blorp->isl_dev->info->gen >= 9) {
} else if (batch->blorp->isl_dev->info->ver >= 9) {
assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
} else {
@ -1192,7 +1192,7 @@ blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch *batch,
nir_discard_if(&b, nir_inot(&b, is_clear));
nir_ssa_def *clear_color = nir_load_var(&b, v_color);
if (blorp_key.indirect_clear_color && blorp->isl_dev->info->gen <= 8) {
if (blorp_key.indirect_clear_color && blorp->isl_dev->info->ver <= 8) {
/* Gen7-8 clear colors are stored as single 0/1 bits */
clear_color = nir_vec4(&b, blorp_nir_bit(&b, clear_color, 31),
blorp_nir_bit(&b, clear_color, 30),
@ -1236,7 +1236,7 @@ blorp_mcs_partial_resolve(struct blorp_batch *batch,
blorp_params_init(&params);
params.snapshot_type = INTEL_SNAPSHOT_MCS_PARTIAL_RESOLVE;
assert(batch->blorp->isl_dev->info->gen >= 7);
assert(batch->blorp->isl_dev->info->ver >= 7);
params.x0 = 0;
params.y0 = 0;

2
src/intel/blorp/blorp_genX_exec.h
View file

@ -417,7 +417,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
{
const unsigned num_varyings =
params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0;
bool need_ndc = batch->blorp->compiler->devinfo->gen <= 5;
bool need_ndc = batch->blorp->compiler->devinfo->ver <= 5;
const unsigned num_elements = 2 + need_ndc + num_varyings;
struct GENX(VERTEX_ELEMENT_STATE) ve[num_elements];

2
src/intel/common/intel_aux_map.c
View file

@ -203,7 +203,7 @@ intel_aux_map_init(void *driver_ctx,
const struct gen_device_info *devinfo)
{
struct intel_aux_map_context *ctx;
if (devinfo->gen < 12)
if (devinfo->ver < 12)
return NULL;
ctx = ralloc(NULL, struct intel_aux_map_context);

2
src/intel/common/intel_batch_decoder.c
View file

@ -572,7 +572,7 @@ decode_single_ksp(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
struct intel_group *inst = intel_ctx_find_instruction(ctx, p);
uint64_t ksp = 0;
bool is_simd8 = ctx->devinfo.gen >= 11; /* vertex shaders on Gen8+ only */
bool is_simd8 = ctx->devinfo.ver >= 11; /* vertex shaders on Gen8+ only */
bool is_enabled = true;
struct intel_field_iterator iter;

4
src/intel/common/intel_decoder.c
View file

@ -511,10 +511,10 @@ static int
devinfo_to_gen(const struct gen_device_info *devinfo, bool x10)
{
if (devinfo->is_baytrail || devinfo->is_haswell) {
return devinfo->gen * 10 + 5;
return devinfo->ver * 10 + 5;
}
return x10 ? devinfo->gen * 10 : devinfo->gen;
return x10 ? devinfo->ver * 10 : devinfo->ver;
}
static uint32_t zlib_inflate(const void *compressed_data,

16
src/intel/common/intel_l3_config.c
View file

@ -163,7 +163,7 @@ DECLARE_L3_LIST(dg1);
static const struct intel_l3_list *
get_l3_list(const struct gen_device_info *devinfo)
{
switch (devinfo->gen) {
switch (devinfo->ver) {
case 7:
return (devinfo->is_baytrail ? &vlv_l3_list : &ivb_l3_list);
@ -262,10 +262,10 @@ intel_get_default_l3_weights(const struct gen_device_info *devinfo,
{
struct intel_l3_weights w = {{ 0 }};
w.w[INTEL_L3P_SLM] = devinfo->gen < 11 && needs_slm;
w.w[INTEL_L3P_SLM] = devinfo->ver < 11 && needs_slm;
w.w[INTEL_L3P_URB] = 1.0;
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
w.w[INTEL_L3P_ALL] = 1.0;
} else {
w.w[INTEL_L3P_DC] = needs_dc ? 0.1 : 0;
@ -285,7 +285,7 @@ intel_get_default_l3_config(const struct gen_device_info *devinfo)
* default configuration.
*/
const struct intel_l3_list *const list = get_l3_list(devinfo);
assert(list->length > 0 || devinfo->gen >= 12);
assert(list->length > 0 || devinfo->ver >= 12);
if (list->length > 0) {
const struct intel_l3_config *const cfg = &list->configs[0];
assert(cfg == intel_get_l3_config(devinfo,
@ -319,7 +319,7 @@ intel_get_l3_config(const struct gen_device_info *devinfo,
}
}
assert(cfg_best || devinfo->gen >= 12);
assert(cfg_best || devinfo->ver >= 12);
return cfg_best;
}
@ -330,7 +330,7 @@ static unsigned
get_l3_way_size(const struct gen_device_info *devinfo)
{
const unsigned way_size_per_bank =
(devinfo->gen >= 9 && devinfo->l3_banks == 1) || devinfo->gen >= 11 ?
(devinfo->ver >= 9 && devinfo->l3_banks == 1) || devinfo->ver >= 11 ?
4 : 2;
assert(devinfo->l3_banks);
@ -344,7 +344,7 @@ get_l3_way_size(const struct gen_device_info *devinfo)
static unsigned
get_urb_size_scale(const struct gen_device_info *devinfo)
{
return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
return (devinfo->ver >= 8 ? devinfo->num_slices : 1);
}
unsigned
@ -363,7 +363,7 @@ intel_get_l3_config_urb_size(const struct gen_device_info *devinfo,
* allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
* only 1008KB of this will be used."
*/
const unsigned max = (devinfo->gen == 9 ? 1008 : ~0);
const unsigned max = (devinfo->ver == 9 ? 1008 : ~0);
return MIN2(max, cfg->n[INTEL_L3P_URB] * get_l3_way_size(devinfo)) /
get_urb_size_scale(devinfo);
}

8
src/intel/common/intel_urb_config.c
View file

@ -84,11 +84,11 @@ intel_get_urb_config(const struct gen_device_info *devinfo,
* only 124KB (per bank). More detailed descripton available in "L3
* Cache" section of the B-Spec."
*/
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
urb_size_kB -= 4 * devinfo->l3_banks;
const unsigned push_constant_kB =
(devinfo->gen >= 8 || (devinfo->is_haswell && devinfo->gt == 3)) ? 32 : 16;
(devinfo->ver >= 8 || (devinfo->is_haswell && devinfo->gt == 3)) ? 32 : 16;
const bool active[4] = { true, tess_present, tess_present, gs_present };
@ -118,7 +118,7 @@ intel_get_urb_config(const struct gen_device_info *devinfo,
* "When tessellation is enabled, the VS Number of URB Entries must be
* greater than or equal to 192."
*/
[MESA_SHADER_VERTEX] = tess_present && devinfo->gen == 8 ?
[MESA_SHADER_VERTEX] = tess_present && devinfo->ver == 8 ?
192 : devinfo->urb.min_entries[MESA_SHADER_VERTEX],
/* There are two constraints on the minimum amount of URB space we can
@ -235,7 +235,7 @@ intel_get_urb_config(const struct gen_device_info *devinfo,
}
if (deref_block_size) {
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
/* From the Gen12 BSpec:
*
* "Deref Block size depends on the last enabled shader and number

2
src/intel/common/tests/mi_builder_test.cpp
View file

@ -194,7 +194,7 @@ mi_builder_test::SetUp()
(void *)&getparam), 0) << strerror(errno);
ASSERT_TRUE(gen_get_device_info_from_pci_id(device_id, &devinfo));
if (devinfo.gen != GFX_VER || devinfo.is_haswell != (GFX_VERx10 == 75)) {
if (devinfo.ver != GFX_VER || devinfo.is_haswell != (GFX_VERx10 == 75)) {
close(fd);
fd = -1;
continue;

2
src/intel/compiler/brw_clip_line.c
View file

@ -81,7 +81,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
c->reg.clipdistance_offset = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_W);
i++;
if (devinfo->gen == 5) {
if (devinfo->ver == 5) {
c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
i++;
}

2
src/intel/compiler/brw_clip_tri.c
View file

@ -117,7 +117,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
c->reg.clipdistance_offset = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_W);
i++;
if (devinfo->gen == 5) {
if (devinfo->ver == 5) {
c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
i++;
}

6
src/intel/compiler/brw_clip_util.c
View file

@ -424,7 +424,7 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
/* Rearrange userclip outcodes so that they come directly after
* the fixed plane bits.
*/
if (p->devinfo->gen == 5 || p->devinfo->is_g4x)
if (p->devinfo->ver == 5 || p->devinfo->is_g4x)
brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14));
else
brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
@ -440,7 +440,7 @@ void brw_clip_ff_sync(struct brw_clip_compile *c)
{
struct brw_codegen *p = &c->func;
if (p->devinfo->gen == 5) {
if (p->devinfo->ver == 5) {
brw_AND(p, brw_null_reg(), c->reg.ff_sync, brw_imm_ud(0x1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
brw_IF(p, BRW_EXECUTE_1);
@ -463,7 +463,7 @@ void brw_clip_init_ff_sync(struct brw_clip_compile *c)
{
struct brw_codegen *p = &c->func;
if (p->devinfo->gen == 5) {
if (p->devinfo->ver == 5) {
brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0));
}
}

4
src/intel/compiler/brw_compile_sf.c
View file

@ -226,7 +226,7 @@ static void do_flatshade_triangle( struct brw_sf_compile *c )
if (c->key.primitive == BRW_SF_PRIM_UNFILLED_TRIS)
return;
if (p->devinfo->gen == 5)
if (p->devinfo->ver == 5)
jmpi = 2;
nr = count_flatshaded_attributes(c);
@ -258,7 +258,7 @@ static void do_flatshade_line( struct brw_sf_compile *c )
if (c->key.primitive == BRW_SF_PRIM_UNFILLED_TRIS)
return;
if (p->devinfo->gen == 5)
if (p->devinfo->ver == 5)
jmpi = 2;
nr = count_flatshaded_attributes(c);

28
src/intel/compiler/brw_compiler.c
View file

@ -106,15 +106,15 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
compiler->use_tcs_8_patch =
devinfo->gen >= 12 ||
(devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH));
devinfo->ver >= 12 ||
(devinfo->ver >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH));
/* Default to the sampler since that's what we've done since forever */
compiler->indirect_ubos_use_sampler = true;
/* There is no vec4 mode on Gen10+, and we don't use it at all on Gen8+. */
for (int i = MESA_SHADER_VERTEX; i < MESA_ALL_SHADER_STAGES; i++) {
compiler->scalar_stage[i] = devinfo->gen >= 8 ||
compiler->scalar_stage[i] = devinfo->ver >= 8 ||
i == MESA_SHADER_FRAGMENT || i == MESA_SHADER_COMPUTE;
}
@ -148,14 +148,14 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
* destination type can be Quadword and source type Doubleword for Gen8 and
* Gen9. So, lower 64 bit multiply instruction on rest of the platforms.
*/
if (devinfo->gen < 8 || devinfo->gen > 9)
if (devinfo->ver < 8 || devinfo->ver > 9)
int64_options |= nir_lower_imul_2x32_64;
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
compiler->glsl_compiler_options[i].MaxIfDepth =
devinfo->gen < 6 ? 16 : UINT_MAX;
devinfo->ver < 6 ? 16 : UINT_MAX;
/* We handle this in NIR */
compiler->glsl_compiler_options[i].EmitNoIndirectInput = false;
@ -177,20 +177,20 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
/* Prior to Gen6, there are no three source operations, and Gen11 loses
* LRP.
*/
nir_options->lower_ffma16 = devinfo->gen < 6;
nir_options->lower_ffma32 = devinfo->gen < 6;
nir_options->lower_ffma64 = devinfo->gen < 6;
nir_options->lower_flrp32 = devinfo->gen < 6 || devinfo->gen >= 11;
nir_options->lower_fpow = devinfo->gen >= 12;
nir_options->lower_ffma16 = devinfo->ver < 6;
nir_options->lower_ffma32 = devinfo->ver < 6;
nir_options->lower_ffma64 = devinfo->ver < 6;
nir_options->lower_flrp32 = devinfo->ver < 6 || devinfo->ver >= 11;
nir_options->lower_fpow = devinfo->ver >= 12;
nir_options->lower_rotate = devinfo->gen < 11;
nir_options->lower_bitfield_reverse = devinfo->gen < 7;
nir_options->lower_rotate = devinfo->ver < 11;
nir_options->lower_bitfield_reverse = devinfo->ver < 7;
nir_options->lower_int64_options = int64_options;
nir_options->lower_doubles_options = fp64_options;
/* Starting with Gen11, we lower away 8-bit arithmetic */
nir_options->support_8bit_alu = devinfo->gen < 11;
nir_options->support_8bit_alu = devinfo->ver < 11;
nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
@ -213,7 +213,7 @@ brw_get_compiler_config_value(const struct brw_compiler *compiler)
{
uint64_t config = 0;
insert_u64_bit(&config, compiler->precise_trig);
if (compiler->devinfo->gen >= 8 && compiler->devinfo->gen < 10) {
if (compiler->devinfo->ver >= 8 && compiler->devinfo->ver < 10) {
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);

2
src/intel/compiler/brw_compiler.h
View file

@ -1729,7 +1729,7 @@ brw_stage_has_packed_dispatch(ASSERTED const struct gen_device_info *devinfo,
* to do a full test run with brw_fs_test_dispatch_packing() hooked up to
* the NIR front-end before changing this assertion.
*/
assert(devinfo->gen <= 12);
assert(devinfo->ver <= 12);
switch (stage) {
case MESA_SHADER_FRAGMENT: {

108
src/intel/compiler/brw_disasm.c
View file

@ -35,7 +35,7 @@
bool
brw_has_jip(const struct gen_device_info *devinfo, enum opcode opcode)
{
if (devinfo->gen < 6)
if (devinfo->ver < 6)
return false;
return opcode == BRW_OPCODE_IF ||
@ -50,11 +50,11 @@ brw_has_jip(const struct gen_device_info *devinfo, enum opcode opcode)
bool
brw_has_uip(const struct gen_device_info *devinfo, enum opcode opcode)
{
if (devinfo->gen < 6)
if (devinfo->ver < 6)
return false;
return (devinfo->gen >= 7 && opcode == BRW_OPCODE_IF) ||
(devinfo->gen >= 8 && opcode == BRW_OPCODE_ELSE) ||
return (devinfo->ver >= 7 && opcode == BRW_OPCODE_IF) ||
(devinfo->ver >= 8 && opcode == BRW_OPCODE_ELSE) ||
opcode == BRW_OPCODE_BREAK ||
opcode == BRW_OPCODE_CONTINUE ||
opcode == BRW_OPCODE_HALT;
@ -63,7 +63,7 @@ brw_has_uip(const struct gen_device_info *devinfo, enum opcode opcode)
static bool
has_branch_ctrl(const struct gen_device_info *devinfo, enum opcode opcode)
{
if (devinfo->gen < 8)
if (devinfo->ver < 8)
return false;
return opcode == BRW_OPCODE_IF ||
@ -92,7 +92,7 @@ is_send(unsigned opcode)
static bool
is_split_send(UNUSED const struct gen_device_info *devinfo, unsigned opcode)
{
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
return is_send(opcode);
else
return opcode == BRW_OPCODE_SENDS ||
@ -393,9 +393,9 @@ static const char *const dp_rc_msg_type_gen9[16] = {
static const char *const *
dp_rc_msg_type(const struct gen_device_info *devinfo)
{
return (devinfo->gen >= 9 ? dp_rc_msg_type_gen9 :
devinfo->gen >= 7 ? dp_rc_msg_type_gen7 :
devinfo->gen >= 6 ? dp_rc_msg_type_gen6 :
return (devinfo->ver >= 9 ? dp_rc_msg_type_gen9 :
devinfo->ver >= 7 ? dp_rc_msg_type_gen7 :
devinfo->ver >= 6 ? dp_rc_msg_type_gen6 :
dp_write_port_msg_type);
}
@ -761,7 +761,7 @@ dest(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
/* These are fixed for split sends */
type = BRW_REGISTER_TYPE_UD;
elem_size = 4;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst),
brw_inst_dst_da_reg_nr(devinfo, inst));
string(file, brw_reg_type_to_letters(type));
@ -839,12 +839,12 @@ dest_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins
unsigned subreg_nr;
enum brw_reg_type type;
if (devinfo->gen < 10 && is_align1)
if (devinfo->ver < 10 && is_align1)
return 0;
if (devinfo->gen == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst))
if (devinfo->ver == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst))
reg_file = BRW_MESSAGE_REGISTER_FILE;
else if (devinfo->gen >= 12)
else if (devinfo->ver >= 12)
reg_file = brw_inst_3src_a1_dst_reg_file(devinfo, inst);
else if (is_align1 && brw_inst_3src_a1_dst_reg_file(devinfo, inst))
reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
@ -904,7 +904,7 @@ src_da1(FILE *file,
{
int err = 0;
if (devinfo->gen >= 8 && is_logic_instruction(opcode))
if (devinfo->ver >= 8 && is_logic_instruction(opcode))
err |= control(file, "bitnot", m_bitnot, _negate, NULL);
else
err |= control(file, "negate", m_negate, _negate, NULL);
@ -936,7 +936,7 @@ src_ia1(FILE *file,
{
int err = 0;
if (devinfo->gen >= 8 && is_logic_instruction(opcode))
if (devinfo->ver >= 8 && is_logic_instruction(opcode))
err |= control(file, "bitnot", m_bitnot, _negate, NULL);
else
err |= control(file, "negate", m_negate, _negate, NULL);
@ -991,7 +991,7 @@ src_da16(FILE *file,
{
int err = 0;
if (devinfo->gen >= 8 && is_logic_instruction(opcode))
if (devinfo->ver >= 8 && is_logic_instruction(opcode))
err |= control(file, "bitnot", m_bitnot, _negate, NULL);
else
err |= control(file, "negate", m_negate, _negate, NULL);
@ -1023,7 +1023,7 @@ vstride_from_align1_3src_vstride(const struct gen_device_info *devinfo,
switch (vstride) {
case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2:
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
return BRW_VERTICAL_STRIDE_1;
else
return BRW_VERTICAL_STRIDE_2;
@ -1114,11 +1114,11 @@ src0_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins
bool is_scalar_region;
bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
if (devinfo->gen < 10 && is_align1)
if (devinfo->ver < 10 && is_align1)
return 0;
if (is_align1) {
if (devinfo->gen >= 12 && !brw_inst_3src_a1_src0_is_imm(devinfo, inst)) {
if (devinfo->ver >= 12 && !brw_inst_3src_a1_src0_is_imm(devinfo, inst)) {
_file = brw_inst_3src_a1_src0_reg_file(devinfo, inst);
} else if (brw_inst_3src_a1_src0_reg_file(devinfo, inst) ==
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
@ -1200,11 +1200,11 @@ src1_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins
bool is_scalar_region;
bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
if (devinfo->gen < 10 && is_align1)
if (devinfo->ver < 10 && is_align1)
return 0;
if (is_align1) {
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
_file = brw_inst_3src_a1_src1_reg_file(devinfo, inst);
} else if (brw_inst_3src_a1_src1_reg_file(devinfo, inst) ==
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
@ -1273,11 +1273,11 @@ src2_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins
bool is_scalar_region;
bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
if (devinfo->gen < 10 && is_align1)
if (devinfo->ver < 10 && is_align1)
return 0;
if (is_align1) {
if (devinfo->gen >= 12 && !brw_inst_3src_a1_src2_is_imm(devinfo, inst)) {
if (devinfo->ver >= 12 && !brw_inst_3src_a1_src2_is_imm(devinfo, inst)) {
_file = brw_inst_3src_a1_src2_reg_file(devinfo, inst);
} else if (brw_inst_3src_a1_src2_reg_file(devinfo, inst) ==
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
@ -1470,7 +1470,7 @@ static int
src0(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
{
if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
return src_sends_da(file,
devinfo,
BRW_REGISTER_TYPE_UD,
@ -1610,7 +1610,7 @@ qtr_ctrl(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst
{
int qtr_ctl = brw_inst_qtr_control(devinfo, inst);
int exec_size = 1 << brw_inst_exec_size(devinfo, inst);
const unsigned nib_ctl = devinfo->gen < 7 ? 0 :
const unsigned nib_ctl = devinfo->ver < 7 ? 0 :
brw_inst_nib_control(devinfo, inst);
if (exec_size < 8 || nib_ctl) {
@ -1696,7 +1696,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
err |= control(file, "predicate inverse", pred_inv,
brw_inst_pred_inv(devinfo, inst), NULL);
format(file, "f%"PRIu64".%"PRIu64,
devinfo->gen >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0,
devinfo->ver >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0,
brw_inst_flag_subreg_nr(devinfo, inst));
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
err |= control(file, "predicate control align1", pred_ctrl_align1,
@ -1736,12 +1736,12 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
* control flow doesn't update flags.
*/
if (brw_inst_cond_modifier(devinfo, inst) &&
(devinfo->gen < 6 || (opcode != BRW_OPCODE_SEL &&
(devinfo->ver < 6 || (opcode != BRW_OPCODE_SEL &&
opcode != BRW_OPCODE_CSEL &&
opcode != BRW_OPCODE_IF &&
opcode != BRW_OPCODE_WHILE))) {
format(file, ".f%"PRIu64".%"PRIu64,
devinfo->gen >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0,
devinfo->ver >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0,
brw_inst_flag_subreg_nr(devinfo, inst));
}
}
@ -1753,7 +1753,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
string(file, ")");
}
if (opcode == BRW_OPCODE_SEND && devinfo->gen < 6)
if (opcode == BRW_OPCODE_SEND && devinfo->ver < 6)
format(file, " %"PRIu64, brw_inst_base_mrf(devinfo, inst));
if (brw_has_uip(devinfo, opcode)) {
@ -1767,7 +1767,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
write_label(file, devinfo, root_label, offset, brw_inst_uip(devinfo, inst));
} else if (brw_has_jip(devinfo, opcode)) {
int jip;
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
jip = brw_inst_jip(devinfo, inst);
} else {
jip = brw_inst_gen6_jump_count(devinfo, inst);
@ -1776,20 +1776,20 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
pad(file, 16);
string(file, "JIP: ");
write_label(file, devinfo, root_label, offset, jip);
} else if (devinfo->gen < 6 && (opcode == BRW_OPCODE_BREAK ||
} else if (devinfo->ver < 6 && (opcode == BRW_OPCODE_BREAK ||
opcode == BRW_OPCODE_CONTINUE ||
opcode == BRW_OPCODE_ELSE)) {
pad(file, 16);
format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst));
pad(file, 32);
format(file, "Pop: %"PRIu64, brw_inst_gen4_pop_count(devinfo, inst));
} else if (devinfo->gen < 6 && (opcode == BRW_OPCODE_IF ||
} else if (devinfo->ver < 6 && (opcode == BRW_OPCODE_IF ||
opcode == BRW_OPCODE_IFF ||
opcode == BRW_OPCODE_HALT ||
opcode == BRW_OPCODE_WHILE)) {
pad(file, 16);
format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst));
} else if (devinfo->gen < 6 && opcode == BRW_OPCODE_ENDIF) {
} else if (devinfo->ver < 6 && opcode == BRW_OPCODE_ENDIF) {
pad(file, 16);
format(file, "Pop: %"PRIu64, brw_inst_gen4_pop_count(devinfo, inst));
} else if (opcode == BRW_OPCODE_JMPI) {
@ -1871,7 +1871,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
space = 0;
fprintf(file, " ");
err |= control(file, "SFID", devinfo->gen >= 6 ? gen6_sfid : gen4_sfid,
err |= control(file, "SFID", devinfo->ver >= 6 ? gen6_sfid : gen4_sfid,
sfid, &space);
string(file, " MsgDesc:");
@ -1893,7 +1893,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
brw_inst_math_msg_precision(devinfo, inst), &space);
break;
case BRW_SFID_SAMPLER:
if (devinfo->gen >= 5) {
if (devinfo->ver >= 5) {
err |= control(file, "sampler message", gen5_sampler_msg_type,
brw_sampler_desc_msg_type(devinfo, imm_desc),
&space);
@ -1920,15 +1920,15 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
case GEN6_SFID_DATAPORT_SAMPLER_CACHE:
case GEN6_SFID_DATAPORT_CONSTANT_CACHE:
/* aka BRW_SFID_DATAPORT_READ on Gen4-5 */
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
format(file, " (%u, %u, %u, %u)",
brw_dp_desc_binding_table_index(devinfo, imm_desc),
brw_dp_desc_msg_control(devinfo, imm_desc),
brw_dp_desc_msg_type(devinfo, imm_desc),
devinfo->gen >= 7 ? 0u :
devinfo->ver >= 7 ? 0u :
brw_dp_write_desc_write_commit(devinfo, imm_desc));
} else {
bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
bool is_965 = devinfo->ver == 4 && !devinfo->is_g4x;
err |= control(file, "DP read message type",
is_965 ? gen4_dp_read_port_msg_type :
g45_dp_read_port_msg_type,
@ -1951,17 +1951,17 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
dp_rc_msg_type(devinfo), msg_type, &space);
bool is_rt_write = msg_type ==
(devinfo->gen >= 6 ? GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
(devinfo->ver >= 6 ? GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
: BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE);
if (is_rt_write) {
err |= control(file, "RT message type", m_rt_write_subtype,
brw_inst_rt_message_type(devinfo, inst), &space);
if (devinfo->gen >= 6 && brw_inst_rt_slot_group(devinfo, inst))
if (devinfo->ver >= 6 && brw_inst_rt_slot_group(devinfo, inst))
string(file, " Hi");
if (brw_dp_write_desc_last_render_target(devinfo, imm_desc))
string(file, " LastRT");
if (devinfo->gen < 7 &&
if (devinfo->ver < 7 &&
brw_dp_write_desc_write_commit(devinfo, imm_desc))
string(file, " WriteCommit");
} else {
@ -1982,11 +1982,11 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
space = 1;
err |= control(file, "urb opcode",
devinfo->gen >= 7 ? gen7_urb_opcode
devinfo->ver >= 7 ? gen7_urb_opcode
: gen5_urb_opcode,
opcode, &space);
if (devinfo->gen >= 7 &&
if (devinfo->ver >= 7 &&
brw_inst_urb_per_slot_offset(devinfo, inst)) {
string(file, " per-slot");
}
@ -2001,13 +2001,13 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
&space);
}
if (devinfo->gen < 7) {
if (devinfo->ver < 7) {
err |= control(file, "urb allocate", urb_allocate,
brw_inst_urb_allocate(devinfo, inst), &space);
err |= control(file, "urb used", urb_used,
brw_inst_urb_used(devinfo, inst), &space);
}
if (devinfo->gen < 8) {
if (devinfo->ver < 8) {
err |= control(file, "urb complete", urb_complete,
brw_inst_urb_complete(devinfo, inst), &space);
}
@ -2022,7 +2022,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
break;
case GEN7_SFID_DATAPORT_DATA_CACHE:
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
format(file, " (");
err |= control(file, "DP DC0 message type",
@ -2049,7 +2049,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
break;
case HSW_SFID_DATAPORT_DATA_CACHE_1: {
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
format(file, " (");
unsigned msg_ctrl = brw_dp_desc_msg_control(devinfo, imm_desc);
@ -2103,7 +2103,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
}
case GEN7_SFID_PIXEL_INTERPOLATOR:
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
format(file, " (%s, %s, 0x%02"PRIx64")",
brw_inst_pi_nopersp(devinfo, inst) ? "linear" : "persp",
pixel_interpolator_msg_types[brw_inst_pi_message_type(devinfo, inst)],
@ -2148,7 +2148,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
space = 1;
err |= control(file, "access mode", access_mode,
brw_inst_access_mode(devinfo, inst), &space);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
err |= control(file, "write enable control", wectrl,
brw_inst_mask_control(devinfo, inst), &space);
} else {
@ -2156,13 +2156,13 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
brw_inst_mask_control(devinfo, inst), &space);
}
if (devinfo->gen < 12) {
if (devinfo->ver < 12) {
err |= control(file, "dependency control", dep_ctrl,
((brw_inst_no_dd_check(devinfo, inst) << 1) |
brw_inst_no_dd_clear(devinfo, inst)), &space);
}
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
err |= qtr_ctrl(file, devinfo, inst);
else {
if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_COMPRESSED &&
@ -2176,18 +2176,18 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
}
}
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
err |= swsb(file, devinfo, inst);
err |= control(file, "compaction", cmpt_ctrl, is_compacted, &space);
err |= control(file, "thread control", thread_ctrl,
(devinfo->gen >= 12 ? brw_inst_atomic_control(devinfo, inst) :
(devinfo->ver >= 12 ? brw_inst_atomic_control(devinfo, inst) :
brw_inst_thread_control(devinfo, inst)),
&space);
if (has_branch_ctrl(devinfo, opcode)) {
err |= control(file, "branch ctrl", branch_ctrl,
brw_inst_branch_control(devinfo, inst), &space);
} else if (devinfo->gen >= 6) {
} else if (devinfo->ver >= 6) {
err |= control(file, "acc write control", accwr,
brw_inst_acc_wr_control(devinfo, inst), &space);
}

2
src/intel/compiler/brw_disasm_info.c
View file

@ -158,7 +158,7 @@ disasm_annotate(struct disasm_info *disasm,
* There's also only complication from emitting an annotation without
* a corresponding hardware instruction to disassemble.
*/
if (devinfo->gen >= 6 && inst->opcode == BRW_OPCODE_DO) {
if (devinfo->ver >= 6 && inst->opcode == BRW_OPCODE_DO) {
disasm->use_tail = true;
}

10
src/intel/compiler/brw_eu.cpp
View file

@ -205,7 +205,7 @@ brw_set_default_compression_control(struct brw_codegen *p,
unreachable("not reached");
}
if (p->devinfo->gen <= 6) {
if (p->devinfo->ver <= 6) {
p->current->compressed =
(compression_control == BRW_COMPRESSION_COMPRESSED);
}
@ -219,7 +219,7 @@ void
brw_inst_set_compression(const struct gen_device_info *devinfo,
brw_inst *inst, bool on)
{
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
/* No-op, the EU will figure out for us whether the instruction needs to
* be compressed.
*/
@ -251,12 +251,12 @@ void
brw_inst_set_group(const struct gen_device_info *devinfo,
brw_inst *inst, unsigned group)
{
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
assert(group % 4 == 0 && group < 32);
brw_inst_set_qtr_control(devinfo, inst, group / 8);
brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
assert(group % 8 == 0 && group < 32);
brw_inst_set_qtr_control(devinfo, inst, group / 8);
@ -492,7 +492,7 @@ brw_label_assembly(const struct gen_device_info *devinfo,
offset + brw_inst_jip(devinfo, inst) * to_bytes_scale, mem_ctx);
} else if (brw_has_jip(devinfo, brw_inst_opcode(devinfo, inst))) {
int jip;
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
jip = brw_inst_jip(devinfo, inst);
} else {
jip = brw_inst_gen6_jump_count(devinfo, inst);

114
src/intel/compiler/brw_eu.h
View file

@ -288,7 +288,7 @@ brw_message_desc(const struct gen_device_info *devinfo,
unsigned response_length,
bool header_present)
{
if (devinfo->gen >= 5) {
if (devinfo->ver >= 5) {
return (SET_BITS(msg_length, 28, 25) |
SET_BITS(response_length, 24, 20) |
SET_BITS(header_present, 19, 19));
@ -301,7 +301,7 @@ brw_message_desc(const struct gen_device_info *devinfo,
static inline unsigned
brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
{
if (devinfo->gen >= 5)
if (devinfo->ver >= 5)
return GET_BITS(desc, 28, 25);
else
return GET_BITS(desc, 23, 20);
@ -310,7 +310,7 @@ brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
static inline unsigned
brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
{
if (devinfo->gen >= 5)
if (devinfo->ver >= 5)
return GET_BITS(desc, 24, 20);
else
return GET_BITS(desc, 19, 16);
@ -320,7 +320,7 @@ static inline bool
brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
uint32_t desc)
{
assert(devinfo->gen >= 5);
assert(devinfo->ver >= 5);
return GET_BITS(desc, 19, 19);
}
@ -345,12 +345,12 @@ brw_urb_desc(const struct gen_device_info *devinfo,
bool channel_mask_present,
unsigned global_offset)
{
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
return (SET_BITS(per_slot_offset_present, 17, 17) |
SET_BITS(channel_mask_present, 15, 15) |
SET_BITS(global_offset, 14, 4) |
SET_BITS(msg_type, 3, 0));
} else if (devinfo->gen >= 7) {
} else if (devinfo->ver >= 7) {
assert(!channel_mask_present);
return (SET_BITS(per_slot_offset_present, 16, 16) |
SET_BITS(global_offset, 13, 3) |
@ -364,7 +364,7 @@ static inline uint32_t
brw_urb_desc_msg_type(ASSERTED const struct gen_device_info *devinfo,
uint32_t desc)
{
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
return GET_BITS(desc, 3, 0);
}
@ -382,10 +382,10 @@ brw_sampler_desc(const struct gen_device_info *devinfo,
{
const unsigned desc = (SET_BITS(binding_table_index, 7, 0) |
SET_BITS(sampler, 11, 8));
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
return (desc | SET_BITS(msg_type, 16, 12) |
SET_BITS(simd_mode, 18, 17));
else if (devinfo->gen >= 5)
else if (devinfo->ver >= 5)
return (desc | SET_BITS(msg_type, 15, 12) |
SET_BITS(simd_mode, 17, 16));
else if (devinfo->is_g4x)
@ -411,9 +411,9 @@ brw_sampler_desc_sampler(UNUSED const struct gen_device_info *devinfo, uint32_t
static inline unsigned
brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
{
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
return GET_BITS(desc, 16, 12);
else if (devinfo->gen >= 5 || devinfo->is_g4x)
else if (devinfo->ver >= 5 || devinfo->is_g4x)
return GET_BITS(desc, 15, 12);
else
return GET_BITS(desc, 15, 14);
@ -422,8 +422,8 @@ brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
static inline unsigned
brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
{
assert(devinfo->gen >= 5);
if (devinfo->gen >= 7)
assert(devinfo->ver >= 5);
if (devinfo->ver >= 7)
return GET_BITS(desc, 18, 17);
else
return GET_BITS(desc, 17, 16);
@ -433,7 +433,7 @@ static inline unsigned
brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
uint32_t desc)
{
assert(devinfo->gen == 4 && !devinfo->is_g4x);
assert(devinfo->ver == 4 && !devinfo->is_g4x);
return GET_BITS(desc, 13, 12);
}
@ -449,12 +449,12 @@ brw_dp_desc(const struct gen_device_info *devinfo,
/* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
* helpers instead.
*/
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
const unsigned desc = SET_BITS(binding_table_index, 7, 0);
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
return (desc | SET_BITS(msg_control, 13, 8) |
SET_BITS(msg_type, 18, 14));
} else if (devinfo->gen >= 7) {
} else if (devinfo->ver >= 7) {
return (desc | SET_BITS(msg_control, 13, 8) |
SET_BITS(msg_type, 17, 14));
} else {
@ -473,10 +473,10 @@ brw_dp_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
static inline unsigned
brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
{
assert(devinfo->gen >= 6);
if (devinfo->gen >= 8)
assert(devinfo->ver >= 6);
if (devinfo->ver >= 8)
return GET_BITS(desc, 18, 14);
else if (devinfo->gen >= 7)
else if (devinfo->ver >= 7)
return GET_BITS(desc, 17, 14);
else
return GET_BITS(desc, 16, 13);
@ -485,8 +485,8 @@ brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
static inline unsigned
brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
{
assert(devinfo->gen >= 6);
if (devinfo->gen >= 7)
assert(devinfo->ver >= 6);
if (devinfo->ver >= 7)
return GET_BITS(desc, 13, 8);
else
return GET_BITS(desc, 12, 8);
@ -503,9 +503,9 @@ brw_dp_read_desc(const struct gen_device_info *devinfo,
unsigned msg_type,
unsigned target_cache)
{
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
else if (devinfo->gen >= 5 || devinfo->is_g4x)
else if (devinfo->ver >= 5 || devinfo->is_g4x)
return (SET_BITS(binding_table_index, 7, 0) |
SET_BITS(msg_control, 10, 8) |
SET_BITS(msg_type, 13, 11) |
@ -520,9 +520,9 @@ brw_dp_read_desc(const struct gen_device_info *devinfo,
static inline unsigned
brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
{
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
return brw_dp_desc_msg_type(devinfo, desc);
else if (devinfo->gen >= 5 || devinfo->is_g4x)
else if (devinfo->ver >= 5 || devinfo->is_g4x)
return GET_BITS(desc, 13, 11);
else
return GET_BITS(desc, 13, 12);
@ -532,9 +532,9 @@ static inline unsigned
brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
uint32_t desc)
{
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
return brw_dp_desc_msg_control(devinfo, desc);
else if (devinfo->gen >= 5 || devinfo->is_g4x)
else if (devinfo->ver >= 5 || devinfo->is_g4x)
return GET_BITS(desc, 10, 8);
else
return GET_BITS(desc, 11, 8);
@ -552,8 +552,8 @@ brw_dp_write_desc(const struct gen_device_info *devinfo,
unsigned last_render_target,
unsigned send_commit_msg)
{
assert(devinfo->gen <= 6 || !send_commit_msg);
if (devinfo->gen >= 6)
assert(devinfo->ver <= 6 || !send_commit_msg);
if (devinfo->ver >= 6)
return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) |
SET_BITS(last_render_target, 12, 12) |
SET_BITS(send_commit_msg, 17, 17);
@ -569,7 +569,7 @@ static inline unsigned
brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
uint32_t desc)
{
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
return brw_dp_desc_msg_type(devinfo, desc);
else
return GET_BITS(desc, 14, 12);
@ -579,7 +579,7 @@ static inline unsigned
brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
uint32_t desc)
{
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
return brw_dp_desc_msg_control(devinfo, desc);
else
return GET_BITS(desc, 11, 8);
@ -589,7 +589,7 @@ static inline bool
brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
uint32_t desc)
{
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
return GET_BITS(desc, 12, 12);
else
return GET_BITS(desc, 11, 11);
@ -599,8 +599,8 @@ static inline bool
brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
uint32_t desc)
{
assert(devinfo->gen <= 6);
if (devinfo->gen >= 6)
assert(devinfo->ver <= 6);
if (devinfo->ver >= 6)
return GET_BITS(desc, 17, 17);
else
return GET_BITS(desc, 15, 15);
@ -615,7 +615,7 @@ brw_dp_surface_desc(const struct gen_device_info *devinfo,
unsigned msg_type,
unsigned msg_control)
{
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
/* We'll OR in the binding table index later */
return brw_dp_desc(devinfo, 0, msg_type, msg_control);
}
@ -629,7 +629,7 @@ brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
assert(exec_size <= 8 || exec_size == 16);
unsigned msg_type;
if (devinfo->gen >= 8 || devinfo->is_haswell) {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (exec_size > 0) {
msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
} else {
@ -654,7 +654,7 @@ brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
bool response_expected)
{
assert(exec_size <= 8 || exec_size == 16);
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
assert(exec_size > 0);
const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
@ -684,14 +684,14 @@ brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
unsigned msg_type;
if (write) {
if (devinfo->gen >= 8 || devinfo->is_haswell) {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
} else {
msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
}
} else {
/* Read */
if (devinfo->gen >= 8 || devinfo->is_haswell) {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
} else {
msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
@ -699,7 +699,7 @@ brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
}
/* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
if (write && devinfo->gen == 7 && !devinfo->is_haswell && exec_size == 0)
if (write && devinfo->ver == 7 && !devinfo->is_haswell && exec_size == 0)
exec_size = 8;
/* See also MDC_SM3 in the SKL PRM Vol 2d. */
@ -736,7 +736,7 @@ brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
{
assert(exec_size <= 8 || exec_size == 16);
assert(devinfo->gen > 7 || devinfo->is_haswell);
assert(devinfo->ver > 7 || devinfo->is_haswell);
const unsigned msg_type =
write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE :
HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ;
@ -758,15 +758,15 @@ brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo,
unsigned msg_type;
if (write) {
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
} else {
msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
}
} else {
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
msg_type = GEN7_DATAPORT_DC_DWORD_SCATTERED_READ;
} else if (devinfo->gen > 4 || devinfo->is_g4x) {
} else if (devinfo->ver > 4 || devinfo->is_g4x) {
msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
} else {
msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
@ -807,7 +807,7 @@ brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
bool write)
{
assert(exec_size <= 8 || exec_size == 16);
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
unsigned msg_type =
write ? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
@ -870,7 +870,7 @@ brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
bool write)
{
assert(exec_size <= 8 || exec_size == 16);
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
unsigned msg_type =
write ? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
@ -893,9 +893,9 @@ brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
bool response_expected)
{
assert(exec_size == 8);
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
assert(bit_size == 16 || bit_size == 32 || bit_size == 64);
assert(devinfo->gen >= 12 || bit_size >= 32);
assert(devinfo->ver >= 12 || bit_size >= 32);
const unsigned msg_type = bit_size == 16 ?
GEN12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP :
@ -918,9 +918,9 @@ brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
bool response_expected)
{
assert(exec_size == 8);
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
assert(bit_size == 16 || bit_size == 32);
assert(devinfo->gen >= 12 || bit_size == 32);
assert(devinfo->ver >= 12 || bit_size == 32);
assert(exec_size > 0);
const unsigned msg_type = bit_size == 32 ?
@ -946,7 +946,7 @@ brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
assert(exec_group % 8 == 0);
unsigned msg_type;
if (devinfo->gen >= 8 || devinfo->is_haswell) {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (exec_size == 0) {
msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
} else {
@ -983,13 +983,13 @@ brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
unsigned msg_type;
if (write) {
if (devinfo->gen >= 8 || devinfo->is_haswell) {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
} else {
msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE;
}
} else {
if (devinfo->gen >= 8 || devinfo->is_haswell) {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
} else {
msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
@ -998,7 +998,7 @@ brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
/* See also MDC_SG3 in the SKL PRM Vol 2d. */
unsigned msg_control;
if (devinfo->gen >= 8 || devinfo->is_haswell) {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
/* See also MDC_SG3 in the SKL PRM Vol 2d. */
const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */
1 + ((exec_group / 8) % 2);
@ -1232,13 +1232,13 @@ static inline unsigned
brw_jump_scale(const struct gen_device_info *devinfo)
{
/* Broadwell measures jump targets in bytes. */
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return 16;
/* Ironlake and later measure jump targets in 64-bit data chunks (in order
* (to support compaction), so each 128-bit instruction requires 2 chunks.
*/
if (devinfo->gen >= 5)
if (devinfo->ver >= 5)
return 2;
/* Gen4 simply uses the number of 128-bit instructions. */

130
src/intel/compiler/brw_eu_compact.c
View file

@ -972,7 +972,7 @@ set_control_index(const struct compaction_state *c,
const struct gen_device_info *devinfo = c->devinfo;
uint32_t uncompacted; /* 17b/G45; 19b/IVB+; 21b/TGL+ */
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
uncompacted = (brw_inst_bits(src, 95, 92) << 17) | /* 4b */
(brw_inst_bits(src, 34, 34) << 16) | /* 1b */
(brw_inst_bits(src, 33, 33) << 15) | /* 1b */
@ -983,7 +983,7 @@ set_control_index(const struct compaction_state *c,
(brw_inst_bits(src, 23, 22) << 6) | /* 2b */
(brw_inst_bits(src, 21, 19) << 3) | /* 3b */
(brw_inst_bits(src, 18, 16)); /* 3b */
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
uncompacted = (brw_inst_bits(src, 33, 31) << 16) | /* 3b */
(brw_inst_bits(src, 23, 12) << 4) | /* 12b */
(brw_inst_bits(src, 10, 9) << 2) | /* 2b */
@ -996,7 +996,7 @@ set_control_index(const struct compaction_state *c,
/* On gen7, the flag register and subregister numbers are integrated into
* the control index.
*/
if (devinfo->gen == 7)
if (devinfo->ver == 7)
uncompacted |= brw_inst_bits(src, 90, 89) << 17; /* 2b */
}
@ -1017,7 +1017,7 @@ set_datatype_index(const struct compaction_state *c, brw_compact_inst *dst,
const struct gen_device_info *devinfo = c->devinfo;
uint32_t uncompacted; /* 18b/G45+; 21b/BDW+; 20b/TGL+ */
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
uncompacted = (brw_inst_bits(src, 91, 88) << 15) | /* 4b */
(brw_inst_bits(src, 66, 66) << 14) | /* 1b */
(brw_inst_bits(src, 50, 50) << 13) | /* 1b */
@ -1034,7 +1034,7 @@ set_datatype_index(const struct compaction_state *c, brw_compact_inst *dst,
if (!is_immediate) {
uncompacted |= brw_inst_bits(src, 98, 98) << 19; /* 1b */
}
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
uncompacted = (brw_inst_bits(src, 63, 61) << 18) | /* 3b */
(brw_inst_bits(src, 94, 89) << 12) | /* 6b */
(brw_inst_bits(src, 46, 35)); /* 12b */
@ -1060,7 +1060,7 @@ set_subreg_index(const struct compaction_state *c, brw_compact_inst *dst,
const struct gen_device_info *devinfo = c->devinfo;
uint16_t uncompacted; /* 15b */
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
uncompacted = (brw_inst_bits(src, 55, 51) << 0) | /* 5b */
(brw_inst_bits(src, 71, 67) << 5); /* 5b */
@ -1092,7 +1092,7 @@ set_src0_index(const struct compaction_state *c, brw_compact_inst *dst,
uint16_t uncompacted; /* 12b */
int table_len;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
table_len = ARRAY_SIZE(gen12_src0_index_table);
uncompacted = (brw_inst_bits(src, 87, 84) << 8) | /* 4b */
(brw_inst_bits(src, 83, 81) << 5) | /* 3b */
@ -1120,7 +1120,7 @@ set_src1_index(const struct compaction_state *c, brw_compact_inst *dst,
{
const struct gen_device_info *devinfo = c->devinfo;
if (is_immediate) {
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
/* src1 index takes the low 4 bits of the 12-bit compacted value */
brw_compact_inst_set_src1_index(devinfo, dst, imm & 0xf);
} else {
@ -1132,7 +1132,7 @@ set_src1_index(const struct compaction_state *c, brw_compact_inst *dst,
uint16_t uncompacted; /* 12b */
int table_len;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
table_len = ARRAY_SIZE(gen12_src0_index_table);
uncompacted = (brw_inst_bits(src, 121, 120) << 10) | /* 2b */
(brw_inst_bits(src, 119, 116) << 6) | /* 4b */
@ -1159,9 +1159,9 @@ static bool
set_3src_control_index(const struct gen_device_info *devinfo,
brw_compact_inst *dst, const brw_inst *src)
{
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
uint64_t uncompacted = /* 36b/TGL+ */
(brw_inst_bits(src, 95, 92) << 32) | /* 4b */
(brw_inst_bits(src, 90, 88) << 29) | /* 3b */
@ -1193,7 +1193,7 @@ set_3src_control_index(const struct gen_device_info *devinfo,
(brw_inst_bits(src, 34, 32) << 21) | /* 3b */
(brw_inst_bits(src, 28, 8)); /* 21b */
if (devinfo->gen >= 9 || devinfo->is_cherryview) {
if (devinfo->ver >= 9 || devinfo->is_cherryview) {
uncompacted |=
brw_inst_bits(src, 36, 35) << 24; /* 2b */
}
@ -1213,9 +1213,9 @@ static bool
set_3src_source_index(const struct gen_device_info *devinfo,
brw_compact_inst *dst, const brw_inst *src)
{
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
uint32_t uncompacted = /* 21b/TGL+ */
(brw_inst_bits(src, 114, 114) << 20) | /* 1b */
(brw_inst_bits(src, 113, 112) << 18) | /* 2b */
@ -1247,7 +1247,7 @@ set_3src_source_index(const struct gen_device_info *devinfo,
(brw_inst_bits(src, 72, 65) << 19) | /* 8b */
(brw_inst_bits(src, 55, 37)); /* 19b */
if (devinfo->gen >= 9 || devinfo->is_cherryview) {
if (devinfo->ver >= 9 || devinfo->is_cherryview) {
uncompacted |=
(brw_inst_bits(src, 126, 125) << 47) | /* 2b */
(brw_inst_bits(src, 105, 104) << 45) | /* 2b */
@ -1273,7 +1273,7 @@ static bool
set_3src_subreg_index(const struct gen_device_info *devinfo,
brw_compact_inst *dst, const brw_inst *src)
{
assert(devinfo->gen >= 12);
assert(devinfo->ver >= 12);
uint32_t uncompacted = /* 20b/TGL+ */
(brw_inst_bits(src, 119, 115) << 15) | /* 5b */
@ -1309,17 +1309,17 @@ has_unmapped_bits(const struct gen_device_info *devinfo, const brw_inst *src)
* - Imm64[27:31] (bits 91-95 on Gen7, bit 95 on Gen8)
* - UIP[31] (bit 95 on Gen8)
*/
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
assert(!brw_inst_bits(src, 7, 7));
return false;
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
assert(!brw_inst_bits(src, 7, 7));
return brw_inst_bits(src, 95, 95) ||
brw_inst_bits(src, 47, 47) ||
brw_inst_bits(src, 11, 11);
} else {
assert(!brw_inst_bits(src, 7, 7) &&
!(devinfo->gen < 7 && brw_inst_bits(src, 90, 90)));
!(devinfo->ver < 7 && brw_inst_bits(src, 90, 90)));
return brw_inst_bits(src, 95, 91) ||
brw_inst_bits(src, 47, 47);
}
@ -1333,13 +1333,13 @@ has_3src_unmapped_bits(const struct gen_device_info *devinfo,
* fields of the compacted instruction. All of them seem to be reserved
* bits currently.
*/
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
assert(!brw_inst_bits(src, 7, 7));
} else if (devinfo->gen >= 9 || devinfo->is_cherryview) {
} else if (devinfo->ver >= 9 || devinfo->is_cherryview) {
assert(!brw_inst_bits(src, 127, 127) &&
!brw_inst_bits(src, 7, 7));
} else {
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
assert(!brw_inst_bits(src, 127, 126) &&
!brw_inst_bits(src, 105, 105) &&
!brw_inst_bits(src, 84, 84) &&
@ -1357,7 +1357,7 @@ static bool
brw_try_compact_3src_instruction(const struct gen_device_info *devinfo,
brw_compact_inst *dst, const brw_inst *src)
{
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
if (has_3src_unmapped_bits(devinfo, src))
return false;
@ -1375,7 +1375,7 @@ brw_try_compact_3src_instruction(const struct gen_device_info *devinfo,
if (!set_3src_source_index(devinfo, dst, src))
return false;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
if (!set_3src_subreg_index(devinfo, dst, src))
return false;
@ -1423,7 +1423,7 @@ static int
compact_immediate(const struct gen_device_info *devinfo,
enum brw_reg_type type, unsigned imm)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
/* 16-bit immediates need to be replicated through the 32-bit immediate
* field
*/
@ -1494,7 +1494,7 @@ static int
uncompact_immediate(const struct gen_device_info *devinfo,
enum brw_reg_type type, unsigned compact_imm)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
switch (type) {
case BRW_REGISTER_TYPE_F:
return compact_imm << 20;
@ -1582,10 +1582,10 @@ precompact(const struct gen_device_info *devinfo, brw_inst inst)
* overlap with the immediate and setting them would overwrite the
* immediate we set.
*/
if (devinfo->gen >= 6 &&
if (devinfo->ver >= 6 &&
!(devinfo->is_haswell &&
brw_inst_opcode(devinfo, &inst) == BRW_OPCODE_DIM) &&
!(devinfo->gen >= 8 &&
!(devinfo->ver >= 8 &&
(brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_DF ||
brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_UQ ||
brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_Q))) {
@ -1606,7 +1606,7 @@ precompact(const struct gen_device_info *devinfo, brw_inst inst)
* Compaction of floating-point immediates is improved on Gen12, thus
* removing the need for this.
*/
if (devinfo->gen < 12 &&
if (devinfo->ver < 12 &&
brw_inst_imm_ud(devinfo, &inst) == 0x0 &&
brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_F &&
brw_inst_dst_type(devinfo, &inst) == BRW_REGISTER_TYPE_F &&
@ -1620,7 +1620,7 @@ precompact(const struct gen_device_info *devinfo, brw_inst inst)
*
* FINISHME: Use dst:f | imm:f on Gen12
*/
if (devinfo->gen < 12 &&
if (devinfo->ver < 12 &&
compact_immediate(devinfo, BRW_REGISTER_TYPE_D,
brw_inst_imm_ud(devinfo, &inst)) != -1 &&
brw_inst_cond_modifier(devinfo, &inst) == BRW_CONDITIONAL_NONE &&
@ -1652,7 +1652,7 @@ try_compact_instruction(const struct compaction_state *c,
assert(brw_inst_cmpt_control(devinfo, src) == 0);
if (is_3src(devinfo, brw_inst_opcode(devinfo, src))) {
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
memset(&temp, 0, sizeof(temp));
if (brw_try_compact_3src_instruction(devinfo, &temp, src)) {
*dst = temp;
@ -1672,7 +1672,7 @@ try_compact_instruction(const struct compaction_state *c,
if (is_immediate) {
/* Instructions with immediates cannot be compacted on Gen < 6 */
if (devinfo->gen < 6)
if (devinfo->ver < 6)
return false;
compacted_imm = compact_immediate(devinfo, type,
@ -1706,7 +1706,7 @@ try_compact_instruction(const struct compaction_state *c,
if (!set_src1_index(c, &temp, src, is_immediate, compacted_imm))
return false;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
compact(swsb);
compact_reg(dst);
compact_reg(src0);
@ -1718,13 +1718,13 @@ try_compact_instruction(const struct compaction_state *c,
compact_reg(src1);
}
} else {
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
compact(acc_wr_control);
} else {
compact(mask_control_ex);
}
if (devinfo->gen <= 6)
if (devinfo->ver <= 6)
compact(flag_subreg_nr);
compact(cond_modifier);
@ -1766,7 +1766,7 @@ set_uncompacted_control(const struct compaction_state *c, brw_inst *dst,
uint32_t uncompacted =
c->control_index_table[brw_compact_inst_control_index(devinfo, src)];
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_bits(dst, 95, 92, (uncompacted >> 17));
brw_inst_set_bits(dst, 34, 34, (uncompacted >> 16) & 0x1);
brw_inst_set_bits(dst, 33, 33, (uncompacted >> 15) & 0x1);
@ -1777,7 +1777,7 @@ set_uncompacted_control(const struct compaction_state *c, brw_inst *dst,
brw_inst_set_bits(dst, 23, 22, (uncompacted >> 6) & 0x3);
brw_inst_set_bits(dst, 21, 19, (uncompacted >> 3) & 0x7);
brw_inst_set_bits(dst, 18, 16, (uncompacted >> 0) & 0x7);
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
brw_inst_set_bits(dst, 33, 31, (uncompacted >> 16));
brw_inst_set_bits(dst, 23, 12, (uncompacted >> 4) & 0xfff);
brw_inst_set_bits(dst, 10, 9, (uncompacted >> 2) & 0x3);
@ -1787,7 +1787,7 @@ set_uncompacted_control(const struct compaction_state *c, brw_inst *dst,
brw_inst_set_bits(dst, 31, 31, (uncompacted >> 16) & 0x1);
brw_inst_set_bits(dst, 23, 8, (uncompacted & 0xffff));
if (devinfo->gen == 7)
if (devinfo->ver == 7)
brw_inst_set_bits(dst, 90, 89, uncompacted >> 17);
}
}
@ -1800,7 +1800,7 @@ set_uncompacted_datatype(const struct compaction_state *c, brw_inst *dst,
uint32_t uncompacted =
c->datatype_table[brw_compact_inst_datatype_index(devinfo, src)];
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_bits(dst, 98, 98, (uncompacted >> 19));
brw_inst_set_bits(dst, 91, 88, (uncompacted >> 15) & 0xf);
brw_inst_set_bits(dst, 66, 66, (uncompacted >> 14) & 0x1);
@ -1811,7 +1811,7 @@ set_uncompacted_datatype(const struct compaction_state *c, brw_inst *dst,
brw_inst_set_bits(dst, 43, 40, (uncompacted >> 5) & 0xf);
brw_inst_set_bits(dst, 39, 36, (uncompacted >> 1) & 0xf);
brw_inst_set_bits(dst, 35, 35, (uncompacted >> 0) & 0x1);
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
brw_inst_set_bits(dst, 63, 61, (uncompacted >> 18));
brw_inst_set_bits(dst, 94, 89, (uncompacted >> 12) & 0x3f);
brw_inst_set_bits(dst, 46, 35, (uncompacted >> 0) & 0xfff);
@ -1829,7 +1829,7 @@ set_uncompacted_subreg(const struct compaction_state *c, brw_inst *dst,
uint16_t uncompacted =
c->subreg_table[brw_compact_inst_subreg_index(devinfo, src)];
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_bits(dst, 103, 99, (uncompacted >> 10));
brw_inst_set_bits(dst, 71, 67, (uncompacted >> 5) & 0x1f);
brw_inst_set_bits(dst, 55, 51, (uncompacted >> 0) & 0x1f);
@ -1848,7 +1848,7 @@ set_uncompacted_src0(const struct compaction_state *c, brw_inst *dst,
uint32_t compacted = brw_compact_inst_src0_index(devinfo, src);
uint16_t uncompacted = c->src0_index_table[compacted];
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_bits(dst, 87, 84, (uncompacted >> 8));
brw_inst_set_bits(dst, 83, 81, (uncompacted >> 5) & 0x7);
brw_inst_set_bits(dst, 80, 80, (uncompacted >> 4) & 0x1);
@ -1867,7 +1867,7 @@ set_uncompacted_src1(const struct compaction_state *c, brw_inst *dst,
uint16_t uncompacted =
c->src1_index_table[brw_compact_inst_src1_index(devinfo, src)];
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_bits(dst, 121, 120, (uncompacted >> 10));
brw_inst_set_bits(dst, 119, 116, (uncompacted >> 6) & 0xf);
brw_inst_set_bits(dst, 115, 113, (uncompacted >> 3) & 0x7);
@ -1883,9 +1883,9 @@ set_uncompacted_3src_control_index(const struct compaction_state *c,
brw_inst *dst, brw_compact_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
uint64_t compacted = brw_compact_inst_3src_control_index(devinfo, src);
uint64_t uncompacted = gen12_3src_control_index_table[compacted];
@ -1914,7 +1914,7 @@ set_uncompacted_3src_control_index(const struct compaction_state *c,
brw_inst_set_bits(dst, 34, 32, (uncompacted >> 21) & 0x7);
brw_inst_set_bits(dst, 28, 8, (uncompacted >> 0) & 0x1fffff);
if (devinfo->gen >= 9 || devinfo->is_cherryview)
if (devinfo->ver >= 9 || devinfo->is_cherryview)
brw_inst_set_bits(dst, 36, 35, (uncompacted >> 24) & 0x3);
}
}
@ -1923,11 +1923,11 @@ static void
set_uncompacted_3src_source_index(const struct gen_device_info *devinfo,
brw_inst *dst, brw_compact_inst *src)
{
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
uint32_t compacted = brw_compact_inst_3src_source_index(devinfo, src);
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
uint32_t uncompacted = gen12_3src_source_index_table[compacted];
brw_inst_set_bits(dst, 114, 114, (uncompacted >> 20));
@ -1954,7 +1954,7 @@ set_uncompacted_3src_source_index(const struct gen_device_info *devinfo,
brw_inst_set_bits(dst, 72, 65, (uncompacted >> 19) & 0xff);
brw_inst_set_bits(dst, 55, 37, (uncompacted >> 0) & 0x7ffff);
if (devinfo->gen >= 9 || devinfo->is_cherryview) {
if (devinfo->ver >= 9 || devinfo->is_cherryview) {
brw_inst_set_bits(dst, 126, 125, (uncompacted >> 47) & 0x3);
brw_inst_set_bits(dst, 105, 104, (uncompacted >> 45) & 0x3);
brw_inst_set_bits(dst, 84, 84, (uncompacted >> 44) & 0x1);
@ -1969,7 +1969,7 @@ static void
set_uncompacted_3src_subreg_index(const struct gen_device_info *devinfo,
brw_inst *dst, brw_compact_inst *src)
{
assert(devinfo->gen >= 12);
assert(devinfo->ver >= 12);
uint32_t compacted = brw_compact_inst_3src_subreg_index(devinfo, src);
uint32_t uncompacted = gen12_3src_subreg_table[compacted];
@ -1985,7 +1985,7 @@ brw_uncompact_3src_instruction(const struct compaction_state *c,
brw_inst *dst, brw_compact_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
#define uncompact(field) \
brw_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
@ -1994,7 +1994,7 @@ brw_uncompact_3src_instruction(const struct compaction_state *c,
uncompact(hw_opcode);
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
set_uncompacted_3src_control_index(c, dst, src);
set_uncompacted_3src_source_index(devinfo, dst, src);
set_uncompacted_3src_subreg_index(devinfo, dst, src);
@ -2035,7 +2035,7 @@ uncompact_instruction(const struct compaction_state *c, brw_inst *dst,
const struct gen_device_info *devinfo = c->devinfo;
memset(dst, 0, sizeof(*dst));
if (devinfo->gen >= 8 &&
if (devinfo->ver >= 8 &&
is_3src(devinfo, brw_opcode_decode(
devinfo, brw_compact_inst_3src_hw_opcode(devinfo, src)))) {
brw_uncompact_3src_instruction(c, dst, src);
@ -2066,12 +2066,12 @@ uncompact_instruction(const struct compaction_state *c, brw_inst *dst,
uncompact_reg(src1);
}
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
uncompact(swsb);
uncompact_reg(dst);
uncompact_reg(src0);
} else {
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
uncompact(acc_wr_control);
} else {
uncompact(mask_control_ex);
@ -2079,7 +2079,7 @@ uncompact_instruction(const struct compaction_state *c, brw_inst *dst,
uncompact(cond_modifier);
if (devinfo->gen <= 6)
if (devinfo->ver <= 6)
uncompact(flag_subreg_nr);
uncompact_reg(dst);
@ -2105,7 +2105,7 @@ void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
brw_inst *uncompacted)
{
fprintf(stderr, "Instruction compact/uncompact changed (gen%d):\n",
devinfo->gen);
devinfo->ver);
fprintf(stderr, " before: ");
brw_disassemble_inst(stderr, devinfo, orig, true, 0, NULL);
@ -2144,7 +2144,7 @@ update_uip_jip(const struct gen_device_info *devinfo, brw_inst *insn,
* - bytes on Gen8+; and
* - compacted instructions on Gen6+.
*/
int shift = devinfo->gen >= 8 ? 3 : 0;
int shift = devinfo->ver >= 8 ? 3 : 0;
int32_t jip_compacted = brw_inst_jip(devinfo, insn) >> shift;
jip_compacted -= compacted_between(this_old_ip,
@ -2154,7 +2154,7 @@ update_uip_jip(const struct gen_device_info *devinfo, brw_inst *insn,
if (brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ENDIF ||
brw_inst_opcode(devinfo, insn) == BRW_OPCODE_WHILE ||
(brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ELSE && devinfo->gen <= 7))
(brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ELSE && devinfo->ver <= 7))
return;
int32_t uip_compacted = brw_inst_uip(devinfo, insn) >> shift;
@ -2168,7 +2168,7 @@ static void
update_gen4_jump_count(const struct gen_device_info *devinfo, brw_inst *insn,
int this_old_ip, int *compacted_counts)
{
assert(devinfo->gen == 5 || devinfo->is_g4x);
assert(devinfo->ver == 5 || devinfo->is_g4x);
/* Jump Count is in units of:
* - uncompacted instructions on G45; and
@ -2215,7 +2215,7 @@ compaction_state_init(struct compaction_state *c,
assert(gen12_src1_index_table[ARRAY_SIZE(gen12_src1_index_table) - 1] != 0);
c->devinfo = devinfo;
switch (devinfo->gen) {
switch (devinfo->ver) {
case 12:
c->control_index_table = gen12_control_index_table;;
c->datatype_table = gen12_datatype_table;
@ -2284,7 +2284,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
*/
int old_ip[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst) + 1];
if (devinfo->gen == 4 && !devinfo->is_g4x)
if (devinfo->ver == 4 && !devinfo->is_g4x)
return;
struct compaction_state c;
@ -2359,7 +2359,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
case BRW_OPCODE_BREAK:
case BRW_OPCODE_CONTINUE:
case BRW_OPCODE_HALT:
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
update_uip_jip(devinfo, insn, this_old_ip, compacted_counts);
} else {
update_gen4_jump_count(devinfo, insn, this_old_ip,
@ -2372,7 +2372,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
case BRW_OPCODE_ELSE:
case BRW_OPCODE_ENDIF:
case BRW_OPCODE_WHILE:
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
if (brw_inst_cmpt_control(devinfo, insn)) {
brw_inst uncompacted;
uncompact_instruction(&c, &uncompacted,
@ -2387,7 +2387,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
} else {
update_uip_jip(devinfo, insn, this_old_ip, compacted_counts);
}
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
assert(!brw_inst_cmpt_control(devinfo, insn));
/* Jump Count is in units of compacted instructions on Gen6. */

288
src/intel/compiler/brw_eu_emit.c
View file

@ -48,14 +48,14 @@ gen6_resolve_implied_move(struct brw_codegen *p,
unsigned msg_reg_nr)
{
const struct gen_device_info *devinfo = p->devinfo;
if (devinfo->gen < 6)
if (devinfo->ver < 6)
return;
if (src->file == BRW_MESSAGE_REGISTER_FILE)
return;
if (src->file != BRW_ARCHITECTURE_REGISTER_FILE || src->nr != BRW_ARF_NULL) {
assert(devinfo->gen < 12);
assert(devinfo->ver < 12);
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
@ -79,7 +79,7 @@ gen7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg)
* registers required for messages with EOT.
*/
const struct gen_device_info *devinfo = p->devinfo;
if (devinfo->gen >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) {
if (devinfo->ver >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) {
reg->file = BRW_GENERAL_REGISTER_FILE;
reg->nr += GEN7_MRF_HACK_START;
}
@ -91,7 +91,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
const struct gen_device_info *devinfo = p->devinfo;
if (dest.file == BRW_MESSAGE_REGISTER_FILE)
assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
else if (dest.file == BRW_GENERAL_REGISTER_FILE)
assert(dest.nr < 128);
@ -109,7 +109,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
gen7_convert_mrf_to_grf(p, &dest);
if (devinfo->gen >= 12 &&
if (devinfo->ver >= 12 &&
(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC)) {
assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
@ -125,7 +125,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
} else if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDSC) {
assert(devinfo->gen < 12);
assert(devinfo->ver < 12);
assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
dest.file == BRW_ARCHITECTURE_REGISTER_FILE);
assert(dest.address_mode == BRW_ADDRESS_DIRECT);
@ -195,7 +195,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
* this code to fix it.
*/
bool fix_exec_size;
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
fix_exec_size = dest.width < BRW_EXECUTE_4;
else
fix_exec_size = dest.width < BRW_EXECUTE_8;
@ -211,13 +211,13 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
const struct gen_device_info *devinfo = p->devinfo;
if (reg.file == BRW_MESSAGE_REGISTER_FILE)
assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
else if (reg.file == BRW_GENERAL_REGISTER_FILE)
assert(reg.nr < 128);
gen7_convert_mrf_to_grf(p, &reg);
if (devinfo->gen >= 6 &&
if (devinfo->ver >= 6 &&
(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||
@ -231,7 +231,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
assert(reg.address_mode == BRW_ADDRESS_DIRECT);
}
if (devinfo->gen >= 12 &&
if (devinfo->ver >= 12 &&
(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC)) {
assert(reg.file != BRW_IMMEDIATE_VALUE);
@ -271,7 +271,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
else
brw_inst_set_imm_ud(devinfo, inst, reg.ud);
if (devinfo->gen < 12 && type_sz(reg.type) < 8) {
if (devinfo->ver < 12 && type_sz(reg.type) < 8) {
brw_inst_set_src1_reg_file(devinfo, inst,
BRW_ARCHITECTURE_REGISTER_FILE);
brw_inst_set_src1_reg_hw_type(devinfo, inst,
@ -321,7 +321,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
* descriptions for registers in align_16 as align_1:
*/
brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
} else if (devinfo->gen == 7 && !devinfo->is_haswell &&
} else if (devinfo->ver == 7 && !devinfo->is_haswell &&
reg.type == BRW_REGISTER_TYPE_DF &&
reg.vstride == BRW_VERTICAL_STRIDE_2) {
/* From SNB PRM:
@ -351,7 +351,7 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDSC ||
(devinfo->gen >= 12 &&
(devinfo->ver >= 12 &&
(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC))) {
assert(reg.file == BRW_GENERAL_REGISTER_FILE ||
@ -428,7 +428,7 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
* descriptions for registers in align_16 as align_1:
*/
brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
} else if (devinfo->gen == 7 && !devinfo->is_haswell &&
} else if (devinfo->ver == 7 && !devinfo->is_haswell &&
reg.type == BRW_REGISTER_TYPE_DF &&
reg.vstride == BRW_VERTICAL_STRIDE_2) {
/* From SNB PRM:
@ -458,11 +458,11 @@ brw_set_desc_ex(struct brw_codegen *p, brw_inst *inst,
const struct gen_device_info *devinfo = p->devinfo;
assert(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC);
if (devinfo->gen < 12)
if (devinfo->ver < 12)
brw_inst_set_src1_file_type(devinfo, inst,
BRW_IMMEDIATE_VALUE, BRW_REGISTER_TYPE_UD);
brw_inst_set_send_desc(devinfo, inst, desc);
if (devinfo->gen >= 9)
if (devinfo->ver >= 9)
brw_inst_set_send_ex_desc(devinfo, inst, ex_desc);
}
@ -546,9 +546,9 @@ static void brw_set_urb_message( struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
assert(devinfo->gen < 7 || swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
assert(devinfo->gen < 7 || !(flags & BRW_URB_WRITE_ALLOCATE));
assert(devinfo->gen >= 7 || !(flags & BRW_URB_WRITE_PER_SLOT_OFFSET));
assert(devinfo->ver < 7 || swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
assert(devinfo->ver < 7 || !(flags & BRW_URB_WRITE_ALLOCATE));
assert(devinfo->ver >= 7 || !(flags & BRW_URB_WRITE_PER_SLOT_OFFSET));
brw_set_desc(p, insn, brw_message_desc(
devinfo, msg_length, response_length, true));
@ -566,11 +566,11 @@ static void brw_set_urb_message( struct brw_codegen *p,
brw_inst_set_urb_global_offset(devinfo, insn, offset);
brw_inst_set_urb_swizzle_control(devinfo, insn, swizzle_control);
if (devinfo->gen < 8) {
if (devinfo->ver < 8) {
brw_inst_set_urb_complete(devinfo, insn, !!(flags & BRW_URB_WRITE_COMPLETE));
}
if (devinfo->gen < 7) {
if (devinfo->ver < 7) {
brw_inst_set_urb_allocate(devinfo, insn, !!(flags & BRW_URB_WRITE_ALLOCATE));
brw_inst_set_urb_used(devinfo, insn, !(flags & BRW_URB_WRITE_UNUSED));
} else {
@ -593,8 +593,8 @@ gen7_set_dp_scratch_message(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
assert(num_regs == 1 || num_regs == 2 || num_regs == 4 ||
(devinfo->gen >= 8 && num_regs == 8));
const unsigned block_size = (devinfo->gen >= 8 ? util_logbase2(num_regs) :
(devinfo->ver >= 8 && num_regs == 8));
const unsigned block_size = (devinfo->ver >= 8 ? util_logbase2(num_regs) :
num_regs - 1);
brw_set_desc(p, inst, brw_message_desc(
@ -619,7 +619,7 @@ brw_inst_set_state(const struct gen_device_info *devinfo,
brw_inst_set_compression(devinfo, insn, state->compressed);
brw_inst_set_access_mode(devinfo, insn, state->access_mode);
brw_inst_set_mask_control(devinfo, insn, state->mask_control);
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
brw_inst_set_swsb(devinfo, insn, tgl_swsb_encode(state->swsb));
brw_inst_set_saturate(devinfo, insn, state->saturate);
brw_inst_set_pred_control(devinfo, insn, state->predicate);
@ -628,15 +628,15 @@ brw_inst_set_state(const struct gen_device_info *devinfo,
if (is_3src(devinfo, brw_inst_opcode(devinfo, insn)) &&
state->access_mode == BRW_ALIGN_16) {
brw_inst_set_3src_a16_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
brw_inst_set_3src_a16_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
} else {
brw_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
brw_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
}
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
brw_inst_set_acc_wr_control(devinfo, insn, state->acc_wr_control);
}
@ -749,10 +749,10 @@ to_3src_align1_vstride(const struct gen_device_info *devinfo,
case BRW_VERTICAL_STRIDE_0:
return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0;
case BRW_VERTICAL_STRIDE_1:
assert(devinfo->gen >= 12);
assert(devinfo->ver >= 12);
return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1;
case BRW_VERTICAL_STRIDE_2:
assert(devinfo->gen < 12);
assert(devinfo->ver < 12);
return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2;
case BRW_VERTICAL_STRIDE_4:
return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4;
@ -793,7 +793,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
assert(dest.nr < 128);
if (devinfo->gen >= 10)
if (devinfo->ver >= 10)
assert(!(src0.file == BRW_IMMEDIATE_VALUE &&
src2.file == BRW_IMMEDIATE_VALUE));
@ -809,7 +809,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
dest.file == BRW_ARCHITECTURE_REGISTER_FILE);
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_3src_a1_dst_reg_file(devinfo, inst, dest.file);
brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
} else {
@ -891,7 +891,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
assert(src2.file == BRW_GENERAL_REGISTER_FILE ||
src2.file == BRW_IMMEDIATE_VALUE);
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
if (src0.file == BRW_IMMEDIATE_VALUE) {
brw_inst_set_3src_a1_src0_is_imm(devinfo, inst, 1);
} else {
@ -927,8 +927,8 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
dest.type == BRW_REGISTER_TYPE_DF ||
dest.type == BRW_REGISTER_TYPE_D ||
dest.type == BRW_REGISTER_TYPE_UD ||
(dest.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 8));
if (devinfo->gen == 6) {
(dest.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 8));
if (devinfo->ver == 6) {
brw_inst_set_3src_a16_dst_reg_file(devinfo, inst,
dest.file == BRW_MESSAGE_REGISTER_FILE);
}
@ -963,7 +963,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
brw_inst_set_3src_a16_src2_rep_ctrl(devinfo, inst,
src2.vstride == BRW_VERTICAL_STRIDE_0);
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
/* Set both the source and destination types based on dest.type,
* ignoring the source register types. The MAD and LRP emitters ensure
* that all four types are float. The BFE and BFI2 emitters, however,
@ -1108,7 +1108,7 @@ brw_MOV(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0)
* To avoid the problems that causes, we use an <X,2,0> source region to
* read each element twice.
*/
if (devinfo->gen == 7 && !devinfo->is_haswell &&
if (devinfo->ver == 7 && !devinfo->is_haswell &&
brw_get_default_access_mode(p) == BRW_ALIGN_1 &&
dest.type == BRW_REGISTER_TYPE_DF &&
(src0.type == BRW_REGISTER_TYPE_F ||
@ -1235,7 +1235,7 @@ brw_F32TO16(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
* an undocumented feature.
*/
const bool needs_zero_fill = (dst.type == BRW_REGISTER_TYPE_UD &&
(!align16 || devinfo->gen >= 8));
(!align16 || devinfo->ver >= 8));
brw_inst *inst;
if (align16) {
@ -1254,19 +1254,19 @@ brw_F32TO16(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
dst = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
}
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
inst = brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_HF), src);
} else {
assert(devinfo->gen == 7);
assert(devinfo->ver == 7);
inst = brw_alu1(p, BRW_OPCODE_F32TO16, dst, src);
}
if (needs_zero_fill) {
if (devinfo->gen < 12)
if (devinfo->ver < 12)
brw_inst_set_no_dd_clear(devinfo, inst, true);
brw_set_default_swsb(p, tgl_swsb_null());
inst = brw_MOV(p, suboffset(dst, 1), brw_imm_w(0));
if (devinfo->gen < 12)
if (devinfo->ver < 12)
brw_inst_set_no_dd_check(devinfo, inst, true);
}
@ -1297,10 +1297,10 @@ brw_F16TO32(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
src.type == BRW_REGISTER_TYPE_HF);
}
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
return brw_MOV(p, dst, retype(src, BRW_REGISTER_TYPE_HF));
} else {
assert(devinfo->gen == 7);
assert(devinfo->ver == 7);
return brw_alu1(p, BRW_OPCODE_F16TO32, dst, src);
}
}
@ -1404,16 +1404,16 @@ brw_IF(struct brw_codegen *p, unsigned execute_size)
/* Override the defaults for this instruction:
*/
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
brw_set_dest(p, insn, brw_ip_reg());
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d(0x0));
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
brw_set_dest(p, insn, brw_imm_w(0));
brw_inst_set_gen6_jump_count(devinfo, insn, 0);
brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
brw_set_src1(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
} else if (devinfo->gen == 7) {
} else if (devinfo->ver == 7) {
brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
brw_set_src1(p, insn, brw_imm_w(0));
@ -1421,7 +1421,7 @@ brw_IF(struct brw_codegen *p, unsigned execute_size)
brw_inst_set_uip(devinfo, insn, 0);
} else {
brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
if (devinfo->gen < 12)
if (devinfo->ver < 12)
brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(devinfo, insn, 0);
brw_inst_set_uip(devinfo, insn, 0);
@ -1431,7 +1431,7 @@ brw_IF(struct brw_codegen *p, unsigned execute_size)
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NORMAL);
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_ENABLE);
if (!p->single_program_flow && devinfo->gen < 6)
if (!p->single_program_flow && devinfo->ver < 6)
brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
push_if_stack(p, insn);
@ -1527,7 +1527,7 @@ patch_IF_ELSE(struct brw_codegen *p,
* instructions to conditional ADDs. So we do patch IF and ELSE
* instructions in single program flow mode on those platforms.
*/
if (devinfo->gen < 6)
if (devinfo->ver < 6)
assert(!p->single_program_flow);
assert(if_inst != NULL && brw_inst_opcode(devinfo, if_inst) == BRW_OPCODE_IF);
@ -1541,7 +1541,7 @@ patch_IF_ELSE(struct brw_codegen *p,
if (else_inst == NULL) {
/* Patch IF -> ENDIF */
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
/* Turn it into an IFF, which means no mask stack operations for
* all-false and jumping past the ENDIF.
*/
@ -1549,7 +1549,7 @@ patch_IF_ELSE(struct brw_codegen *p,
brw_inst_set_gen4_jump_count(devinfo, if_inst,
br * (endif_inst - if_inst + 1));
brw_inst_set_gen4_pop_count(devinfo, if_inst, 0);
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
/* As of gen6, there is no IFF and IF must point to the ENDIF. */
brw_inst_set_gen6_jump_count(devinfo, if_inst, br*(endif_inst - if_inst));
} else {
@ -1560,24 +1560,24 @@ patch_IF_ELSE(struct brw_codegen *p,
brw_inst_set_exec_size(devinfo, else_inst, brw_inst_exec_size(devinfo, if_inst));
/* Patch IF -> ELSE */
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
brw_inst_set_gen4_jump_count(devinfo, if_inst,
br * (else_inst - if_inst));
brw_inst_set_gen4_pop_count(devinfo, if_inst, 0);
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
brw_inst_set_gen6_jump_count(devinfo, if_inst,
br * (else_inst - if_inst + 1));
}
/* Patch ELSE -> ENDIF */
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
/* BRW_OPCODE_ELSE pre-gen6 should point just past the
* matching ENDIF.
*/
brw_inst_set_gen4_jump_count(devinfo, else_inst,
br * (endif_inst - else_inst + 1));
brw_inst_set_gen4_pop_count(devinfo, else_inst, 1);
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
/* BRW_OPCODE_ELSE on gen6 should point to the matching ENDIF. */
brw_inst_set_gen6_jump_count(devinfo, else_inst,
br * (endif_inst - else_inst));
@ -1587,7 +1587,7 @@ patch_IF_ELSE(struct brw_codegen *p,
/* The IF instruction's UIP and ELSE's JIP should point to ENDIF */
brw_inst_set_uip(devinfo, if_inst, br * (endif_inst - if_inst));
brw_inst_set_jip(devinfo, else_inst, br * (endif_inst - else_inst));
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
/* Since we don't set branch_ctrl, the ELSE's JIP and UIP both
* should point to ENDIF.
*/
@ -1605,16 +1605,16 @@ brw_ELSE(struct brw_codegen *p)
insn = next_insn(p, BRW_OPCODE_ELSE);
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
brw_set_dest(p, insn, brw_ip_reg());
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d(0x0));
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
brw_set_dest(p, insn, brw_imm_w(0));
brw_inst_set_gen6_jump_count(devinfo, insn, 0);
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
} else if (devinfo->gen == 7) {
} else if (devinfo->ver == 7) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_w(0));
@ -1622,7 +1622,7 @@ brw_ELSE(struct brw_codegen *p)
brw_inst_set_uip(devinfo, insn, 0);
} else {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
if (devinfo->gen < 12)
if (devinfo->ver < 12)
brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(devinfo, insn, 0);
brw_inst_set_uip(devinfo, insn, 0);
@ -1630,7 +1630,7 @@ brw_ELSE(struct brw_codegen *p)
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_ENABLE);
if (!p->single_program_flow && devinfo->gen < 6)
if (!p->single_program_flow && devinfo->ver < 6)
brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
push_if_stack(p, insn);
@ -1658,7 +1658,7 @@ brw_ENDIF(struct brw_codegen *p)
* instructions to conditional ADDs. So we only do this trick on Gen4 and
* Gen5.
*/
if (devinfo->gen < 6 && p->single_program_flow)
if (devinfo->ver < 6 && p->single_program_flow)
emit_endif = false;
/*
@ -1684,15 +1684,15 @@ brw_ENDIF(struct brw_codegen *p)
return;
}
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_d(0x0));
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
brw_set_dest(p, insn, brw_imm_w(0));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
} else if (devinfo->gen == 7) {
} else if (devinfo->ver == 7) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_w(0));
@ -1702,14 +1702,14 @@ brw_ENDIF(struct brw_codegen *p)
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_ENABLE);
if (devinfo->gen < 6)
if (devinfo->ver < 6)
brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
/* Also pop item off the stack in the endif instruction: */
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
brw_inst_set_gen4_jump_count(devinfo, insn, 0);
brw_inst_set_gen4_pop_count(devinfo, insn, 1);
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
brw_inst_set_gen6_jump_count(devinfo, insn, 2);
} else {
brw_inst_set_jip(devinfo, insn, 2);
@ -1724,10 +1724,10 @@ brw_BREAK(struct brw_codegen *p)
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_BREAK);
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, brw_imm_d(0x0));
} else if (devinfo->gen >= 6) {
} else if (devinfo->ver >= 6) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_d(0x0));
@ -1752,14 +1752,14 @@ brw_CONT(struct brw_codegen *p)
insn = next_insn(p, BRW_OPCODE_CONTINUE);
brw_set_dest(p, insn, brw_ip_reg());
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
brw_set_src0(p, insn, brw_imm_d(0x0));
} else {
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d(0x0));
}
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
brw_inst_set_gen4_pop_count(devinfo, insn,
p->if_depth_in_loop[p->loop_stack_depth]);
}
@ -1776,7 +1776,7 @@ brw_HALT(struct brw_codegen *p)
insn = next_insn(p, BRW_OPCODE_HALT);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
/* From the Gen4 PRM:
*
* "IP register must be put (for example, by the assembler) at <dst>
@ -1785,10 +1785,10 @@ brw_HALT(struct brw_codegen *p)
brw_set_dest(p, insn, brw_ip_reg());
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d(0x0)); /* exitcode updated later. */
} else if (devinfo->gen < 8) {
} else if (devinfo->ver < 8) {
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_d(0x0)); /* UIP and JIP, updated later. */
} else if (devinfo->gen < 12) {
} else if (devinfo->ver < 12) {
brw_set_src0(p, insn, brw_imm_d(0x0));
}
@ -1818,7 +1818,7 @@ brw_DO(struct brw_codegen *p, unsigned execute_size)
{
const struct gen_device_info *devinfo = p->devinfo;
if (devinfo->gen >= 6 || p->single_program_flow) {
if (devinfo->ver >= 6 || p->single_program_flow) {
push_loop_stack(p, &p->store[p->nr_insn]);
return &p->store[p->nr_insn];
} else {
@ -1855,7 +1855,7 @@ brw_patch_break_cont(struct brw_codegen *p, brw_inst *while_inst)
brw_inst *inst;
unsigned br = brw_jump_scale(devinfo);
assert(devinfo->gen < 6);
assert(devinfo->ver < 6);
for (inst = while_inst - 1; inst != do_inst; inst--) {
/* If the jump count is != 0, that means that this instruction has already
@ -1879,16 +1879,16 @@ brw_WHILE(struct brw_codegen *p)
brw_inst *insn, *do_insn;
unsigned br = brw_jump_scale(devinfo);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
insn = next_insn(p, BRW_OPCODE_WHILE);
do_insn = get_inner_do_insn(p);
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
if (devinfo->gen < 12)
if (devinfo->ver < 12)
brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(devinfo, insn, br * (do_insn - insn));
} else if (devinfo->gen == 7) {
} else if (devinfo->ver == 7) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_w(0));
@ -1943,7 +1943,7 @@ void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx)
brw_inst *jmp_insn = &p->store[jmp_insn_idx];
unsigned jmpi = 1;
if (devinfo->gen >= 5)
if (devinfo->ver >= 5)
jmpi = 2;
assert(brw_inst_opcode(devinfo, jmp_insn) == BRW_OPCODE_JMPI);
@ -1978,7 +1978,7 @@ void brw_CMP(struct brw_codegen *p,
* It also applies to other Gen7 platforms (IVB, BYT) even though it isn't
* mentioned on their work-arounds pages.
*/
if (devinfo->gen == 7) {
if (devinfo->ver == 7) {
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
dest.nr == BRW_ARF_NULL) {
brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
@ -2008,7 +2008,7 @@ void brw_CMPN(struct brw_codegen *p,
*
* Page 77 of the Haswell PRM Volume 2b contains the same text.
*/
if (devinfo->gen == 7) {
if (devinfo->ver == 7) {
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
dest.nr == BRW_ARF_NULL) {
brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
@ -2038,7 +2038,7 @@ void gen4_math(struct brw_codegen *p,
data_type = BRW_MATH_DATA_VECTOR;
}
assert(devinfo->gen < 6);
assert(devinfo->ver < 6);
/* Example code doesn't set predicate_control for send
* instructions.
@ -2065,13 +2065,13 @@ void gen6_math(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn = next_insn(p, BRW_OPCODE_MATH);
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
(devinfo->gen >= 7 && dest.file == BRW_MESSAGE_REGISTER_FILE));
(devinfo->ver >= 7 && dest.file == BRW_MESSAGE_REGISTER_FILE));
assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1);
if (devinfo->gen == 6) {
if (devinfo->ver == 6) {
assert(src0.hstride == BRW_HORIZONTAL_STRIDE_1);
assert(src1.hstride == BRW_HORIZONTAL_STRIDE_1);
}
@ -2082,16 +2082,16 @@ void gen6_math(struct brw_codegen *p,
assert(src0.type != BRW_REGISTER_TYPE_F);
assert(src1.type != BRW_REGISTER_TYPE_F);
assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
(devinfo->gen >= 8 && src1.file == BRW_IMMEDIATE_VALUE));
(devinfo->ver >= 8 && src1.file == BRW_IMMEDIATE_VALUE));
} else {
assert(src0.type == BRW_REGISTER_TYPE_F ||
(src0.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 9));
(src0.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 9));
assert(src1.type == BRW_REGISTER_TYPE_F ||
(src1.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 9));
(src1.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 9));
}
/* Source modifiers are ignored for extended math instructions on Gen6. */
if (devinfo->gen == 6) {
if (devinfo->ver == 6) {
assert(!src0.negate);
assert(!src0.abs);
assert(!src1.negate);
@ -2113,7 +2113,7 @@ unsigned
brw_scratch_surface_idx(const struct brw_codegen *p)
{
/* The scratch space is thread-local so IA coherency is unnecessary. */
if (p->devinfo->gen >= 8)
if (p->devinfo->ver >= 8)
return GEN8_BTI_STATELESS_NON_COHERENT;
else
return BRW_BTI_STATELESS;
@ -2133,13 +2133,13 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
(devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_WRITE);
const struct tgl_swsb swsb = brw_get_default_swsb(p);
uint32_t msg_type;
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
offset /= 16;
mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
@ -2187,7 +2187,7 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
src_header = vec16(src_header);
assert(brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE);
if (devinfo->gen < 6)
if (devinfo->ver < 6)
brw_inst_set_base_mrf(devinfo, insn, mrf.nr);
/* Until gen6, writes followed by reads from the same location
@ -2200,7 +2200,7 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
* protection. Our use of DP writes is all about register
* spilling within a thread.
*/
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
dest = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
send_commit_msg = 0;
} else {
@ -2209,13 +2209,13 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
}
brw_set_dest(p, insn, dest);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
brw_set_src0(p, insn, mrf);
} else {
brw_set_src0(p, insn, brw_null_reg());
}
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
else
msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
@ -2247,10 +2247,10 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
const struct tgl_swsb swsb = brw_get_default_swsb(p);
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
offset /= 16;
if (p->devinfo->gen >= 7) {
if (p->devinfo->ver >= 7) {
/* On gen 7 and above, we no longer have message registers and we can
* send from any register we want. By using the destination register
* for the message, we guarantee that the implied message write won't
@ -2266,8 +2266,8 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
const unsigned rlen = num_regs;
const unsigned target_cache =
(devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
(devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_READ);
{
@ -2296,7 +2296,7 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
brw_inst_set_compression(devinfo, insn, false);
brw_set_dest(p, insn, dest); /* UW? */
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
brw_set_src0(p, insn, mrf);
} else {
brw_set_src0(p, insn, brw_null_reg());
@ -2359,13 +2359,13 @@ void brw_oword_block_read(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_CONSTANT_CACHE :
(devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_CONSTANT_CACHE :
BRW_SFID_DATAPORT_READ);
const unsigned exec_size = 1 << brw_get_default_exec_size(p);
const struct tgl_swsb swsb = brw_get_default_swsb(p);
/* On newer hardware, offset is in units of owords. */
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
offset /= 16;
mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
@ -2400,7 +2400,7 @@ void brw_oword_block_read(struct brw_codegen *p,
dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
brw_set_dest(p, insn, dest);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
brw_set_src0(p, insn, mrf);
} else {
brw_set_src0(p, insn, brw_null_reg());
@ -2431,7 +2431,7 @@ brw_fb_WRITE(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
(devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_WRITE);
brw_inst *insn;
unsigned msg_type;
@ -2442,7 +2442,7 @@ brw_fb_WRITE(struct brw_codegen *p,
else
dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
insn = next_insn(p, BRW_OPCODE_SENDC);
} else {
insn = next_insn(p, BRW_OPCODE_SEND);
@ -2450,7 +2450,7 @@ brw_fb_WRITE(struct brw_codegen *p,
brw_inst_set_sfid(devinfo, insn, target_cache);
brw_inst_set_compression(devinfo, insn, false);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
/* headerless version, just submit color payload */
src0 = payload;
@ -2486,7 +2486,7 @@ gen9_fb_READ(struct brw_codegen *p,
bool per_sample)
{
const struct gen_device_info *devinfo = p->devinfo;
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
const unsigned msg_subtype =
brw_get_default_exec_size(p) == BRW_EXECUTE_16 ? 0 : 1;
brw_inst *insn = next_insn(p, BRW_OPCODE_SENDC);
@ -2548,7 +2548,7 @@ void brw_SAMPLE(struct brw_codegen *p,
*/
brw_inst_set_compression(devinfo, insn, false);
if (devinfo->gen < 6)
if (devinfo->ver < 6)
brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr);
brw_set_dest(p, insn, dest);
@ -2583,7 +2583,7 @@ void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
uint32_t sampler = sampler_index.ud;
if (sampler >= 16) {
assert(devinfo->is_haswell || devinfo->gen >= 8);
assert(devinfo->is_haswell || devinfo->ver >= 8);
brw_ADD(p,
get_element_ud(header, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
@ -2591,7 +2591,7 @@ void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
}
} else {
/* Non-const sampler array indexing case */
if (devinfo->gen < 8 && !devinfo->is_haswell) {
if (devinfo->ver < 8 && !devinfo->is_haswell) {
return;
}
@ -2628,7 +2628,7 @@ void brw_urb_WRITE(struct brw_codegen *p,
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
if (devinfo->gen >= 7 && !(flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
if (devinfo->ver >= 7 && !(flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
/* Enable Channel Masks in the URB_WRITE_HWORD message header */
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
@ -2643,13 +2643,13 @@ void brw_urb_WRITE(struct brw_codegen *p,
insn = next_insn(p, BRW_OPCODE_SEND);
assert(msg_length < BRW_MAX_MRF(devinfo->gen));
assert(msg_length < BRW_MAX_MRF(devinfo->ver));
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, brw_imm_d(0));
if (devinfo->gen < 6)
if (devinfo->ver < 6)
brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr);
brw_set_urb_message(p,
@ -2704,7 +2704,7 @@ brw_send_indirect_message(struct brw_codegen *p,
send = next_insn(p, BRW_OPCODE_SEND);
brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
brw_inst_set_send_sel_reg32_desc(devinfo, send, true);
else
brw_set_src1(p, send, addr);
@ -2760,7 +2760,7 @@ brw_send_indirect_split_message(struct brw_codegen *p,
}
if (ex_desc.file == BRW_IMMEDIATE_VALUE &&
(devinfo->gen >= 12 ||
(devinfo->ver >= 12 ||
((ex_desc.ud | ex_desc_imm) & INTEL_MASK(15, 12)) == 0)) {
ex_desc.ud |= ex_desc_imm;
} else {
@ -2802,7 +2802,7 @@ brw_send_indirect_split_message(struct brw_codegen *p,
brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
}
send = next_insn(p, devinfo->gen >= 12 ? BRW_OPCODE_SEND : BRW_OPCODE_SENDS);
send = next_insn(p, devinfo->ver >= 12 ? BRW_OPCODE_SEND : BRW_OPCODE_SENDS);
brw_set_dest(p, send, dst);
brw_set_src0(p, send, retype(payload0, BRW_REGISTER_TYPE_UD));
brw_set_src1(p, send, retype(payload1, BRW_REGISTER_TYPE_UD));
@ -2873,7 +2873,7 @@ while_jumps_before_offset(const struct gen_device_info *devinfo,
brw_inst *insn, int while_offset, int start_offset)
{
int scale = 16 / brw_jump_scale(devinfo);
int jip = devinfo->gen == 6 ? brw_inst_gen6_jump_count(devinfo, insn)
int jip = devinfo->ver == 6 ? brw_inst_gen6_jump_count(devinfo, insn)
: brw_inst_jip(devinfo, insn);
assert(jip < 0);
return while_offset + jip * scale <= start_offset;
@ -2933,7 +2933,7 @@ brw_find_loop_end(struct brw_codegen *p, int start_offset)
int offset;
void *store = p->store;
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
/* Always start after the instruction (such as a WHILE) we're trying to fix
* up.
@ -2964,7 +2964,7 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset)
int scale = 16 / br;
void *store = p->store;
if (devinfo->gen < 6)
if (devinfo->ver < 6)
return;
for (offset = start_offset; offset < p->next_insn_offset; offset += 16) {
@ -2979,7 +2979,7 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset)
/* Gen7 UIP points to WHILE; Gen6 points just after it */
brw_inst_set_uip(devinfo, insn,
(brw_find_loop_end(p, offset) - offset +
(devinfo->gen == 6 ? 16 : 0)) / scale);
(devinfo->ver == 6 ? 16 : 0)) / scale);
break;
case BRW_OPCODE_CONTINUE:
assert(block_end_offset != 0);
@ -2994,7 +2994,7 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset)
case BRW_OPCODE_ENDIF: {
int32_t jump = (block_end_offset == 0) ?
1 * br : (block_end_offset - offset) / scale;
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
brw_inst_set_jip(devinfo, insn, jump);
else
brw_inst_set_gen6_jump_count(devinfo, insn, jump);
@ -3046,7 +3046,7 @@ void brw_ff_sync(struct brw_codegen *p,
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, brw_imm_d(0));
if (devinfo->gen < 6)
if (devinfo->ver < 6)
brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr);
brw_set_ff_sync_message(p,
@ -3077,8 +3077,8 @@ brw_svb_write(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
(devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_WRITE);
brw_inst *insn;
@ -3120,12 +3120,12 @@ brw_untyped_atomic(struct brw_codegen *p,
bool header_present)
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* SIMD4x2 untyped atomic instructions only exist on HSW+ */
const bool has_simd4x2 = devinfo->gen >= 8 || devinfo->is_haswell;
const bool has_simd4x2 = devinfo->ver >= 8 || devinfo->is_haswell;
const unsigned exec_size = align1 ? 1 << brw_get_default_exec_size(p) :
has_simd4x2 ? 0 : 8;
const unsigned response_length =
@ -3155,7 +3155,7 @@ brw_untyped_surface_read(struct brw_codegen *p,
unsigned num_channels)
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
@ -3178,12 +3178,12 @@ brw_untyped_surface_write(struct brw_codegen *p,
bool header_present)
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* SIMD4x2 untyped surface write instructions only exist on HSW+ */
const bool has_simd4x2 = devinfo->gen >= 8 || devinfo->is_haswell;
const bool has_simd4x2 = devinfo->ver >= 8 || devinfo->is_haswell;
const unsigned exec_size = align1 ? 1 << brw_get_default_exec_size(p) :
has_simd4x2 ? 0 : 8;
const unsigned desc =
@ -3224,7 +3224,7 @@ brw_set_memory_fence_message(struct brw_codegen *p,
if (commit_enable)
brw_inst_set_dp_msg_control(devinfo, insn, 1 << 5);
assert(devinfo->gen >= 11 || bti == 0);
assert(devinfo->ver >= 11 || bti == 0);
brw_inst_set_binding_table_index(devinfo, insn, bti);
}
@ -3293,7 +3293,7 @@ brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst,
const unsigned qtr_control = brw_get_default_group(p) / 8;
brw_inst *inst;
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
assert(mask.type == BRW_REGISTER_TYPE_UD);
brw_push_insn_state(p);
@ -3309,7 +3309,7 @@ brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst,
if (brw_get_default_access_mode(p) == BRW_ALIGN_1) {
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
/* Getting the first active channel index is easy on Gen8: Just find
* the first bit set in the execution mask. The register exists on
* HSW already but it reads back as all ones when the current
@ -3375,7 +3375,7 @@ brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst,
} else {
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
if (devinfo->gen >= 8 &&
if (devinfo->ver >= 8 &&
mask.file == BRW_IMMEDIATE_VALUE && mask.ud == 0xffffffff) {
/* In SIMD4x2 mode the first active channel index is just the
* negation of the first bit of the mask register. Note that ce0
@ -3562,10 +3562,10 @@ void brw_shader_time_add(struct brw_codegen *p,
uint32_t surf_index)
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
@ -3600,7 +3600,7 @@ brw_barrier(struct brw_codegen *p, struct brw_reg src)
const struct gen_device_info *devinfo = p->devinfo;
struct brw_inst *inst;
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
@ -3657,18 +3657,18 @@ brw_float_controls_mode(struct brw_codegen *p,
brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(~mask));
brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
if (p->devinfo->gen < 12)
if (p->devinfo->ver < 12)
brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
if (mode) {
brw_inst *inst_or = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(mode));
brw_inst_set_exec_size(p->devinfo, inst_or, BRW_EXECUTE_1);
if (p->devinfo->gen < 12)
if (p->devinfo->ver < 12)
brw_inst_set_thread_control(p->devinfo, inst_or, BRW_THREAD_SWITCH);
}
if (p->devinfo->gen >= 12)
if (p->devinfo->ver >= 12)
brw_SYNC(p, TGL_SYNC_NOP);
}

56
src/intel/compiler/brw_eu_validate.c
View file

@ -106,7 +106,7 @@ inst_is_send(const struct gen_device_info *devinfo, const brw_inst *inst)
static bool
inst_is_split_send(const struct gen_device_info *devinfo, const brw_inst *inst)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
return inst_is_send(devinfo, inst);
} else {
switch (brw_inst_opcode(devinfo, inst)) {
@ -134,7 +134,7 @@ signed_type(unsigned type)
static enum brw_reg_type
inst_dst_type(const struct gen_device_info *devinfo, const brw_inst *inst)
{
return (devinfo->gen < 12 || !inst_is_send(devinfo, inst)) ?
return (devinfo->ver < 12 || !inst_is_send(devinfo, inst)) ?
brw_inst_dst_type(devinfo, inst) : BRW_REGISTER_TYPE_D;
}
@ -223,7 +223,7 @@ num_sources_from_inst(const struct gen_device_info *devinfo,
if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MATH) {
math_function = brw_inst_math_function(devinfo, inst);
} else if (devinfo->gen < 6 &&
} else if (devinfo->ver < 6 &&
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND) {
if (brw_inst_sfid(devinfo, inst) == BRW_SFID_MATH) {
/* src1 must be a descriptor (including the information to determine
@ -297,7 +297,7 @@ invalid_values(const struct gen_device_info *devinfo, const brw_inst *inst)
* No invalid encodings on Gen10-12 (align1)
*/
} else {
if (devinfo->gen > 6) {
if (devinfo->ver > 6) {
ERROR_IF(brw_inst_dst_reg_file(devinfo, inst) == MRF ||
(num_sources > 0 &&
brw_inst_src0_reg_file(devinfo, inst) == MRF) ||
@ -312,7 +312,7 @@ invalid_values(const struct gen_device_info *devinfo, const brw_inst *inst)
if (num_sources == 3) {
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
if (devinfo->gen >= 10) {
if (devinfo->ver >= 10) {
ERROR_IF(brw_inst_3src_a1_dst_type (devinfo, inst) == INVALID_REG_TYPE ||
brw_inst_3src_a1_src0_type(devinfo, inst) == INVALID_REG_TYPE ||
brw_inst_3src_a1_src1_type(devinfo, inst) == INVALID_REG_TYPE ||
@ -372,7 +372,7 @@ alignment_supported(const struct gen_device_info *devinfo,
{
struct string error_msg = { .str = NULL, .len = 0 };
ERROR_IF(devinfo->gen >= 11 && brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16,
ERROR_IF(devinfo->ver >= 11 && brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16,
"Align16 not supported");
return error_msg;
@ -442,7 +442,7 @@ send_restrictions(const struct gen_device_info *devinfo,
ERROR_IF(brw_inst_src0_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT,
"send must use direct addressing");
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
ERROR_IF(brw_inst_send_src0_reg_file(devinfo, inst) != BRW_GENERAL_REGISTER_FILE,
"send from non-GRF");
ERROR_IF(brw_inst_eot(devinfo, inst) &&
@ -450,7 +450,7 @@ send_restrictions(const struct gen_device_info *devinfo,
"send with EOT must use g112-g127");
}
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
ERROR_IF(!dst_is_null(devinfo, inst) &&
(brw_inst_dst_da_reg_nr(devinfo, inst) +
brw_inst_rlen(devinfo, inst) > 127) &&
@ -553,7 +553,7 @@ execution_type(const struct gen_device_info *devinfo, const brw_inst *inst)
/* Mixed operand types where one is float is float on Gen < 6
* (and not allowed on later platforms)
*/
if (devinfo->gen < 6 &&
if (devinfo->ver < 6 &&
(src0_exec_type == BRW_REGISTER_TYPE_F ||
src1_exec_type == BRW_REGISTER_TYPE_F))
return BRW_REGISTER_TYPE_F;
@ -629,7 +629,7 @@ is_half_float_conversion(const struct gen_device_info *devinfo,
static bool
is_mixed_float(const struct gen_device_info *devinfo, const brw_inst *inst)
{
if (devinfo->gen < 8)
if (devinfo->ver < 8)
return false;
if (inst_is_send(devinfo, inst))
@ -699,7 +699,7 @@ general_restrictions_based_on_operand_types(const struct gen_device_info *devinf
if (inst_is_send(devinfo, inst))
return error_msg;
if (devinfo->gen >= 11) {
if (devinfo->ver >= 11) {
if (num_sources == 3) {
ERROR_IF(brw_reg_type_to_size(brw_inst_3src_a1_src1_type(devinfo, inst)) == 1 ||
brw_reg_type_to_size(brw_inst_3src_a1_src2_type(devinfo, inst)) == 1,
@ -759,7 +759,7 @@ general_restrictions_based_on_operand_types(const struct gen_device_info *devinf
* 32-bit elements, so they are doubled. For evaluating the validity of an
* instruction, we halve them.
*/
if (devinfo->gen == 7 && !devinfo->is_haswell &&
if (devinfo->ver == 7 && !devinfo->is_haswell &&
exec_type_size == 8 && dst_type_size == 4)
dst_type_size = 8;
@ -859,7 +859,7 @@ general_restrictions_based_on_operand_types(const struct gen_device_info *devinf
ERROR_IF(subreg % 4 != 0,
"Conversions between integer and half-float must be "
"aligned to a DWord on the destination");
} else if ((devinfo->is_cherryview || devinfo->gen >= 9) &&
} else if ((devinfo->is_cherryview || devinfo->ver >= 9) &&
dst_type == BRW_REGISTER_TYPE_HF) {
unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
ERROR_IF(dst_stride != 2 &&
@ -878,7 +878,7 @@ general_restrictions_based_on_operand_types(const struct gen_device_info *devinf
*/
bool validate_dst_size_and_exec_size_ratio =
!is_mixed_float(devinfo, inst) ||
!(devinfo->is_cherryview || devinfo->gen >= 9);
!(devinfo->is_cherryview || devinfo->ver >= 9);
if (validate_dst_size_and_exec_size_ratio &&
exec_type_size > dst_type_size) {
@ -897,7 +897,7 @@ general_restrictions_based_on_operand_types(const struct gen_device_info *devinf
* Implementation Restriction: The relaxed alignment rule for byte
* destination (#10.5) is not supported.
*/
if ((devinfo->gen > 4 || devinfo->is_g4x) && dst_type_is_byte) {
if ((devinfo->ver > 4 || devinfo->is_g4x) && dst_type_is_byte) {
ERROR_IF(subreg % exec_type_size != 0 &&
subreg % exec_type_size != 1,
"Destination subreg must be aligned to the size of the "
@ -943,7 +943,7 @@ general_restrictions_on_region_parameters(const struct gen_device_info *devinfo,
"Destination Horizontal Stride must be 1");
if (num_sources >= 1) {
if (devinfo->is_haswell || devinfo->gen >= 8) {
if (devinfo->is_haswell || devinfo->ver >= 8) {
ERROR_IF(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 &&
@ -958,7 +958,7 @@ general_restrictions_on_region_parameters(const struct gen_device_info *devinfo,
}
if (num_sources == 2) {
if (devinfo->is_haswell || devinfo->gen >= 8) {
if (devinfo->is_haswell || devinfo->ver >= 8) {
ERROR_IF(brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 &&
@ -1002,7 +1002,7 @@ general_restrictions_on_region_parameters(const struct gen_device_info *devinfo,
* 32-bit elements, so they are doubled. For evaluating the validity of an
* instruction, we halve them.
*/
if (devinfo->gen == 7 && !devinfo->is_haswell &&
if (devinfo->ver == 7 && !devinfo->is_haswell &&
element_size == 8)
element_size = 4;
@ -1444,7 +1444,7 @@ region_alignment_rules(const struct gen_device_info *devinfo,
* 32-bit elements, so they are doubled. For evaluating the validity of an
* instruction, we halve them.
*/
if (devinfo->gen == 7 && !devinfo->is_haswell &&
if (devinfo->ver == 7 && !devinfo->is_haswell &&
element_size == 8)
element_size = 4;
@ -1471,7 +1471,7 @@ region_alignment_rules(const struct gen_device_info *devinfo,
* 3. The destination elements are evenly split between the two OWords
* of a register.
*/
if (devinfo->gen <= 8) {
if (devinfo->ver <= 8) {
if (dst_regs == 1 && (src0_regs == 2 || src1_regs == 2)) {
unsigned upper_oword_writes = 0, lower_oword_writes = 0;
@ -1515,7 +1515,7 @@ region_alignment_rules(const struct gen_device_info *devinfo,
* It is not known whether this restriction applies to KBL other Gens after
* SKL.
*/
if (devinfo->gen <= 8 ||
if (devinfo->ver <= 8 ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MATH) {
/* Nothing explicitly states that on Gen < 8 elements must be evenly
@ -1571,7 +1571,7 @@ region_alignment_rules(const struct gen_device_info *devinfo,
* It is impossible to violate rule (1) without violating (2) or (3), so we
* do not attempt to validate it.
*/
if (devinfo->gen <= 7 && dst_regs == 2) {
if (devinfo->ver <= 7 && dst_regs == 2) {
for (unsigned i = 0; i < num_sources; i++) {
#define DO_SRC(n) \
if (src ## n ## _regs <= 1) \
@ -1636,7 +1636,7 @@ region_alignment_rules(const struct gen_device_info *devinfo,
* Additionally the simulator source code indicates that the real condition
* is that the size of the destination type is 4 bytes.
*/
if (devinfo->gen <= 7 && dst_regs == 2) {
if (devinfo->ver <= 7 && dst_regs == 2) {
enum brw_reg_type dst_type = inst_dst_type(devinfo, inst);
bool dst_is_packed_dword =
is_packed(exec_size * stride, exec_size, stride) &&
@ -1760,7 +1760,7 @@ special_requirements_for_handling_double_precision_data_types(
unsigned dst_address_mode = brw_inst_dst_address_mode(devinfo, inst);
bool is_integer_dword_multiply =
devinfo->gen >= 8 &&
devinfo->ver >= 8 &&
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MUL &&
(brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_D ||
brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_UD) &&
@ -1875,7 +1875,7 @@ special_requirements_for_handling_double_precision_data_types(
*
* We assume that the restriction applies to all Gen8+ parts.
*/
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
enum brw_reg_type src1_type =
num_sources > 1 ? brw_inst_src1_type(devinfo, inst) : src0_type;
@ -1917,7 +1917,7 @@ instruction_restrictions(const struct gen_device_info *devinfo,
* "When multiplying a DW and any lower precision integer, source modifier
* is not supported."
*/
if (devinfo->gen >= 12 &&
if (devinfo->ver >= 12 &&
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MUL) {
enum brw_reg_type exec_type = execution_type(devinfo, inst);
const bool src0_valid = type_sz(brw_inst_src0_type(devinfo, inst)) == 4 ||
@ -1937,7 +1937,7 @@ instruction_restrictions(const struct gen_device_info *devinfo,
if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_CMP ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_CMPN) {
if (devinfo->gen <= 7) {
if (devinfo->ver <= 7) {
/* Page 166 of the Ivy Bridge PRM Volume 4 part 3 (Execution Unit
* ISA) says:
*
@ -1965,7 +1965,7 @@ instruction_restrictions(const struct gen_device_info *devinfo,
*
* Page 77 of the Haswell PRM Volume 2b contains the same text.
*/
if (devinfo->gen == 7) {
if (devinfo->ver == 7) {
ERROR_IF(dst_is_null(devinfo, inst) &&
brw_inst_thread_control(devinfo, inst) != BRW_THREAD_SWITCH,
"If the destination is the null register, the {Switch} "

246
src/intel/compiler/brw_fs.cpp
View file

@ -433,7 +433,7 @@ fs_inst::has_source_and_destination_hazard() const
bool
fs_inst::can_do_source_mods(const struct gen_device_info *devinfo) const
{
if (devinfo->gen == 6 && is_math())
if (devinfo->ver == 6 && is_math())
return false;
if (is_send_from_grf())
@ -444,7 +444,7 @@ fs_inst::can_do_source_mods(const struct gen_device_info *devinfo) const
* "When multiplying a DW and any lower precision integer, source modifier
* is not supported."
*/
if (devinfo->gen >= 12 && (opcode == BRW_OPCODE_MUL ||
if (devinfo->ver >= 12 && (opcode == BRW_OPCODE_MUL ||
opcode == BRW_OPCODE_MAD)) {
const brw_reg_type exec_type = get_exec_type(this);
const unsigned min_type_sz = opcode == BRW_OPCODE_MAD ?
@ -572,7 +572,7 @@ fs_reg::component_size(unsigned width) const
fs_reg
fs_visitor::get_timestamp(const fs_builder &bld)
{
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
fs_reg ts = fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_TIMESTAMP,
@ -1099,7 +1099,7 @@ fs_inst::flags_read(const gen_device_info *devinfo) const
/* The vertical predication modes combine corresponding bits from
* f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
*/
const unsigned shift = devinfo->gen >= 7 ? 4 : 2;
const unsigned shift = devinfo->ver >= 7 ? 4 : 2;
return flag_mask(this, 1) << shift | flag_mask(this, 1);
} else if (predicate) {
return flag_mask(this, predicate_width(predicate));
@ -1240,7 +1240,7 @@ fs_visitor::emit_fragcoord_interpolation(fs_reg wpos)
wpos = offset(wpos, bld, 1);
/* gl_FragCoord.z */
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
bld.MOV(wpos, fetch_payload_reg(bld, payload.source_depth_reg));
} else {
bld.emit(FS_OPCODE_LINTERP, wpos,
@ -1298,13 +1298,13 @@ fs_visitor::emit_frontfacing_interpolation()
{
fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::bool_type));
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
fs_reg g1 = fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W));
fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_W);
bld.ASR(tmp, g1, brw_imm_d(15));
bld.NOT(*reg, tmp);
} else if (devinfo->gen >= 6) {
} else if (devinfo->ver >= 6) {
/* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
* a boolean result from this (~0/true or 0/false).
*
@ -1366,7 +1366,7 @@ fs_visitor::compute_sample_position(fs_reg dst, fs_reg int_sample_pos)
fs_reg *
fs_visitor::emit_samplepos_setup()
{
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
const fs_builder abld = bld.annotate("compute sample position");
fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::vec2_type));
@ -1403,7 +1403,7 @@ fs_visitor::emit_sampleid_setup()
{
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
const fs_builder abld = bld.annotate("compute sample id");
fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::uint_type));
@ -1414,7 +1414,7 @@ fs_visitor::emit_sampleid_setup()
* rasterization is disabled, gl_SampleID will always be zero."
*/
abld.MOV(*reg, brw_imm_d(0));
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
/* Sample ID comes in as 4-bit numbers in g1.0:
*
* 15:12 Slot 3 SampleID (only used in SIMD16)
@ -1492,7 +1492,7 @@ fs_visitor::emit_sampleid_setup()
* FINISHME: One day, we could come up with a way to do this that
* actually works on gen7.
*/
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
abld.exec_all().group(8, 0).MOV(t2, brw_imm_v(0x32103210));
@ -1510,7 +1510,7 @@ fs_visitor::emit_samplemaskin_setup()
{
assert(stage == MESA_SHADER_FRAGMENT);
struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data);
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::int_type));
@ -1801,7 +1801,7 @@ calculate_urb_setup(const struct gen_device_info *devinfo,
int urb_next = 0;
/* Figure out where each of the incoming setup attributes lands. */
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
if (util_bitcount64(nir->info.inputs_read &
BRW_FS_VARYING_INPUT_MASK) <= 16) {
/* The SF/SBE pipeline stage can do arbitrary rearrangement of the
@ -2987,7 +2987,7 @@ fs_visitor::opt_zero_samples()
/* Gen4 infers the texturing opcode based on the message length so we can't
* change it.
*/
if (devinfo->gen < 5)
if (devinfo->ver < 5)
return false;
bool progress = false;
@ -3162,7 +3162,7 @@ fs_visitor::compute_to_mrf()
int next_ip = 0;
/* No MRFs on Gen >= 7. */
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
return false;
const fs_live_variables &live = live_analysis.require();
@ -3220,7 +3220,7 @@ fs_visitor::compute_to_mrf()
if (scan_inst->mlen)
break;
if (devinfo->gen == 6) {
if (devinfo->ver == 6) {
/* gen6 math instructions must have the destination be
* GRF, so no compute-to-MRF for them.
*/
@ -3471,7 +3471,7 @@ fs_visitor::emit_repclear_shader()
bool
fs_visitor::remove_duplicate_mrf_writes()
{
fs_inst *last_mrf_move[BRW_MAX_MRF(devinfo->gen)];
fs_inst *last_mrf_move[BRW_MAX_MRF(devinfo->ver)];
bool progress = false;
/* Need to update the MRF tracking for compressed instructions. */
@ -3631,7 +3631,7 @@ fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
{
int write_len = regs_written(inst);
int first_write_grf = inst->dst.nr;
bool needs_dep[BRW_MAX_MRF(devinfo->gen)];
bool needs_dep[BRW_MAX_MRF(devinfo->ver)];
assert(write_len < (int)sizeof(needs_dep) - 1);
memset(needs_dep, false, sizeof(needs_dep));
@ -3702,7 +3702,7 @@ fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t *block, fs_ins
{
int write_len = regs_written(inst);
unsigned first_write_grf = inst->dst.nr;
bool needs_dep[BRW_MAX_MRF(devinfo->gen)];
bool needs_dep[BRW_MAX_MRF(devinfo->ver)];
assert(write_len < (int)sizeof(needs_dep) - 1);
memset(needs_dep, false, sizeof(needs_dep));
@ -3750,7 +3750,7 @@ fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t *block, fs_ins
void
fs_visitor::insert_gen4_send_dependency_workarounds()
{
if (devinfo->gen != 4 || devinfo->is_g4x)
if (devinfo->ver != 4 || devinfo->is_g4x)
return;
bool progress = false;
@ -3790,7 +3790,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD)
continue;
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
const fs_builder ubld = fs_builder(this, block, inst).exec_all();
const fs_reg payload = ubld.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD);
@ -3811,7 +3811,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
* else does except for register spill/unspill, which generates and
* uses its MRF within a single IR instruction.
*/
inst->base_mrf = FIRST_PULL_LOAD_MRF(devinfo->gen) + 1;
inst->base_mrf = FIRST_PULL_LOAD_MRF(devinfo->ver) + 1;
inst->mlen = 1;
}
}
@ -3943,7 +3943,7 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block)
* If multiplying by an immediate value that fits in 16-bits, do a
* single MUL instruction with that value in the proper location.
*/
if (devinfo->gen < 7) {
if (devinfo->ver < 7) {
fs_reg imm(VGRF, alloc.allocate(dispatch_width / 8), inst->dst.type);
ibld.MOV(imm, inst->src[1]);
ibld.MUL(inst->dst, imm, inst->src[0]);
@ -4023,7 +4023,7 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block)
high.stride = inst->dst.stride;
high.offset = inst->dst.offset % REG_SIZE;
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
/* From GEN:BUG:1604601757:
*
* "When multiplying a DW and any lower precision integer, source modifier
@ -4034,7 +4034,7 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block)
* pass would spawn another dword multiply. Instead, lower the
* modifier first.
*/
const bool source_mods_unsupported = (devinfo->gen >= 12);
const bool source_mods_unsupported = (devinfo->ver >= 12);
if (inst->src[1].abs || (inst->src[1].negate &&
source_mods_unsupported))
@ -4147,7 +4147,7 @@ fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block)
* mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
* mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
*/
if (devinfo->gen >= 8 && (inst->src[1].negate || inst->src[1].abs))
if (devinfo->ver >= 8 && (inst->src[1].negate || inst->src[1].abs))
lower_src_modifiers(this, block, inst, 1);
/* Should have been lowered to 8-wide. */
@ -4156,7 +4156,7 @@ fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block)
fs_inst *mul = ibld.MUL(acc, inst->src[0], inst->src[1]);
fs_inst *mach = ibld.MACH(inst->dst, inst->src[0], inst->src[1]);
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
/* Until Gen8, integer multiplies read 32-bits from one source,
* and 16-bits from the other, and relying on the MACH instruction
* to generate the high bits of the result.
@ -4173,7 +4173,7 @@ fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block)
if (mul->src[1].file == IMM) {
mul->src[1] = brw_imm_uw(mul->src[1].ud);
}
} else if (devinfo->gen == 7 && !devinfo->is_haswell &&
} else if (devinfo->ver == 7 && !devinfo->is_haswell &&
inst->group > 0) {
/* Among other things the quarter control bits influence which
* accumulator register is used by the hardware for instructions
@ -4208,7 +4208,7 @@ fs_visitor::lower_integer_multiplication()
/* If the instruction is already in a form that does not need lowering,
* return early.
*/
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
if (type_sz(inst->src[1].type) < 4 && type_sz(inst->src[0].type) <= 4)
continue;
} else {
@ -4250,7 +4250,7 @@ fs_visitor::lower_integer_multiplication()
bool
fs_visitor::lower_minmax()
{
assert(devinfo->gen < 6);
assert(devinfo->ver < 6);
bool progress = false;
@ -4391,7 +4391,7 @@ sample_mask_reg(const fs_builder &bld)
assert(bld.dispatch_width() <= 16);
return brw_flag_subreg(sample_mask_flag_subreg(v) + bld.group() / 16);
} else {
assert(v->devinfo->gen >= 6 && bld.dispatch_width() <= 16);
assert(v->devinfo->ver >= 6 && bld.dispatch_width() <= 16);
return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7),
BRW_REGISTER_TYPE_UW);
}
@ -4475,7 +4475,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
int header_size = 2, payload_header_size;
unsigned length = 0;
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
/* TODO: Support SIMD32 on gen4-5 */
assert(bld.group() < 16);
@ -4499,9 +4499,9 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
assert(length == 0);
length = 2;
} else if ((devinfo->gen <= 7 && !devinfo->is_haswell &&
} else if ((devinfo->ver <= 7 && !devinfo->is_haswell &&
prog_data->uses_kill) ||
(devinfo->gen < 11 &&
(devinfo->ver < 11 &&
(color1.file != BAD_FILE || key->nr_color_regions > 1))) {
/* From the Sandy Bridge PRM, volume 4, page 198:
*
@ -4527,7 +4527,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
ubld.LOAD_PAYLOAD(header, header_sources, 2, 0);
/* Gen12 will require additional fix-ups if we ever hit this path. */
assert(devinfo->gen < 12);
assert(devinfo->ver < 12);
}
uint32_t g00_bits = 0;
@ -4631,7 +4631,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
}
if (src_stencil.file != BAD_FILE) {
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
assert(bld.dispatch_width() == 8);
/* XXX: src_stencil is only available on gen9+. dst_depth is never
@ -4648,7 +4648,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
}
fs_inst *load;
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
/* Send from the GRF */
fs_reg payload = fs_reg(VGRF, -1, BRW_REGISTER_TYPE_F);
load = bld.LOAD_PAYLOAD(payload, sources, length, payload_header_size);
@ -4664,7 +4664,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
inst->last_rt, false);
uint32_t ex_desc = 0;
if (devinfo->gen >= 11) {
if (devinfo->ver >= 11) {
/* Set the "Render Target Index" and "Src0 Alpha Present" fields
* in the extended message descriptor, in lieu of using a header.
*/
@ -4694,10 +4694,10 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
/* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
* will do this for us if we just give it a COMPR4 destination.
*/
if (devinfo->gen < 6 && bld.dispatch_width() == 16)
if (devinfo->ver < 6 && bld.dispatch_width() == 16)
load->dst.nr |= BRW_MRF_COMPR4;
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
/* Set up src[0] for the implied MOV from grf0-1 */
inst->resize_sources(1);
inst->src[0] = brw_vec8_grf(0, 0);
@ -4730,7 +4730,7 @@ lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst)
};
ubld.LOAD_PAYLOAD(header, header_sources, ARRAY_SIZE(header_sources), 0);
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
/* On Gen12 the Viewport and Render Target Array Index fields (AKA
* Poly 0 Info) are provided in r1.1 instead of r0.0, and the render
* target message header format was updated accordingly -- However
@ -4958,7 +4958,7 @@ lower_sampler_logical_send_gen5(const fs_builder &bld, fs_inst *inst, opcode op,
static bool
is_high_sampler(const struct gen_device_info *devinfo, const fs_reg &sampler)
{
if (devinfo->gen < 8 && !devinfo->is_haswell)
if (devinfo->ver < 8 && !devinfo->is_haswell)
return false;
return sampler.file != IMM || sampler.ud >= 16;
@ -4968,7 +4968,7 @@ static unsigned
sampler_msg_type(const gen_device_info *devinfo,
opcode opcode, bool shadow_compare)
{
assert(devinfo->gen >= 5);
assert(devinfo->ver >= 5);
switch (opcode) {
case SHADER_OPCODE_TEX:
return shadow_compare ? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE :
@ -4986,35 +4986,35 @@ sampler_msg_type(const gen_device_info *devinfo,
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
case SHADER_OPCODE_TXD:
assert(!shadow_compare || devinfo->gen >= 8 || devinfo->is_haswell);
assert(!shadow_compare || devinfo->ver >= 8 || devinfo->is_haswell);
return shadow_compare ? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE :
GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
case SHADER_OPCODE_TXF:
return GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
case SHADER_OPCODE_TXF_LZ:
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ;
case SHADER_OPCODE_TXF_CMS_W:
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
case SHADER_OPCODE_TXF_CMS:
return devinfo->gen >= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS :
return devinfo->ver >= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS :
GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
case SHADER_OPCODE_TXF_UMS:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
case SHADER_OPCODE_TXF_MCS:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
case SHADER_OPCODE_LOD:
return GEN5_SAMPLER_MESSAGE_LOD;
case SHADER_OPCODE_TG4:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
return shadow_compare ? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C :
GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
break;
case SHADER_OPCODE_TG4_OFFSET:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
return shadow_compare ? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C :
GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
case SHADER_OPCODE_SAMPLEINFO:
@ -5116,7 +5116,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
/* Gen11+ sampler message headers include bits in 4:0 which conflict
* with the ones included in g0.3 bits 4:0. Mask them out.
*/
if (devinfo->gen >= 11) {
if (devinfo->ver >= 11) {
sampler_state_ptr = ubld1.vgrf(BRW_REGISTER_TYPE_UD);
ubld1.AND(sampler_state_ptr,
retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
@ -5135,7 +5135,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
ubld1.SHL(tmp, tmp, brw_imm_ud(4));
ubld1.ADD(component(header, 3), sampler_state_ptr, tmp);
}
} else if (devinfo->gen >= 11) {
} else if (devinfo->ver >= 11) {
/* Gen11+ sampler message headers include bits in 4:0 which conflict
* with the ones included in g0.3 bits 4:0. Mask them out.
*/
@ -5156,7 +5156,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
switch (op) {
case FS_OPCODE_TXB:
case SHADER_OPCODE_TXL:
if (devinfo->gen >= 9 && op == SHADER_OPCODE_TXL && lod.is_zero()) {
if (devinfo->ver >= 9 && op == SHADER_OPCODE_TXL && lod.is_zero()) {
op = SHADER_OPCODE_TXL_LZ;
break;
}
@ -5199,7 +5199,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
*/
bld.MOV(retype(sources[length++], BRW_REGISTER_TYPE_D), coordinate);
if (devinfo->gen >= 9) {
if (devinfo->ver >= 9) {
if (coord_components >= 2) {
bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_D),
offset(coordinate, bld, 1));
@ -5209,14 +5209,14 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
length++;
}
if (devinfo->gen >= 9 && lod.is_zero()) {
if (devinfo->ver >= 9 && lod.is_zero()) {
op = SHADER_OPCODE_TXF_LZ;
} else {
bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_D), lod);
length++;
}
for (unsigned i = devinfo->gen >= 9 ? 2 : 1; i < coord_components; i++)
for (unsigned i = devinfo->ver >= 9 ? 2 : 1; i < coord_components; i++)
bld.MOV(retype(sources[length++], BRW_REGISTER_TYPE_D),
offset(coordinate, bld, i));
@ -5341,7 +5341,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
inst->src[1] = brw_imm_ud(0); /* ex_desc */
} else if (surface_handle.file != BAD_FILE) {
/* Bindless surface */
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
inst->desc = brw_sampler_desc(devinfo,
GEN9_BTI_BINDLESS,
sampler.file == IMM ? sampler.ud % 16 : 0,
@ -5434,7 +5434,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
assert(inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM);
const unsigned grad_components = inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].ud;
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
lower_sampler_logical_send_gen7(bld, inst, op, coordinate,
shadow_c, lod, lod2, min_lod,
sample_index,
@ -5442,7 +5442,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
surface_handle, sampler_handle,
tg4_offset,
coord_components, grad_components);
} else if (devinfo->gen >= 5) {
} else if (devinfo->ver >= 5) {
lower_sampler_logical_send_gen5(bld, inst, op, coordinate,
shadow_c, lod, lod2, sample_index,
surface, sampler,
@ -5509,7 +5509,7 @@ setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc,
inst->src[1] = brw_imm_ud(0); /* ex_desc */
} else if (surface_handle.file != BAD_FILE) {
/* Bindless surface */
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
inst->desc = desc | GEN9_BTI_BINDLESS;
inst->src[0] = brw_imm_ud(0);
@ -5580,7 +5580,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
* For all stateless A32 messages, we also need a header
*/
fs_reg header;
if ((devinfo->gen < 9 && is_typed_access) || is_stateless) {
if ((devinfo->ver < 9 && is_typed_access) || is_stateless) {
fs_builder ubld = bld.exec_all().group(8, 0);
header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
if (is_stateless) {
@ -5596,7 +5596,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
fs_reg payload, payload2;
unsigned mlen, ex_mlen = 0;
if (devinfo->gen >= 9 &&
if (devinfo->ver >= 9 &&
(src.file == BAD_FILE || header.file == BAD_FILE)) {
/* We have split sends on gen9 and above */
if (header.file == BAD_FILE) {
@ -5651,8 +5651,8 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
sfid = devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
sfid = devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
BRW_DATAPORT_READ_TARGET_RENDER_CACHE;
break;
@ -5663,7 +5663,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
/* Untyped Surface messages go through the data cache but the SFID value
* changed on Haswell.
*/
sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
break;
@ -5674,7 +5674,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
/* Typed surface messages go through the render cache on IVB and the
* data cache on HSW+.
*/
sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN6_SFID_DATAPORT_RENDER_CACHE);
break;
@ -5778,7 +5778,7 @@ static void
lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst)
{
const gen_device_info *devinfo = bld.shader->devinfo;
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
/* Get the logical send arguments. */
const fs_reg &addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS];
@ -5883,7 +5883,7 @@ lower_a64_logical_send(const fs_builder &bld, fs_inst *inst)
if (inst->opcode == SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL ||
inst->opcode == SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL ||
inst->opcode == SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL) {
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
/* OWORD messages only take a scalar address in a header */
mlen = 1;
@ -5895,7 +5895,7 @@ lower_a64_logical_send(const fs_builder &bld, fs_inst *inst)
payload2 = retype(bld.move_to_vgrf(src, src_comps),
BRW_REGISTER_TYPE_UD);
}
} else if (devinfo->gen >= 9) {
} else if (devinfo->ver >= 9) {
/* On Skylake and above, we have SENDS */
mlen = 2 * (inst->exec_size / 8);
ex_mlen = src_comps * type_sz(src.type) * inst->exec_size / REG_SIZE;
@ -6025,7 +6025,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
const gen_device_info *devinfo = bld.shader->devinfo;
const brw_compiler *compiler = bld.shader->compiler;
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
fs_reg index = inst->src[0];
/* We are switching the instruction from an ALU-like instruction to a
* send-from-grf instruction. Since sends can't handle strides or
@ -6064,7 +6064,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
simd_mode, 0);
} else if (alignment >= 4) {
inst->sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
inst->sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
inst->desc |= brw_dp_untyped_surface_rw_desc(devinfo, inst->exec_size,
@ -6098,7 +6098,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
}
}
} else {
const fs_reg payload(MRF, FIRST_PULL_LOAD_MRF(devinfo->gen),
const fs_reg payload(MRF, FIRST_PULL_LOAD_MRF(devinfo->ver),
BRW_REGISTER_TYPE_UD);
bld.MOV(byte_offset(payload, REG_SIZE), inst->src[1]);
@ -6114,7 +6114,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
static void
lower_math_logical_send(const fs_builder &bld, fs_inst *inst)
{
assert(bld.shader->devinfo->gen < 6);
assert(bld.shader->devinfo->ver < 6);
inst->base_mrf = 2;
inst->mlen = inst->sources * inst->exec_size / 8;
@ -6397,7 +6397,7 @@ fs_visitor::lower_logical_sends()
* logical instructions (which we can easily recognize because they
* have mlen = 0) into send-like virtual instructions.
*/
if (devinfo->gen < 6 && inst->mlen == 0) {
if (devinfo->ver < 6 && inst->mlen == 0) {
lower_math_logical_send(ibld, inst);
break;
@ -6525,7 +6525,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
* destination type is integer because empirically the hardware doesn't
* seem to care what the actual type is as long as it's dword-aligned.
*/
if (devinfo->gen < 8) {
if (devinfo->ver < 8) {
for (unsigned i = 0; i < inst->sources; i++) {
/* IVB implements DF scalars as <0;2,1> regions. */
const bool is_scalar_exception = is_uniform(inst->src[i]) &&
@ -6549,7 +6549,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
}
}
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
/* From the G45 PRM, Volume 4 Page 361:
*
* "Operand Alignment Rule: With the exceptions listed below, a
@ -6577,7 +6577,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
* There is similar text in the HSW PRMs. Gen4-6 don't even implement
* 32-wide control flow support in hardware and will behave similarly.
*/
if (devinfo->gen < 8 && !inst->force_writemask_all)
if (devinfo->ver < 8 && !inst->force_writemask_all)
max_width = MIN2(max_width, 16);
/* From the IVB PRMs (applies to HSW too):
@ -6586,7 +6586,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
* From the BDW PRMs (applies to later hardware too):
* "Ternary instruction with condition modifiers must not use SIMD32."
*/
if (inst->conditional_mod && (devinfo->gen < 8 || inst->is_3src(devinfo)))
if (inst->conditional_mod && (devinfo->ver < 8 || inst->is_3src(devinfo)))
max_width = MIN2(max_width, 16);
/* From the IVB PRMs (applies to other devices that don't have the
@ -6609,7 +6609,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
* In this situation we calculate the maximum size of the split
* instructions so they only ever write to a single register.
*/
if (devinfo->gen < 8 && inst->size_written > REG_SIZE &&
if (devinfo->ver < 8 && inst->size_written > REG_SIZE &&
!inst->force_writemask_all) {
const unsigned channels_per_grf = inst->exec_size /
DIV_ROUND_UP(inst->size_written, REG_SIZE);
@ -6627,7 +6627,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
* the compressed instruction which will be just wrong under
* non-uniform control flow.
*/
if (devinfo->gen == 7 && !devinfo->is_haswell &&
if (devinfo->ver == 7 && !devinfo->is_haswell &&
(exec_type_size == 8 || type_sz(inst->dst.type) == 8))
max_width = MIN2(max_width, 4);
}
@ -6700,16 +6700,16 @@ get_sampler_lowered_simd_width(const struct gen_device_info *devinfo,
* pre-ILK we need to pad to at most three components.
*/
const unsigned req_coord_components =
(devinfo->gen >= 7 ||
(devinfo->ver >= 7 ||
!inst->components_read(TEX_LOGICAL_SRC_COORDINATE)) ? 0 :
(devinfo->gen >= 5 && inst->opcode != SHADER_OPCODE_TXF_LOGICAL &&
(devinfo->ver >= 5 && inst->opcode != SHADER_OPCODE_TXF_LOGICAL &&
inst->opcode != SHADER_OPCODE_TXF_CMS_LOGICAL) ? 4 :
3;
/* On Gen9+ the LOD argument is for free if we're able to use the LZ
* variant of the TXL or TXF message.
*/
const bool implicit_lod = devinfo->gen >= 9 &&
const bool implicit_lod = devinfo->ver >= 9 &&
(inst->opcode == SHADER_OPCODE_TXL ||
inst->opcode == SHADER_OPCODE_TXF) &&
inst->src[TEX_LOGICAL_SRC_LOD].is_zero();
@ -6797,7 +6797,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
* coissuing would affect CMP instructions not otherwise affected by
* the errata.
*/
const unsigned max_width = (devinfo->gen == 7 && !devinfo->is_haswell &&
const unsigned max_width = (devinfo->ver == 7 && !devinfo->is_haswell &&
!inst->dst.is_null() ? 8 : ~0);
return MIN2(max_width, get_fpu_lowered_simd_width(devinfo, inst));
}
@ -6824,7 +6824,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
/* Unary extended math instructions are limited to SIMD8 on Gen4 and
* Gen6. Extended Math Function is limited to SIMD8 with half-float.
*/
if (devinfo->gen == 6 || (devinfo->gen == 4 && !devinfo->is_g4x))
if (devinfo->ver == 6 || (devinfo->ver == 4 && !devinfo->is_g4x))
return MIN2(8, inst->exec_size);
if (inst->dst.type == BRW_REGISTER_TYPE_HF)
return MIN2(8, inst->exec_size);
@ -6835,7 +6835,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
/* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
* to SIMD8 with half-float
*/
if (devinfo->gen < 7)
if (devinfo->ver < 7)
return MIN2(8, inst->exec_size);
if (inst->dst.type == BRW_REGISTER_TYPE_HF)
return MIN2(8, inst->exec_size);
@ -6867,7 +6867,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
* shorter return payload would be to use the SIMD8 sampler message that
* takes (header, u, v, r) as parameters instead of (header, u).
*/
return (devinfo->gen == 4 ? 16 : MIN2(16, inst->exec_size));
return (devinfo->ver == 4 ? 16 : MIN2(16, inst->exec_size));
case FS_OPCODE_DDX_COARSE:
case FS_OPCODE_DDX_FINE:
@ -6897,22 +6897,22 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
* Empirically, compressed align16 instructions using odd register
* numbers don't appear to work on Sandybridge either.
*/
return (devinfo->gen == 4 || devinfo->gen == 6 ||
(devinfo->gen == 7 && !devinfo->is_haswell) ?
return (devinfo->ver == 4 || devinfo->ver == 6 ||
(devinfo->ver == 7 && !devinfo->is_haswell) ?
MIN2(8, inst->exec_size) : MIN2(16, inst->exec_size));
case SHADER_OPCODE_MULH:
/* MULH is lowered to the MUL/MACH sequence using the accumulator, which
* is 8-wide on Gen7+.
*/
return (devinfo->gen >= 7 ? 8 :
return (devinfo->ver >= 7 ? 8 :
get_fpu_lowered_simd_width(devinfo, inst));
case FS_OPCODE_FB_WRITE_LOGICAL:
/* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
* here.
*/
assert(devinfo->gen != 6 ||
assert(devinfo->ver != 6 ||
inst->src[FB_WRITE_LOGICAL_SRC_SRC_DEPTH].file == BAD_FILE ||
inst->exec_size == 8);
/* Dual-source FB writes are unsupported in SIMD16 mode. */
@ -6942,7 +6942,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
/* Only one execution size is representable pre-ILK depending on whether
* the shadow reference argument is present.
*/
if (devinfo->gen == 4)
if (devinfo->ver == 4)
return inst->src[TEX_LOGICAL_SRC_SHADOW_C].file == BAD_FILE ? 16 : 8;
else
return get_sampler_lowered_simd_width(devinfo, inst);
@ -6952,7 +6952,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
/* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
* messages. Use SIMD16 instead.
*/
if (devinfo->gen == 4)
if (devinfo->ver == 4)
return 16;
else
return get_sampler_lowered_simd_width(devinfo, inst);
@ -6976,7 +6976,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
return devinfo->gen <= 8 ? 8 : MIN2(16, inst->exec_size);
return devinfo->ver <= 8 ? 8 : MIN2(16, inst->exec_size);
case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL:
case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
@ -7003,7 +7003,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
const unsigned swiz = inst->src[1].ud;
return (is_uniform(inst->src[0]) ?
get_fpu_lowered_simd_width(devinfo, inst) :
devinfo->gen < 11 && type_sz(inst->src[0].type) == 4 ? 8 :
devinfo->ver < 11 && type_sz(inst->src[0].type) == 4 ? 8 :
swiz == BRW_SWIZZLE_XYXY || swiz == BRW_SWIZZLE_ZWZW ? 4 :
get_fpu_lowered_simd_width(devinfo, inst));
}
@ -7017,9 +7017,9 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
* the EU decompression logic not handling VxH indirect addressing
* correctly.
*/
const unsigned max_size = (devinfo->gen >= 8 ? 2 : 1) * REG_SIZE;
const unsigned max_size = (devinfo->ver >= 8 ? 2 : 1) * REG_SIZE;
/* Prior to Broadwell, we only have 8 address subregisters. */
return MIN3(devinfo->gen >= 8 ? 16 : 8,
return MIN3(devinfo->ver >= 8 ? 16 : 8,
max_size / (inst->dst.stride * type_sz(inst->dst.type)),
inst->exec_size);
}
@ -7340,7 +7340,7 @@ fs_visitor::lower_simd_width()
bool
fs_visitor::lower_barycentrics()
{
const bool has_interleaved_layout = devinfo->has_pln || devinfo->gen >= 7;
const bool has_interleaved_layout = devinfo->has_pln || devinfo->ver >= 7;
bool progress = false;
if (stage != MESA_SHADER_FRAGMENT || !has_interleaved_layout)
@ -7465,7 +7465,7 @@ fs_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) con
if (inst->conditional_mod) {
fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
if (!inst->predicate &&
(devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
(devinfo->ver < 5 || (inst->opcode != BRW_OPCODE_SEL &&
inst->opcode != BRW_OPCODE_CSEL &&
inst->opcode != BRW_OPCODE_IF &&
inst->opcode != BRW_OPCODE_WHILE))) {
@ -7675,7 +7675,7 @@ fs_visitor::setup_fs_payload_gen6()
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
const unsigned payload_width = MIN2(16, dispatch_width);
assert(dispatch_width % payload_width == 0);
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
/* R0: PS thread payload header. */
payload.num_regs++;
@ -7720,7 +7720,7 @@ fs_visitor::setup_fs_payload_gen6()
/* R32-33: MSAA input coverage mask */
if (prog_data->uses_sample_mask) {
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
payload.sample_mask_in_reg[j] = payload.num_regs;
payload.num_regs += payload_width / 8;
}
@ -7784,7 +7784,7 @@ fs_visitor::setup_gs_payload()
void
fs_visitor::setup_cs_payload()
{
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
/* TODO: Fill out uses_btd_stack_ids automatically */
payload.num_regs = 1 + brw_cs_prog_data(prog_data)->uses_btd_stack_ids;
}
@ -7967,7 +7967,7 @@ fs_visitor::optimize()
}
OPT(lower_sub_sat);
if (devinfo->gen <= 5 && OPT(lower_minmax)) {
if (devinfo->ver <= 5 && OPT(lower_minmax)) {
OPT(opt_cmod_propagation);
OPT(opt_cse);
OPT(opt_copy_propagation);
@ -8090,7 +8090,7 @@ find_halt_control_flow_region_start(const fs_visitor *v)
bool
fs_visitor::fixup_nomask_control_flow()
{
if (devinfo->gen != 12)
if (devinfo->ver != 12)
return false;
const brw_predicate pred = dispatch_width > 16 ? BRW_PREDICATE_ALIGN1_ANY32H :
@ -8298,7 +8298,7 @@ fs_visitor::allocate_registers(bool allow_spilling)
* and platform.
*/
prog_data->total_scratch = MAX2(prog_data->total_scratch, 2048);
} else if (devinfo->gen <= 7) {
} else if (devinfo->ver <= 7) {
/* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
* field documentation, platforms prior to Haswell measure scratch
* size linearly with a range of [1kB, 12kB] and 1kB granularity.
@ -8364,9 +8364,9 @@ fs_visitor::set_tcs_invocation_id()
struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
const unsigned instance_id_mask =
devinfo->gen >= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
devinfo->ver >= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
const unsigned instance_id_shift =
devinfo->gen >= 11 ? 16 : 17;
devinfo->ver >= 11 ? 16 : 17;
/* Get instance number from g0.2 bits 22:16 or 23:17 */
fs_reg t = bld.vgrf(BRW_REGISTER_TYPE_UD);
@ -8596,7 +8596,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
assert(stage == MESA_SHADER_FRAGMENT);
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
setup_fs_payload_gen6();
else
setup_fs_payload_gen4();
@ -8613,7 +8613,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
if (nir->info.inputs_read > 0 ||
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
(nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) {
if (devinfo->gen < 6)
if (devinfo->ver < 6)
emit_interpolation_setup_gen4();
else
emit_interpolation_setup_gen6();
@ -8626,7 +8626,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
const unsigned lower_width = MIN2(dispatch_width, 16);
for (unsigned i = 0; i < dispatch_width / lower_width; i++) {
const fs_reg dispatch_mask =
devinfo->gen >= 6 ? brw_vec1_grf((i ? 2 : 1), 7) :
devinfo->ver >= 6 ? brw_vec1_grf((i ? 2 : 1), 7) :
brw_vec1_grf(0, 0);
bld.exec_all().group(1, 0)
.MOV(sample_mask_reg(bld.group(lower_width, i)),
@ -8656,7 +8656,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
assign_curb_setup();
if (devinfo->gen >= 9)
if (devinfo->ver >= 9)
gen9_ps_header_only_workaround(wm_prog_data);
assign_urb_setup();
@ -9013,7 +9013,7 @@ brw_nir_populate_wm_prog_data(const nir_shader *shader,
shader->info.fs.uses_sample_qualifier ||
shader->info.outputs_read);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
prog_data->uses_sample_mask =
BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
@ -9069,20 +9069,20 @@ brw_compile_fs(const struct brw_compiler *compiler,
prog_data->base.stage = MESA_SHADER_FRAGMENT;
const struct gen_device_info *devinfo = compiler->devinfo;
const unsigned max_subgroup_size = compiler->devinfo->gen >= 6 ? 32 : 16;
const unsigned max_subgroup_size = compiler->devinfo->ver >= 6 ? 32 : 16;
brw_nir_apply_key(nir, compiler, &key->base, max_subgroup_size, true);
brw_nir_lower_fs_inputs(nir, devinfo, key);
brw_nir_lower_fs_outputs(nir);
if (devinfo->gen < 6)
if (devinfo->ver < 6)
brw_setup_vue_interpolation(params->vue_map, nir, prog_data);
/* From the SKL PRM, Volume 7, "Alpha Coverage":
* "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
* hardware, regardless of the state setting for this feature."
*/
if (devinfo->gen > 6 && key->alpha_to_coverage) {
if (devinfo->ver > 6 && key->alpha_to_coverage) {
/* Run constant fold optimization in order to get the correct source
* offset to determine render target 0 store instruction in
* emit_alpha_to_coverage pass.
@ -9124,7 +9124,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
/* Limit dispatch width to simd8 with dual source blending on gen8.
* See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1917
*/
if (devinfo->gen == 8 && prog_data->dual_src_blend &&
if (devinfo->ver == 8 && prog_data->dual_src_blend &&
!(INTEL_DEBUG & DEBUG_NO8)) {
assert(!params->use_rep_send);
v8->limit_dispatch_width(8, "gen8 workaround: "
@ -9160,7 +9160,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
/* Currently, the compiler only supports SIMD32 on SNB+ */
if (!has_spilled &&
v8->max_dispatch_width >= 32 && !params->use_rep_send &&
devinfo->gen >= 6 && !simd16_failed &&
devinfo->ver >= 6 && !simd16_failed &&
!(INTEL_DEBUG & DEBUG_NO32)) {
/* Try a SIMD32 compile */
v32 = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
@ -9195,7 +9195,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
* Instead, we just give them exactly one shader and we pick the widest one
* available.
*/
if (compiler->devinfo->gen < 5) {
if (compiler->devinfo->ver < 5) {
if (simd32_cfg || simd16_cfg)
simd8_cfg = NULL;
if (simd32_cfg)
@ -9203,11 +9203,11 @@ brw_compile_fs(const struct brw_compiler *compiler,
}
/* If computed depth is enabled SNB only allows SIMD8. */
if (compiler->devinfo->gen == 6 &&
if (compiler->devinfo->ver == 6 &&
prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF)
assert(simd16_cfg == NULL && simd32_cfg == NULL);
if (compiler->devinfo->gen <= 5 && !simd8_cfg) {
if (compiler->devinfo->ver <= 5 && !simd8_cfg) {
/* Iron lake and earlier only have one Dispatch GRF start field. Make
* the data available in the base prog data struct for convenience.
*/
@ -9236,7 +9236,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
*/
if (simd32_cfg || simd16_cfg)
simd8_cfg = NULL;
if (simd32_cfg && devinfo->gen < 12)
if (simd32_cfg && devinfo->ver < 12)
simd16_cfg = NULL;
}
@ -9326,7 +9326,7 @@ cs_fill_push_const_info(const struct gen_device_info *devinfo,
{
const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
int subgroup_id_index = get_subgroup_id_param_index(devinfo, prog_data);
bool cross_thread_supported = devinfo->gen > 7 || devinfo->is_haswell;
bool cross_thread_supported = devinfo->ver > 7 || devinfo->is_haswell;
/* The thread ID should be stored in the last param dword */
assert(subgroup_id_index == -1 ||

2
src/intel/compiler/brw_fs.h
View file

@ -455,7 +455,7 @@ static inline unsigned
sample_mask_flag_subreg(const fs_visitor *shader)
{
assert(shader->stage == MESA_SHADER_FRAGMENT);
return shader->devinfo->gen >= 7 ? 2 : 1;
return shader->devinfo->ver >= 7 ? 2 : 1;
}
/**

10
src/intel/compiler/brw_fs_bank_conflicts.cpp
View file

@ -549,7 +549,7 @@ namespace {
* Register allocation ensures that, so don't move 127 around to avoid
* breaking that property.
*/
if (v->devinfo->gen >= 8)
if (v->devinfo->ver >= 8)
constrained[p.atom_of_reg(127)] = true;
foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
@ -571,14 +571,14 @@ namespace {
* source of the LINTERP instruction on Gen6, since pair-aligned
* barycentrics allow the PLN instruction to be used.
*/
if (v->devinfo->has_pln && v->devinfo->gen <= 6 &&
if (v->devinfo->has_pln && v->devinfo->ver <= 6 &&
inst->opcode == FS_OPCODE_LINTERP)
constrained[p.atom_of_reg(reg_of(inst->src[0]))] = true;
/* The location of the Gen7 MRF hack registers is hard-coded in the
* rest of the compiler back-end. Don't attempt to move them around.
*/
if (v->devinfo->gen >= 7) {
if (v->devinfo->ver >= 7) {
assert(inst->dst.file != MRF);
for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
@ -599,7 +599,7 @@ namespace {
bool
is_conflict_optimized_out(const gen_device_info *devinfo, const fs_inst *inst)
{
return devinfo->gen >= 9 &&
return devinfo->ver >= 9 &&
((is_grf(inst->src[0]) && (reg_of(inst->src[0]) == reg_of(inst->src[1]) ||
reg_of(inst->src[0]) == reg_of(inst->src[2]))) ||
reg_of(inst->src[1]) == reg_of(inst->src[2]));
@ -911,7 +911,7 @@ fs_visitor::opt_bank_conflicts()
assert(grf_used || !"Must be called after register allocation");
/* No ternary instructions -- No bank conflicts. */
if (devinfo->gen < 6)
if (devinfo->ver < 6)
return false;
const partitioning p = shader_reg_partitioning(this);

6
src/intel/compiler/brw_fs_builder.h
View file

@ -739,7 +739,7 @@ namespace brw {
LRP(const dst_reg &dst, const src_reg &x, const src_reg &y,
const src_reg &a) const
{
if (shader->devinfo->gen >= 6 && shader->devinfo->gen <= 10) {
if (shader->devinfo->ver >= 6 && shader->devinfo->ver <= 10) {
/* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
* we need to reorder the operands.
*/
@ -855,10 +855,10 @@ namespace brw {
* Gen7 relaxes most of the above restrictions, but still can't use IMM
* operands to math
*/
if ((shader->devinfo->gen == 6 &&
if ((shader->devinfo->ver == 6 &&
(src.file == IMM || src.file == UNIFORM ||
src.abs || src.negate)) ||
(shader->devinfo->gen == 7 && src.file == IMM)) {
(shader->devinfo->ver == 7 && src.file == IMM)) {
const dst_reg tmp = vgrf(src.type);
MOV(tmp, src);
return tmp;

8
src/intel/compiler/brw_fs_combine_constants.cpp
View file

@ -48,7 +48,7 @@ static const bool debug = false;
static bool
could_coissue(const struct gen_device_info *devinfo, const fs_inst *inst)
{
if (devinfo->gen != 7)
if (devinfo->ver != 7)
return false;
switch (inst->opcode) {
@ -77,7 +77,7 @@ must_promote_imm(const struct gen_device_info *devinfo, const fs_inst *inst)
{
switch (inst->opcode) {
case SHADER_OPCODE_POW:
return devinfo->gen < 8;
return devinfo->ver < 8;
case BRW_OPCODE_MAD:
case BRW_OPCODE_LRP:
return true;
@ -340,7 +340,7 @@ represent_src_as_imm(const struct gen_device_info *devinfo,
fs_reg *src)
{
/* TODO : consider specific platforms also */
if (devinfo->gen == 12) {
if (devinfo->ver == 12) {
uint16_t hf;
if (representable_as_hf(src->f, &hf)) {
*src = retype(brw_imm_uw(hf), BRW_REGISTER_TYPE_HF);
@ -465,7 +465,7 @@ fs_visitor::opt_combine_constants()
* replicating the single one we want. To avoid this, we always populate
* both HF slots within a DWord with the constant.
*/
const uint32_t width = devinfo->gen == 8 && imm->is_half_float ? 2 : 1;
const uint32_t width = devinfo->ver == 8 && imm->is_half_float ? 2 : 1;
const fs_builder ibld = bld.at(imm->block, n).exec_all().group(width, 0);
/* Put the immediate in an offset aligned to its size. Some instructions

18
src/intel/compiler/brw_fs_copy_propagation.cpp
View file

@ -419,10 +419,10 @@ can_take_stride(fs_inst *inst, brw_reg_type dst_type,
* restrictions.
*/
if (inst->is_math()) {
if (devinfo->gen == 6 || devinfo->gen == 7) {
if (devinfo->ver == 6 || devinfo->ver == 7) {
assert(inst->dst.stride == 1);
return stride == 1 || stride == 0;
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
return stride == inst->dst.stride || stride == 0;
}
}
@ -495,7 +495,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
* of a LINTERP instruction on platforms where the PLN instruction has
* register alignment restrictions.
*/
if (devinfo->has_pln && devinfo->gen <= 6 &&
if (devinfo->has_pln && devinfo->ver <= 6 &&
entry->src.file == FIXED_GRF && (entry->src.nr & 1) &&
inst->opcode == FS_OPCODE_LINTERP && arg == 0)
return false;
@ -516,7 +516,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
/* Reject cases that would violate register regioning restrictions. */
if ((entry->src.file == UNIFORM || !entry->src.is_contiguous()) &&
((devinfo->gen == 6 && inst->is_math()) ||
((devinfo->ver == 6 && inst->is_math()) ||
inst->is_send_from_grf() ||
inst->uses_indirect_addressing())) {
return false;
@ -619,7 +619,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
type_sz(entry->dst.type) != type_sz(inst->src[arg].type)))
return false;
if (devinfo->gen >= 8 && (entry->src.negate || entry->src.abs) &&
if (devinfo->ver >= 8 && (entry->src.negate || entry->src.abs) &&
is_logic_op(inst->opcode)) {
return false;
}
@ -752,14 +752,14 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
val.type = inst->src[i].type;
if (inst->src[i].abs) {
if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
if ((devinfo->ver >= 8 && is_logic_op(inst->opcode)) ||
!brw_abs_immediate(val.type, &val.as_brw_reg())) {
continue;
}
}
if (inst->src[i].negate) {
if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
if ((devinfo->ver >= 8 && is_logic_op(inst->opcode)) ||
!brw_negate_immediate(val.type, &val.as_brw_reg())) {
continue;
}
@ -776,7 +776,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
/* FINISHME: Promote non-float constants and remove this. */
if (devinfo->gen < 8)
if (devinfo->ver < 8)
break;
/* fallthrough */
case SHADER_OPCODE_POW:
@ -784,7 +784,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
* doesn't support scalar source math), and let constant combining
* promote the constant on Gen < 8.
*/
if (devinfo->gen == 6)
if (devinfo->ver == 6)
break;
/* fallthrough */
case BRW_OPCODE_BFI1:

182
src/intel/compiler/brw_fs_generator.cpp
View file

@ -61,7 +61,7 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
switch (reg->file) {
case MRF:
assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
/* Fallthrough */
case VGRF:
if (reg->stride == 0) {
@ -104,7 +104,7 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
}
if (devinfo->gen == 7 && !devinfo->is_haswell) {
if (devinfo->ver == 7 && !devinfo->is_haswell) {
/* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
* "Each DF (Double Float) operand uses an element size of 4 rather
* than 8 and all regioning parameters are twice what the values
@ -171,7 +171,7 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
* region, but on IVB and BYT DF regions must be programmed in terms of
* floats. A <0,2,1> region accomplishes this.
*/
if (devinfo->gen == 7 && !devinfo->is_haswell &&
if (devinfo->ver == 7 && !devinfo->is_haswell &&
type_sz(reg->type) == 8 &&
brw_reg.vstride == BRW_VERTICAL_STRIDE_0 &&
brw_reg.width == BRW_WIDTH_1 &&
@ -229,7 +229,7 @@ fs_generator::patch_halt_jumps()
int scale = brw_jump_scale(p->devinfo);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
/* There is a somewhat strange undocumented requirement of using
* HALT, according to the simulator. If some channel has HALTed to
* a particular UIP, then by the end of the program, every channel
@ -252,7 +252,7 @@ fs_generator::patch_halt_jumps()
brw_inst *patch = &p->store[patch_ip->ip];
assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
/* HALT takes a half-instruction distance from the pre-incremented IP. */
brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
} else {
@ -262,7 +262,7 @@ fs_generator::patch_halt_jumps()
this->discard_halt_patches.make_empty();
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
/* From the g965 PRM:
*
* "As DMask is not automatically reloaded into AMask upon completion
@ -279,7 +279,7 @@ fs_generator::patch_halt_jumps()
brw_inst_set_thread_control(devinfo, reset, BRW_THREAD_SWITCH);
}
if (devinfo->gen == 4 && !devinfo->is_g4x) {
if (devinfo->ver == 4 && !devinfo->is_g4x) {
/* From the g965 PRM:
*
* "[DevBW, DevCL] Erratum: The subfields in mask stack register are
@ -343,7 +343,7 @@ fs_generator::generate_send(fs_inst *inst,
inst->eot);
if (inst->check_tdr)
brw_inst_set_opcode(p->devinfo, brw_last_inst,
devinfo->gen >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC);
devinfo->ver >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC);
} else {
brw_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm,
inst->eot);
@ -360,7 +360,7 @@ fs_generator::fire_fb_write(fs_inst *inst,
{
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
@ -390,20 +390,20 @@ fs_generator::fire_fb_write(fs_inst *inst,
inst->last_rt,
inst->header_size != 0);
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
brw_inst_set_rt_slot_group(devinfo, insn, inst->group / 16);
}
void
fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
{
if (devinfo->gen < 8 && !devinfo->is_haswell) {
if (devinfo->ver < 8 && !devinfo->is_haswell) {
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
}
const struct brw_reg implied_header =
devinfo->gen < 6 ? payload : brw_null_reg();
devinfo->ver < 6 ? payload : brw_null_reg();
if (inst->base_mrf >= 0)
payload = brw_message_reg(inst->base_mrf);
@ -412,7 +412,7 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
fire_fb_write(inst, payload, implied_header, inst->mlen);
} else {
/* This can only happen in gen < 6 */
assert(devinfo->gen < 6);
assert(devinfo->ver < 6);
struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
@ -480,7 +480,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
}
} else {
/* Prior to Broadwell, there are only 8 address registers. */
assert(inst->exec_size <= 8 || devinfo->gen >= 8);
assert(inst->exec_size <= 8 || devinfo->ver >= 8);
/* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
struct brw_reg addr = vec8(brw_address_reg(0));
@ -532,24 +532,24 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
* initializing the whole address register with a pipelined NoMask MOV
* instruction.
*/
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
insn = brw_MOV(p, addr, brw_imm_uw(imm_byte_offset));
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
brw_set_default_swsb(p, tgl_swsb_null());
else
brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
}
insn = brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
brw_set_default_swsb(p, tgl_swsb_regdist(1));
else if (devinfo->gen >= 7)
else if (devinfo->ver >= 7)
brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
if (type_sz(reg.type) > 4 &&
((devinfo->gen == 7 && !devinfo->is_haswell) ||
((devinfo->ver == 7 && !devinfo->is_haswell) ||
devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads two
@ -577,7 +577,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
brw_inst *mov = brw_MOV(p, dst, retype(ind_src, reg.type));
if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
if (devinfo->ver == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
!inst->get_next()->is_tail_sentinel() &&
((fs_inst *)inst->get_next())->mlen > 0) {
/* From the Sandybridge PRM:
@ -606,7 +606,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
/* Ivy bridge has some strange behavior that makes this a real pain to
* implement for 64-bit values so we just don't bother.
*/
assert(devinfo->gen >= 8 || devinfo->is_haswell || type_sz(src.type) <= 4);
assert(devinfo->ver >= 8 || devinfo->is_haswell || type_sz(src.type) <= 4);
/* Because we're using the address register, we're limited to 8-wide
* execution on gen7. On gen8, we're limited to 16-wide by the address
@ -616,7 +616,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
* easier just to split it here.
*/
const unsigned lower_width =
(devinfo->gen <= 7 || type_sz(src.type) > 4) ?
(devinfo->ver <= 7 || type_sz(src.type) > 4) ?
8 : MIN2(16, inst->exec_size);
brw_set_default_exec_size(p, cvt(lower_width) - 1);
@ -695,7 +695,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
insn = brw_MOV(p, addr, brw_imm_uw(src_start_offset));
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
brw_set_default_swsb(p, tgl_swsb_null());
else
brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
@ -705,7 +705,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
insn = brw_SHL(p, addr, group_idx,
brw_imm_uw(util_logbase2(type_sz(src.type)) +
src.hstride - 1));
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
brw_set_default_swsb(p, tgl_swsb_regdist(1));
else
brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
@ -714,7 +714,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
brw_ADD(p, addr, addr, brw_imm_uw(src_start_offset));
if (type_sz(src.type) > 4 &&
((devinfo->gen == 7 && !devinfo->is_haswell) ||
((devinfo->ver == 7 && !devinfo->is_haswell) ||
devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads
@ -765,7 +765,7 @@ fs_generator::generate_quad_swizzle(const fs_inst *inst,
/* The value is uniform across all channels */
brw_MOV(p, dst, src);
} else if (devinfo->gen < 11 && type_sz(src.type) == 4) {
} else if (devinfo->ver < 11 && type_sz(src.type) == 4) {
/* This only works on 8-wide 32-bit values */
assert(inst->exec_size == 8);
assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
@ -809,7 +809,7 @@ fs_generator::generate_quad_swizzle(const fs_inst *inst,
4 * inst->dst.stride, 1, 4 * inst->dst.stride),
stride(suboffset(src, BRW_GET_SWZ(swiz, c)), 4, 1, 0));
if (devinfo->gen < 12) {
if (devinfo->ver < 12) {
brw_inst_set_no_dd_clear(devinfo, insn, c < 3);
brw_inst_set_no_dd_check(devinfo, insn, c > 0);
}
@ -834,7 +834,7 @@ fs_generator::generate_urb_read(fs_inst *inst,
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
brw_set_src0(p, send, header);
if (devinfo->gen < 12)
if (devinfo->ver < 12)
brw_set_src1(p, send, brw_imm_ud(0u));
brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
@ -856,7 +856,7 @@ fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
brw_set_dest(p, insn, brw_null_reg());
brw_set_src0(p, insn, payload);
if (devinfo->gen < 12)
if (devinfo->ver < 12)
brw_set_src1(p, insn, brw_imm_ud(0u));
brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
@ -886,7 +886,7 @@ fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UW));
if (devinfo->gen < 12)
if (devinfo->ver < 12)
brw_set_src1(p, insn, brw_imm_ud(0u));
/* Terminate a compute shader by sending a message to the thread spawner.
@ -899,7 +899,7 @@ fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
if (devinfo->gen < 11) {
if (devinfo->ver < 11) {
brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
/* Note that even though the thread has a URB resource associated with it,
@ -916,7 +916,7 @@ void
fs_generator::generate_barrier(fs_inst *, struct brw_reg src)
{
brw_barrier(p, src);
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_set_default_swsb(p, tgl_swsb_null());
brw_SYNC(p, TGL_SYNC_BAR);
} else {
@ -956,10 +956,10 @@ fs_generator::generate_linterp(fs_inst *inst,
/* nir_lower_interpolation() will do the lowering to MAD instructions for
* us on gen11+
*/
assert(devinfo->gen < 11);
assert(devinfo->ver < 11);
if (devinfo->has_pln) {
if (devinfo->gen <= 6 && (delta_x.nr & 1) != 0) {
if (devinfo->ver <= 6 && (delta_x.nr & 1) != 0) {
/* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
*
* "[DevSNB]:<src1> must be even register aligned.
@ -989,7 +989,7 @@ fs_generator::generate_linterp(fs_inst *inst,
/* LINE writes the accumulator automatically on gen4-5. On Sandy
* Bridge and later, we have to explicitly enable it.
*/
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
brw_inst_set_acc_wr_control(p->devinfo, line, true);
/* brw_set_default_saturate() is called before emitting
@ -1036,7 +1036,7 @@ fs_generator::generate_get_buffer_size(fs_inst *inst,
struct brw_reg src,
struct brw_reg surf_index)
{
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
assert(surf_index.file == BRW_IMMEDIATE_VALUE);
uint32_t simd_mode;
@ -1077,7 +1077,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst,
struct brw_reg surface_index,
struct brw_reg sampler_index)
{
assert(devinfo->gen < 7);
assert(devinfo->ver < 7);
assert(inst->size_written % REG_SIZE == 0);
int msg_type = -1;
uint32_t simd_mode;
@ -1122,7 +1122,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst,
unreachable("Invalid width for texture instruction");
}
if (devinfo->gen >= 5) {
if (devinfo->ver >= 5) {
switch (inst->opcode) {
case SHADER_OPCODE_TEX:
if (inst->shadow_compare) {
@ -1162,7 +1162,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst,
msg_type = GEN5_SAMPLER_MESSAGE_LOD;
break;
case SHADER_OPCODE_TG4:
assert(devinfo->gen == 6);
assert(devinfo->ver == 6);
assert(!inst->shadow_compare);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
break;
@ -1251,7 +1251,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst,
*/
struct brw_reg src = brw_null_reg();
if (inst->header_size != 0) {
if (devinfo->gen < 6 && !inst->offset) {
if (devinfo->ver < 6 && !inst->offset) {
/* Set up an implied move from g0 to the MRF. */
src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
} else {
@ -1342,7 +1342,7 @@ fs_generator::generate_ddx(const fs_inst *inst,
{
unsigned vstride, width;
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
if (inst->opcode == FS_OPCODE_DDX_FINE) {
/* produce accurate derivatives */
vstride = BRW_VERTICAL_STRIDE_2;
@ -1412,7 +1412,7 @@ fs_generator::generate_ddy(const fs_inst *inst,
* So for half-float operations we use the Gen11+ Align1 path. CHV
* inherits its FP16 hardware from SKL, so it is not affected.
*/
if (devinfo->gen >= 11 ||
if (devinfo->ver >= 11 ||
(devinfo->is_broadwell && src.type == BRW_REGISTER_TYPE_HF)) {
src = stride(src, 0, 2, 1);
@ -1439,7 +1439,7 @@ fs_generator::generate_ddy(const fs_inst *inst,
}
} else {
/* replicate the derivative at the top-left pixel to other pixels */
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
struct brw_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size);
struct brw_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size);
@ -1580,7 +1580,7 @@ fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
dst.type = BRW_REGISTER_TYPE_UD;
brw_inst *insn = brw_MOV(p, dst, brw_imm_ud(0));
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
brw_set_default_swsb(p, tgl_swsb_null());
else
brw_inst_set_no_dd_clear(p->devinfo, insn, true);
@ -1590,7 +1590,7 @@ fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
insn = brw_AND(p, suboffset(dst, 3),
retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
brw_imm_ud(INTEL_MASK(3, 0)));
if (devinfo->gen < 12) {
if (devinfo->ver < 12) {
brw_inst_set_no_dd_clear(p->devinfo, insn, true);
brw_inst_set_no_dd_check(p->devinfo, insn, true);
}
@ -1599,7 +1599,7 @@ fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
insn = brw_AND(p, suboffset(dst, 5),
retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
brw_imm_ud(INTEL_MASK(31, 10)));
if (devinfo->gen < 12)
if (devinfo->ver < 12)
brw_inst_set_no_dd_check(p->devinfo, insn, true);
}
@ -1691,7 +1691,7 @@ fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
struct brw_reg dst,
struct brw_reg index)
{
assert(devinfo->gen < 7); /* Should use the gen7 variant. */
assert(devinfo->ver < 7); /* Should use the gen7 variant. */
assert(inst->header_size != 0);
assert(inst->mlen);
@ -1709,7 +1709,7 @@ fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
rlen = 4;
}
if (devinfo->gen >= 5)
if (devinfo->ver >= 5)
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
else {
/* We always use the SIMD16 message so that we only have to load U, and
@ -1730,7 +1730,7 @@ fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
brw_inst_set_sfid(devinfo, send, BRW_SFID_SAMPLER);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
brw_set_src0(p, send, header);
if (devinfo->gen < 6)
if (devinfo->ver < 6)
brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
/* Our surface is set up as floats, regardless of what actual data is
@ -1782,7 +1782,7 @@ fs_generator::generate_set_sample_id(fs_inst *inst,
const struct brw_reg reg = stride(src1, 1, 4, 0);
const unsigned lower_size = MIN2(inst->exec_size,
devinfo->gen >= 8 ? 16 : 8);
devinfo->ver >= 8 ? 16 : 8);
for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
brw_inst *insn = brw_ADD(p, offset(dst, i * lower_size / 8),
@ -1803,7 +1803,7 @@ fs_generator::generate_pack_half_2x16_split(fs_inst *,
struct brw_reg x,
struct brw_reg y)
{
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
assert(dst.type == BRW_REGISTER_TYPE_UD);
assert(x.type == BRW_REGISTER_TYPE_F);
assert(y.type == BRW_REGISTER_TYPE_F);
@ -1845,7 +1845,7 @@ fs_generator::generate_shader_time_add(fs_inst *,
{
const tgl_swsb swsb = brw_get_default_swsb(p);
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_push_insn_state(p);
brw_set_default_mask_control(p, true);
brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
@ -1927,8 +1927,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
* The documentation is often lacking annotations for Atom parts,
* and empirically this affects CHV as well.
*/
if (devinfo->gen >= 8 &&
devinfo->gen <= 9 &&
if (devinfo->ver >= 8 &&
devinfo->ver <= 9 &&
p->nr_insn > 1 &&
brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
@ -1947,7 +1947,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
*
* Clear accumulator register before end of thread.
*/
if (inst->eot && is_accum_used && devinfo->gen >= 12) {
if (inst->eot && is_accum_used && devinfo->ver >= 12) {
brw_set_default_exec_size(p, BRW_EXECUTE_16);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
@ -2005,7 +2005,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
* ourselves.
*/
const unsigned flag_subreg = inst->flag_subreg +
(devinfo->gen >= 7 ? 0 : inst->group / 16);
(devinfo->ver >= 7 ? 0 : inst->group / 16);
brw_set_default_flag_reg(p, flag_subreg / 2, flag_subreg % 2);
brw_set_default_saturate(p, inst->saturate);
brw_set_default_mask_control(p, inst->force_writemask_all);
@ -2013,7 +2013,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_set_default_swsb(p, inst->sched);
unsigned exec_size = inst->exec_size;
if (devinfo->gen == 7 && !devinfo->is_haswell &&
if (devinfo->ver == 7 && !devinfo->is_haswell &&
(get_exec_type_size(inst) == 8 || type_sz(inst->dst.type) == 8)) {
exec_size *= 2;
}
@ -2022,7 +2022,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
assert(inst->force_writemask_all || inst->exec_size >= 4);
assert(inst->force_writemask_all || inst->group % inst->exec_size == 0);
assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->ver));
assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
switch (inst->opcode) {
@ -2051,15 +2051,15 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
break;
case BRW_OPCODE_MAD:
assert(devinfo->gen >= 6);
if (devinfo->gen < 10)
assert(devinfo->ver >= 6);
if (devinfo->ver < 10)
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MAD(p, dst, src[0], src[1], src[2]);
break;
case BRW_OPCODE_LRP:
assert(devinfo->gen >= 6 && devinfo->gen <= 10);
if (devinfo->gen < 10)
assert(devinfo->ver >= 6 && devinfo->ver <= 10);
if (devinfo->ver < 10)
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_LRP(p, dst, src[0], src[1], src[2]);
break;
@ -2099,25 +2099,25 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_SHL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_ROL:
assert(devinfo->gen >= 11);
assert(devinfo->ver >= 11);
assert(src[0].type == dst.type);
brw_ROL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_ROR:
assert(devinfo->gen >= 11);
assert(devinfo->ver >= 11);
assert(src[0].type == dst.type);
brw_ROR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_F32TO16:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_F32TO16(p, dst, src[0]);
break;
case BRW_OPCODE_F16TO32:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_F16TO32(p, dst, src[0]);
break;
case BRW_OPCODE_CMP:
if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell &&
if (inst->exec_size >= 16 && devinfo->ver == 7 && !devinfo->is_haswell &&
dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
/* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
* implemented in the compiler is not sufficient. Overriding the
@ -2129,7 +2129,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
break;
case BRW_OPCODE_CMPN:
if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell &&
if (inst->exec_size >= 16 && devinfo->ver == 7 && !devinfo->is_haswell &&
dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
/* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
* implemented in the compiler is not sufficient. Overriding the
@ -2144,22 +2144,22 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_SEL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_CSEL:
assert(devinfo->gen >= 8);
if (devinfo->gen < 10)
assert(devinfo->ver >= 8);
if (devinfo->ver < 10)
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_CSEL(p, dst, src[0], src[1], src[2]);
break;
case BRW_OPCODE_BFREV:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
case BRW_OPCODE_FBH:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_FBH(p, retype(dst, src[0].type), src[0]);
break;
case BRW_OPCODE_FBL:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
@ -2167,16 +2167,16 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_LZD(p, dst, src[0]);
break;
case BRW_OPCODE_CBIT:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
case BRW_OPCODE_ADDC:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_ADDC(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SUBB:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_SUBB(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_MAC:
@ -2184,19 +2184,19 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
break;
case BRW_OPCODE_BFE:
assert(devinfo->gen >= 7);
if (devinfo->gen < 10)
assert(devinfo->ver >= 7);
if (devinfo->ver < 10)
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_BFE(p, dst, src[0], src[1], src[2]);
break;
case BRW_OPCODE_BFI1:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_BFI1(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_BFI2:
assert(devinfo->gen >= 7);
if (devinfo->gen < 10)
assert(devinfo->ver >= 7);
if (devinfo->ver < 10)
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_BFI2(p, dst, src[0], src[1], src[2]);
break;
@ -2204,7 +2204,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
case BRW_OPCODE_IF:
if (inst->src[0].file != BAD_FILE) {
/* The instruction has an embedded compare (only allowed on gen6) */
assert(devinfo->gen == 6);
assert(devinfo->ver == 6);
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
} else {
brw_IF(p, brw_get_default_exec_size(p));
@ -2242,14 +2242,14 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
assert(inst->mlen == 0);
assert(devinfo->gen >= 7 || inst->exec_size == 8);
assert(devinfo->ver >= 7 || inst->exec_size == 8);
gen6_math(p, dst, brw_math_function(inst->opcode),
src[0], brw_null_reg());
} else {
assert(inst->mlen >= 1);
assert(devinfo->gen == 5 || devinfo->is_g4x || inst->exec_size == 8);
assert(devinfo->ver == 5 || devinfo->is_g4x || inst->exec_size == 8);
gen4_math(p, dst,
brw_math_function(inst->opcode),
inst->base_mrf, src[0],
@ -2261,9 +2261,9 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
case SHADER_OPCODE_INT_REMAINDER:
case SHADER_OPCODE_POW:
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
assert(inst->mlen == 0);
assert((devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) ||
assert((devinfo->ver >= 7 && inst->opcode == SHADER_OPCODE_POW) ||
inst->exec_size == 8);
gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
} else {
@ -2433,7 +2433,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
break;
}
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
/* Use the available SWSB information to stall. A single SYNC is
* sufficient since if there were multiple dependencies, the
* scoreboard algorithm already injected other SYNCs before this
@ -2465,7 +2465,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
break;
}
case FS_OPCODE_LOAD_LIVE_CHANNELS: {
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
assert(inst->force_writemask_all && inst->group == 0);
assert(inst->dst.file == BAD_FILE);
brw_set_default_exec_size(p, BRW_EXECUTE_1);
@ -2643,7 +2643,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
* For convenience, we combine Slice ID and Dual-SubSlice ID into a
* single ID.
*/
if (devinfo->gen == 12) {
if (devinfo->ver == 12) {
/* There is a SWSB restriction that requires that any time sr0 is
* accessed both the instruction doing the access and the next one
* have SWSB set to RegDist(1).
@ -2682,7 +2682,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
if (inst->conditional_mod)
brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
if (devinfo->gen < 12) {
if (devinfo->ver < 12) {
brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
}

4
src/intel/compiler/brw_fs_lower_regioning.cpp
View file

@ -140,7 +140,7 @@ namespace {
* used to pack components Y and W of a vector at offset 16B of a SIMD
* register. The problem doesn't occur if the stride of the source is 0.
*/
if (devinfo->gen == 8 &&
if (devinfo->ver == 8 &&
inst->opcode == BRW_OPCODE_MAD &&
inst->src[i].type == BRW_REGISTER_TYPE_HF &&
reg_offset(inst->src[i]) % REG_SIZE > 0 &&
@ -215,7 +215,7 @@ namespace {
* integer at codegen time due to hardware limitations of 64-bit
* types.
*/
return ((devinfo->gen == 7 && !devinfo->is_haswell) ||
return ((devinfo->ver == 7 && !devinfo->is_haswell) ||
devinfo->is_cherryview || gen_device_info_is_9lp(devinfo)) &&
type_sz(inst->src[0].type) > 4 &&
inst->dst.type != inst->src[0].type;

104
src/intel/compiler/brw_fs_nir.cpp
View file

@ -185,7 +185,7 @@ emit_system_values_block(nir_block *block, fs_visitor *v)
case nir_intrinsic_load_sample_mask_in:
assert(v->stage == MESA_SHADER_FRAGMENT);
assert(v->devinfo->gen >= 7);
assert(v->devinfo->ver >= 7);
reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_MASK_IN];
if (reg->file == BAD_FILE)
*reg = *v->emit_samplemaskin_setup();
@ -237,7 +237,7 @@ emit_system_values_block(nir_block *block, fs_visitor *v)
* a NOT instruction.
*/
fs_reg inverted = negate(shifted);
if (v->devinfo->gen < 8) {
if (v->devinfo->ver < 8) {
inverted = abld.vgrf(BRW_REGISTER_TYPE_UW);
abld.NOT(inverted, shifted);
}
@ -374,7 +374,7 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
bld.emit(BRW_OPCODE_ENDIF);
if (devinfo->gen < 7)
if (devinfo->ver < 7)
limit_dispatch_width(16, "Non-uniform control flow unsupported "
"in SIMD32 mode.");
}
@ -388,7 +388,7 @@ fs_visitor::nir_emit_loop(nir_loop *loop)
bld.emit(BRW_OPCODE_WHILE);
if (devinfo->gen < 7)
if (devinfo->ver < 7)
limit_dispatch_width(16, "Non-uniform control flow unsupported "
"in SIMD32 mode.");
}
@ -534,7 +534,7 @@ fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
fs_reg tmp = vgrf(glsl_type::int_type);
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
/* Bit 15 of g1.1 is 0 if the polygon is front facing. */
fs_reg g1 = fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W));
@ -551,7 +551,7 @@ fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
if (value1 == -1.0f)
bld.MOV(tmp, negate(tmp));
} else if (devinfo->gen >= 6) {
} else if (devinfo->ver >= 6) {
/* Bit 15 of g0.0 is 0 if the polygon is front facing. */
fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
@ -757,7 +757,7 @@ fs_visitor::try_emit_b2fi_of_inot(const fs_builder &bld,
fs_reg result,
nir_alu_instr *instr)
{
if (devinfo->gen < 6 || devinfo->gen >= 12)
if (devinfo->ver < 6 || devinfo->ver >= 12)
return false;
nir_alu_instr *inot_instr = nir_src_as_alu_instr(instr->src[0].src);
@ -1204,7 +1204,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
assert(nir_dest_bit_size(instr->dest.dest) < 64);
fs_reg tmp = bld.vgrf(result.type);
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
op[0] = resolve_source_modifiers(op[0]);
op[1] = resolve_source_modifiers(op[1]);
}
@ -1255,7 +1255,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
* swapped. The extension isn't enabled on those platforms, so don't
* pretend to support the differences.
*/
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
if (op[1].file == IMM)
op[1] = ud ? brw_imm_uw(op[1].ud) : brw_imm_w(op[1].d);
@ -1393,7 +1393,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
}
case nir_op_inot:
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
nir_alu_instr *inot_src_instr = nir_src_as_alu_instr(instr->src[0].src);
if (inot_src_instr != NULL &&
@ -1453,19 +1453,19 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
bld.NOT(result, op[0]);
break;
case nir_op_ixor:
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
resolve_inot_sources(bld, instr, op);
}
bld.XOR(result, op[0], op[1]);
break;
case nir_op_ior:
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
resolve_inot_sources(bld, instr, op);
}
bld.OR(result, op[0], op[1]);
break;
case nir_op_iand:
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
resolve_inot_sources(bld, instr, op);
}
bld.AND(result, op[0], op[1]);
@ -1539,7 +1539,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
case nir_op_ftrunc:
inst = bld.RNDZ(result, op[0]);
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
set_condmod(BRW_CONDITIONAL_R, inst);
set_predicate(BRW_PREDICATE_NORMAL,
bld.ADD(result, result, brw_imm_f(1.0f)));
@ -1563,7 +1563,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
break;
case nir_op_fround_even:
inst = bld.RNDE(result, op[0]);
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
set_condmod(BRW_CONDITIONAL_R, inst);
set_predicate(BRW_PREDICATE_NORMAL,
bld.ADD(result, result, brw_imm_f(1.0f)));
@ -1689,7 +1689,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
case nir_op_ifind_msb: {
assert(nir_dest_bit_size(instr->dest.dest) < 64);
if (devinfo->gen < 7) {
if (devinfo->ver < 7) {
emit_find_msb_using_lzd(bld, result, op[0], true);
} else {
bld.FBH(retype(result, BRW_REGISTER_TYPE_UD), op[0]);
@ -1711,7 +1711,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
case nir_op_find_lsb:
assert(nir_dest_bit_size(instr->dest.dest) < 64);
if (devinfo->gen < 7) {
if (devinfo->ver < 7) {
fs_reg temp = vgrf(glsl_type::int_type);
/* (x & -x) generates a value that consists of only the LSB of x.
@ -1858,7 +1858,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
/* If we need to do a boolean resolve, replace the result with -(x & 1)
* to sign extend the low bit to 0/~0
*/
if (devinfo->gen <= 5 &&
if (devinfo->ver <= 5 &&
!result.is_null() &&
(instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
fs_reg masked = vgrf(glsl_type::int_type);
@ -1893,8 +1893,8 @@ fs_visitor::nir_emit_load_const(const fs_builder &bld,
break;
case 64:
assert(devinfo->gen >= 7);
if (devinfo->gen == 7) {
assert(devinfo->ver >= 7);
if (devinfo->ver == 7) {
/* We don't get 64-bit integer types until gen8 */
for (unsigned i = 0; i < instr->def.num_components; i++) {
bld.MOV(retype(offset(reg, bld, i), BRW_REGISTER_TYPE_DF),
@ -1932,7 +1932,7 @@ fs_visitor::get_nir_src(const nir_src &src)
src.reg.base_offset * src.reg.reg->num_components);
}
if (nir_src_bit_size(src) == 64 && devinfo->gen == 7) {
if (nir_src_bit_size(src) == 64 && devinfo->ver == 7) {
/* The only 64-bit type available on gen7 is DF, so use that. */
reg.type = BRW_REGISTER_TYPE_DF;
} else {
@ -2429,7 +2429,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
if (nir_src_is_const(vertex_src)) {
unsigned vertex = nir_src_as_uint(vertex_src);
assert(devinfo->gen >= 9 || vertex <= 5);
assert(devinfo->ver >= 9 || vertex <= 5);
bld.MOV(icp_handle,
retype(brw_vec1_grf(first_icp_handle + vertex / 8, vertex % 8),
BRW_REGISTER_TYPE_UD));
@ -2713,7 +2713,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
/* Zero the message header */
bld.exec_all().MOV(m0, brw_imm_ud(0u));
if (devinfo->gen < 11) {
if (devinfo->ver < 11) {
/* Copy "Barrier ID" from r0.2, bits 16:13 */
chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
brw_imm_ud(INTEL_MASK(16, 13)));
@ -2726,7 +2726,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
}
/* Set the Barrier Count and the enable bit */
if (devinfo->gen < 11) {
if (devinfo->ver < 11) {
chanbld.OR(m0_2, m0_2,
brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
} else {
@ -3113,7 +3113,7 @@ fs_visitor::nir_emit_gs_intrinsic(const fs_builder &bld,
static fs_reg
fetch_render_target_array_index(const fs_builder &bld)
{
if (bld.shader->devinfo->gen >= 12) {
if (bld.shader->devinfo->ver >= 12) {
/* The render target array index is provided in the thread payload as
* bits 26:16 of r1.1.
*/
@ -3121,7 +3121,7 @@ fetch_render_target_array_index(const fs_builder &bld)
bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 3),
brw_imm_uw(0x7ff));
return idx;
} else if (bld.shader->devinfo->gen >= 6) {
} else if (bld.shader->devinfo->ver >= 6) {
/* The render target array index is provided in the thread payload as
* bits 26:16 of r0.0.
*/
@ -3186,7 +3186,7 @@ fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst,
* be equivalent to the normal CMS fetch for lower multisampling modes.
*/
const opcode op = !wm_key->multisample_fbo ? SHADER_OPCODE_TXF_LOGICAL :
devinfo->gen >= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL :
devinfo->ver >= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL :
SHADER_OPCODE_TXF_CMS_LOGICAL;
/* Emit the instruction. */
@ -3213,7 +3213,7 @@ fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst,
static fs_inst *
emit_coherent_fb_read(const fs_builder &bld, const fs_reg &dst, unsigned target)
{
assert(bld.shader->devinfo->gen >= 9);
assert(bld.shader->devinfo->ver >= 9);
fs_inst *inst = bld.emit(FS_OPCODE_FB_READ_LOGICAL, dst);
inst->target = target;
inst->size_written = 4 * inst->dst.component_size(inst->exec_size);
@ -3384,7 +3384,7 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
if (alu != NULL &&
alu->op != nir_op_bcsel &&
(devinfo->gen > 5 ||
(devinfo->ver > 5 ||
(alu->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE ||
alu->op == nir_op_fneu32 || alu->op == nir_op_feq32 ||
alu->op == nir_op_flt32 || alu->op == nir_op_fge32 ||
@ -3449,7 +3449,7 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
jump->predicate = BRW_PREDICATE_ALIGN1_ANY4H;
}
if (devinfo->gen < 7)
if (devinfo->ver < 7)
limit_dispatch_width(
16, "Fragment discard/demote not implemented in SIMD32 mode.\n");
break;
@ -3630,7 +3630,7 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
interp.type = BRW_REGISTER_TYPE_F;
dest.type = BRW_REGISTER_TYPE_F;
if (devinfo->gen < 6 && interp_mode == INTERP_MODE_SMOOTH) {
if (devinfo->ver < 6 && interp_mode == INTERP_MODE_SMOOTH) {
fs_reg tmp = vgrf(glsl_type::float_type);
bld.emit(FS_OPCODE_LINTERP, tmp, dst_xy, interp);
bld.MUL(offset(dest, bld, i), tmp, this->pixel_w);
@ -3733,7 +3733,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
break;
case nir_intrinsic_load_shared: {
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL);
const unsigned bit_size = nir_dest_bit_size(instr->dest);
@ -3770,7 +3770,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
}
case nir_intrinsic_store_shared: {
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL);
const unsigned bit_size = nir_src_bit_size(instr->src[0]);
@ -4322,7 +4322,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
slm_fence = false;
/* Prior to Gen11, there's only L3 fence, so emit that instead. */
if (slm_fence && devinfo->gen < 11) {
if (slm_fence && devinfo->ver < 11) {
slm_fence = false;
l3_fence = true;
}
@ -4331,7 +4331,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
* to flush it too.
*/
const bool needs_render_fence =
devinfo->gen == 7 && !devinfo->is_haswell;
devinfo->ver == 7 && !devinfo->is_haswell;
/* Be conservative in Gen11+ and always stall in a fence. Since there
* are two different fences, and shader might want to synchronize
@ -4340,11 +4340,11 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
* TODO: Use scope and visibility information for the barriers from NIR
* to make a better decision on whether we need to stall.
*/
const bool stall = devinfo->gen >= 11 || needs_render_fence ||
const bool stall = devinfo->ver >= 11 || needs_render_fence ||
instr->intrinsic == nir_intrinsic_end_invocation_interlock;
const bool commit_enable = stall ||
devinfo->gen >= 10; /* HSD ES # 1404612949 */
devinfo->ver >= 10; /* HSD ES # 1404612949 */
unsigned fence_regs_count = 0;
fs_reg fence_regs[2] = {};
@ -4584,7 +4584,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
case nir_intrinsic_load_global:
case nir_intrinsic_load_global_constant: {
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
assert(nir_dest_bit_size(instr->dest) <= 32);
assert(nir_intrinsic_align(instr) > 0);
@ -4613,7 +4613,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
}
case nir_intrinsic_store_global:
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
assert(nir_src_bit_size(instr->src[0]) <= 32);
assert(nir_intrinsic_write_mask(instr) ==
@ -4718,7 +4718,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
}
case nir_intrinsic_load_ssbo: {
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
const unsigned bit_size = nir_dest_bit_size(instr->dest);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
@ -4755,7 +4755,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
}
case nir_intrinsic_store_ssbo: {
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
const unsigned bit_size = nir_src_bit_size(instr->src[0]);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
@ -4887,13 +4887,13 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
}
case nir_intrinsic_load_scratch: {
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
assert(nir_dest_num_components(instr->dest) == 1);
const unsigned bit_size = nir_dest_bit_size(instr->dest);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
srcs[SURFACE_LOGICAL_SRC_SURFACE] =
brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT);
} else {
@ -4933,13 +4933,13 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
}
case nir_intrinsic_store_scratch: {
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
assert(nir_src_num_components(instr->src[0]) == 1);
const unsigned bit_size = nir_src_bit_size(instr->src[0]);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
srcs[SURFACE_LOGICAL_SRC_SURFACE] =
brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT);
} else {
@ -5185,7 +5185,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
case nir_intrinsic_quad_swap_horizontal: {
const fs_reg value = get_nir_src(instr->src[0]);
const fs_reg tmp = bld.vgrf(value.type);
if (devinfo->gen <= 7) {
if (devinfo->ver <= 7) {
/* The hardware doesn't seem to support these crazy regions with
* compressed instructions on gen7 and earlier so we fall back to
* using quad swizzles. Fortunately, we don't support 64-bit
@ -5920,7 +5920,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
if (srcs[TEX_LOGICAL_SRC_MCS].file == BAD_FILE &&
(instr->op == nir_texop_txf_ms ||
instr->op == nir_texop_samples_identical)) {
if (devinfo->gen >= 7 &&
if (devinfo->ver >= 7 &&
key_tex->compressed_multisample_layout_mask & (1 << texture)) {
srcs[TEX_LOGICAL_SRC_MCS] =
emit_mcs_fetch(srcs[TEX_LOGICAL_SRC_COORDINATE],
@ -6017,7 +6017,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
inst->offset = header_bits;
const unsigned dest_size = nir_tex_instr_dest_size(instr);
if (devinfo->gen >= 9 &&
if (devinfo->ver >= 9 &&
instr->op != nir_texop_tg4 && instr->op != nir_texop_query_levels) {
unsigned write_mask = instr->dest.is_ssa ?
nir_ssa_def_components_read(&instr->dest.ssa):
@ -6032,7 +6032,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
if (srcs[TEX_LOGICAL_SRC_SHADOW_C].file != BAD_FILE)
inst->shadow_compare = true;
if (instr->op == nir_texop_tg4 && devinfo->gen == 6)
if (instr->op == nir_texop_tg4 && devinfo->ver == 6)
emit_gen6_gather_wa(key_tex->gen6_gather_wa[texture], dst);
fs_reg nir_dest[5];
@ -6043,7 +6043,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
/* # levels is in .w */
nir_dest[0] = offset(dst, bld, 3);
} else if (instr->op == nir_texop_txs &&
dest_size >= 3 && devinfo->gen < 7) {
dest_size >= 3 && devinfo->ver < 7) {
/* Gen4-6 return 0 instead of 1 for single layer surfaces. */
fs_reg depth = offset(dst, bld, 2);
nir_dest[2] = vgrf(glsl_type::int_type);
@ -6198,9 +6198,9 @@ fs_reg
setup_imm_df(const fs_builder &bld, double v)
{
const struct gen_device_info *devinfo = bld.shader->devinfo;
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return brw_imm_df(v);
/* gen7.5 does not support DF immediates straighforward but the DIM

48
src/intel/compiler/brw_fs_reg_allocate.cpp
View file

@ -89,7 +89,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
int base_reg_count = BRW_MAX_GRF;
const int index = util_logbase2(dispatch_width / 8);
if (dispatch_width > 8 && devinfo->gen >= 7) {
if (dispatch_width > 8 && devinfo->ver >= 7) {
/* For IVB+, we don't need the PLN hacks or the even-reg alignment in
* SIMD16. Therefore, we can use the exact same register sets for
* SIMD16 as we do for SIMD8 and we don't need to recalculate them.
@ -125,7 +125,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
/* Compute the total number of registers across all classes. */
int ra_reg_count = 0;
for (int i = 0; i < class_count; i++) {
if (devinfo->gen <= 5 && dispatch_width >= 16) {
if (devinfo->ver <= 5 && dispatch_width >= 16) {
/* From the G45 PRM:
*
* In order to reduce the hardware complexity, the following
@ -152,7 +152,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
uint8_t *ra_reg_to_grf = ralloc_array(compiler, uint8_t, ra_reg_count);
struct ra_regs *regs = ra_alloc_reg_set(compiler, ra_reg_count, false);
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
ra_set_allocate_round_robin(regs);
int *classes = ralloc_array(compiler, int, class_count);
int aligned_bary_class = -1;
@ -173,7 +173,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
int aligned_bary_reg_count = 0;
for (int i = 0; i < class_count; i++) {
int class_reg_count;
if (devinfo->gen <= 5 && dispatch_width >= 16) {
if (devinfo->ver <= 5 && dispatch_width >= 16) {
class_reg_count = (base_reg_count - (class_sizes[i] - 1)) / 2;
/* See comment below. The only difference here is that we are
@ -219,7 +219,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
aligned_bary_reg_count = class_reg_count;
}
if (devinfo->gen <= 5 && dispatch_width >= 16) {
if (devinfo->ver <= 5 && dispatch_width >= 16) {
for (int j = 0; j < class_reg_count; j++) {
ra_class_add_reg(regs, classes[i], reg);
@ -260,8 +260,8 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
/* Add a special class for aligned barycentrics, which we'll put the
* first source of LINTERP on so that we can do PLN on Gen <= 6.
*/
if (devinfo->has_pln && (devinfo->gen == 6 ||
(dispatch_width == 8 && devinfo->gen <= 5))) {
if (devinfo->has_pln && (devinfo->ver == 6 ||
(dispatch_width == 8 && devinfo->ver <= 5))) {
aligned_bary_class = ra_alloc_reg_class(regs);
for (int i = 0; i < aligned_bary_reg_count; i++) {
@ -534,7 +534,7 @@ get_used_mrfs(const fs_visitor *v, bool *mrf_used)
{
int reg_width = v->dispatch_width / 8;
memset(mrf_used, 0, BRW_MAX_MRF(v->devinfo->gen) * sizeof(bool));
memset(mrf_used, 0, BRW_MAX_MRF(v->devinfo->ver) * sizeof(bool));
foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
if (inst->dst.file == MRF) {
@ -595,8 +595,8 @@ namespace {
spill_base_mrf(const backend_shader *s)
{
/* We don't use the MRF hack on Gen9+ */
assert(s->devinfo->gen < 9);
return BRW_MAX_MRF(s->devinfo->gen) - spill_max_size(s) - 1;
assert(s->devinfo->ver < 9);
return BRW_MAX_MRF(s->devinfo->ver) - spill_max_size(s) - 1;
}
}
@ -623,7 +623,7 @@ fs_reg_alloc::setup_live_interference(unsigned node,
* MRF registers.
*/
if (first_mrf_hack_node >= 0) {
for (int i = spill_base_mrf(fs); i < BRW_MAX_MRF(devinfo->gen); i++)
for (int i = spill_base_mrf(fs); i < BRW_MAX_MRF(devinfo->ver); i++)
ra_add_node_interference(g, node, first_mrf_hack_node + i);
}
@ -722,7 +722,7 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
* they're used as sources in the same instruction. We also need to add
* interference here.
*/
if (devinfo->gen >= 9) {
if (devinfo->ver >= 9) {
if (inst->opcode == SHADER_OPCODE_SEND && inst->ex_mlen > 0 &&
inst->src[2].file == VGRF && inst->src[3].file == VGRF &&
inst->src[2].nr != inst->src[3].nr)
@ -750,7 +750,7 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
* register early enough in the register file that we don't
* conflict with any used MRF hack registers.
*/
reg -= BRW_MAX_MRF(devinfo->gen) - spill_base_mrf(fs);
reg -= BRW_MAX_MRF(devinfo->ver) - spill_base_mrf(fs);
} else if (grf127_send_hack_node >= 0) {
/* Avoid r127 which might be unusable if the node was previously
* written by a SIMD8 SEND message with source/destination overlap.
@ -769,13 +769,13 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
node_count = 0;
first_payload_node = node_count;
node_count += payload_node_count;
if (devinfo->gen >= 7 && devinfo->gen < 9 && allow_spilling) {
if (devinfo->ver >= 7 && devinfo->ver < 9 && allow_spilling) {
first_mrf_hack_node = node_count;
node_count += BRW_MAX_GRF - GEN7_MRF_HACK_START;
} else {
first_mrf_hack_node = -1;
}
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
grf127_send_hack_node = node_count;
node_count ++;
} else {
@ -784,7 +784,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
first_vgrf_node = node_count;
node_count += fs->alloc.count;
last_vgrf_node = node_count - 1;
if (devinfo->gen >= 9 && allow_spilling) {
if (devinfo->ver >= 9 && allow_spilling) {
scratch_header_node = node_count++;
} else {
scratch_header_node = -1;
@ -805,7 +805,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
* The alternative would be to have per-physical-register classes, which
* would just be silly.
*/
if (devinfo->gen <= 5 && fs->dispatch_width >= 16) {
if (devinfo->ver <= 5 && fs->dispatch_width >= 16) {
/* We have to divide by 2 here because we only have even numbered
* registers. Some of the payload registers will be odd, but
* that's ok because their physical register numbers have already
@ -824,7 +824,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
* The alternative would be to have per-physical-register classes,
* which would just be silly.
*/
for (int i = 0; i < BRW_MAX_MRF(devinfo->gen); i++) {
for (int i = 0; i < BRW_MAX_MRF(devinfo->ver); i++) {
ra_set_node_reg(g, first_mrf_hack_node + i,
GEN7_MRF_HACK_START + i);
}
@ -891,7 +891,7 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, fs_reg dst,
for (unsigned i = 0; i < count / reg_size; i++) {
fs_inst *unspill_inst;
if (devinfo->gen >= 9) {
if (devinfo->ver >= 9) {
fs_reg header = this->scratch_header;
fs_builder ubld = bld.exec_all().group(1, 0);
assert(spill_offset % 16 == 0);
@ -913,7 +913,7 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, fs_reg dst,
BRW_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8),
BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ,
BRW_DATAPORT_READ_TARGET_RENDER_CACHE);
} else if (devinfo->gen >= 7 && spill_offset < (1 << 12) * REG_SIZE) {
} else if (devinfo->ver >= 7 && spill_offset < (1 << 12) * REG_SIZE) {
/* The Gen7 descriptor-based offset is 12 bits of HWORD units.
* Because the Gen7-style scratch block read is hardwired to BTI 255,
* on Gen9+ it would cause the DC to do an IA-coherent read, what
@ -947,7 +947,7 @@ fs_reg_alloc::emit_spill(const fs_builder &bld, fs_reg src,
for (unsigned i = 0; i < count / reg_size; i++) {
fs_inst *spill_inst;
if (devinfo->gen >= 9) {
if (devinfo->ver >= 9) {
fs_reg header = this->scratch_header;
fs_builder ubld = bld.exec_all().group(1, 0);
assert(spill_offset % 16 == 0);
@ -1146,7 +1146,7 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
* SIMD16 mode, because we'd stomp the FB writes.
*/
if (!fs->spilled_any_registers) {
if (devinfo->gen >= 9) {
if (devinfo->ver >= 9) {
this->scratch_header = alloc_scratch_header();
fs_builder ubld = fs->bld.exec_all().group(8, 0).at(
fs->cfg->first_block(), fs->cfg->first_block()->start());
@ -1154,10 +1154,10 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
this->scratch_header);
_mesa_set_add(spill_insts, header_inst);
} else {
bool mrf_used[BRW_MAX_MRF(devinfo->gen)];
bool mrf_used[BRW_MAX_MRF(devinfo->ver)];
get_used_mrfs(fs, mrf_used);
for (int i = spill_base_mrf(fs); i < BRW_MAX_MRF(devinfo->gen); i++) {
for (int i = spill_base_mrf(fs); i < BRW_MAX_MRF(devinfo->ver); i++) {
if (mrf_used[i]) {
fs->fail("Register spilling not supported with m%d used", i);
return;

2
src/intel/compiler/brw_fs_scoreboard.cpp
View file

@ -1075,7 +1075,7 @@ namespace {
bool
fs_visitor::lower_scoreboard()
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
const ordered_address *jps = ordered_inst_addresses(this);
const dependency_list *deps0 = gather_inst_dependencies(this, jps);
const dependency_list *deps1 = allocate_inst_dependencies(this, deps0);

24
src/intel/compiler/brw_fs_visitor.cpp
View file

@ -106,7 +106,7 @@ fs_visitor::emit_dummy_fs()
write = bld.emit(FS_OPCODE_FB_WRITE);
write->eot = true;
write->last_rt = true;
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
write->base_mrf = 2;
write->mlen = 4 * reg_width;
} else {
@ -119,7 +119,7 @@ fs_visitor::emit_dummy_fs()
* varying to avoid GPU hangs, so set that.
*/
struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data);
wm_prog_data->num_varying_inputs = devinfo->gen < 6 ? 1 : 0;
wm_prog_data->num_varying_inputs = devinfo->ver < 6 ? 1 : 0;
memset(wm_prog_data->urb_setup, -1,
sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
brw_compute_urb_setup_index(wm_prog_data);
@ -278,7 +278,7 @@ fs_visitor::emit_interpolation_setup_gen6()
const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
struct brw_reg gi_uw = retype(brw_vec1_grf(1 + i, 0), BRW_REGISTER_TYPE_UW);
if (devinfo->gen >= 8 || dispatch_width == 8) {
if (devinfo->ver >= 8 || dispatch_width == 8) {
/* The "Register Region Restrictions" page says for BDW (and newer,
* presumably):
*
@ -478,7 +478,7 @@ fs_visitor::emit_fb_writes()
fs_inst *inst = NULL;
if (source_depth_to_render_target && devinfo->gen == 6) {
if (source_depth_to_render_target && devinfo->ver == 6) {
/* For outputting oDepth on gen6, SIMD8 writes have to be used. This
* would require SIMD8 moves of each half to message regs, e.g. by using
* the SIMD lowering pass. Unfortunately this is more difficult than it
@ -503,7 +503,7 @@ fs_visitor::emit_fb_writes()
*/
const bool replicate_alpha = key->alpha_test_replicate_alpha ||
(key->nr_color_regions > 1 && key->alpha_to_coverage &&
(sample_mask.file == BAD_FILE || devinfo->gen == 6));
(sample_mask.file == BAD_FILE || devinfo->ver == 6));
for (int target = 0; target < key->nr_color_regions; target++) {
/* Skip over outputs that weren't written. */
@ -514,7 +514,7 @@ fs_visitor::emit_fb_writes()
ralloc_asprintf(this->mem_ctx, "FB write target %d", target));
fs_reg src0_alpha;
if (devinfo->gen >= 6 && replicate_alpha && target != 0)
if (devinfo->ver >= 6 && replicate_alpha && target != 0)
src0_alpha = offset(outputs[0], bld, 3);
inst = emit_single_fb_write(abld, this->outputs[target],
@ -546,7 +546,7 @@ fs_visitor::emit_fb_writes()
inst->last_rt = true;
inst->eot = true;
if (devinfo->gen >= 11 && devinfo->gen <= 12 &&
if (devinfo->ver >= 11 && devinfo->ver <= 12 &&
prog_data->dual_src_blend) {
/* The dual-source RT write messages fail to release the thread
* dependency on ICL and TGL with SIMD32 dispatch, leading to hangs.
@ -753,7 +753,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
fs_inst *inst = abld.emit(opcode, reg_undef, payload);
/* For ICL WA 1805992985 one needs additional write in the end. */
if (devinfo->gen == 11 && stage == MESA_SHADER_TESS_EVAL)
if (devinfo->ver == 11 && stage == MESA_SHADER_TESS_EVAL)
inst->eot = false;
else
inst->eot = slot == last_slot && stage != MESA_SHADER_GEOMETRY;
@ -801,7 +801,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
* send cycle, which is a urb write with an eot must be 4 phases long and
* all 8 lanes must valid.
*/
if (devinfo->gen == 11 && stage == MESA_SHADER_TESS_EVAL) {
if (devinfo->ver == 11 && stage == MESA_SHADER_TESS_EVAL) {
fs_reg payload = fs_reg(VGRF, alloc.allocate(6), BRW_REGISTER_TYPE_UD);
/* Workaround requires all 8 channels (lanes) to be valid. This is
@ -842,7 +842,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
void
fs_visitor::emit_cs_terminate()
{
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
/* We can't directly send from g0, since sends with EOT have to use
* g112-127. So, copy it to a virtual register, The register allocator will
@ -862,7 +862,7 @@ void
fs_visitor::emit_barrier()
{
uint32_t barrier_id_mask;
switch (devinfo->gen) {
switch (devinfo->ver) {
case 7:
case 8:
barrier_id_mask = 0x0f000000u; break;
@ -959,7 +959,7 @@ fs_visitor::init()
this->source_depth_to_render_target = false;
this->runtime_check_aads_emit = false;
this->first_non_payload_grf = 0;
this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->max_grf = devinfo->ver >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->uniforms = 0;
this->last_scratch = 0;

262
src/intel/compiler/brw_inst.h
View file

@ -59,7 +59,7 @@ brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst *inst, uint64_t v) \
{ \
assert(assertions); \
if (devinfo->gen >= 12) \
if (devinfo->ver >= 12) \
brw_inst_set_bits(inst, hi12, lo12, v); \
else \
brw_inst_set_bits(inst, hi4, lo4, v); \
@ -69,7 +69,7 @@ brw_inst_##name(const struct gen_device_info *devinfo, \
const brw_inst *inst) \
{ \
assert(assertions); \
if (devinfo->gen >= 12) \
if (devinfo->ver >= 12) \
return brw_inst_bits(inst, hi12, lo12); \
else \
return brw_inst_bits(inst, hi4, lo4); \
@ -83,15 +83,15 @@ brw_inst_##name(const struct gen_device_info *devinfo, \
#define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
hi7, lo7, hi8, lo8, hi12, lo12) \
unsigned high, low; \
if (devinfo->gen >= 12) { \
if (devinfo->ver >= 12) { \
high = hi12; low = lo12; \
} else if (devinfo->gen >= 8) { \
} else if (devinfo->ver >= 8) { \
high = hi8; low = lo8; \
} else if (devinfo->gen >= 7) { \
} else if (devinfo->ver >= 7) { \
high = hi7; low = lo7; \
} else if (devinfo->gen >= 6) { \
} else if (devinfo->ver >= 6) { \
high = hi6; low = lo6; \
} else if (devinfo->gen >= 5) { \
} else if (devinfo->ver >= 5) { \
high = hi5; low = lo5; \
} else if (devinfo->is_g4x) { \
high = hi45; low = lo45; \
@ -144,7 +144,7 @@ brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst *inst, uint64_t value) \
{ \
assert(assertions); \
if (devinfo->gen >= 12) { \
if (devinfo->ver >= 12) { \
const unsigned k = hi12 - lo12 + 1; \
if (hi12ex != -1 && lo12ex != -1) \
brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \
@ -159,7 +159,7 @@ static inline uint64_t \
brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
{ \
assert(assertions); \
if (devinfo->gen >= 12) { \
if (devinfo->ver >= 12) { \
const unsigned k = hi12 - lo12 + 1; \
return (hi12ex == -1 || lo12ex == -1 ? 0 : \
brw_inst_bits(inst, hi12ex, lo12ex) << k) | \
@ -193,7 +193,7 @@ static inline void \
brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst *inst, uint64_t value) \
{ \
if (devinfo->gen >= 12) { \
if (devinfo->ver >= 12) { \
brw_inst_set_bits(inst, hi12, hi12, value >> 1); \
if ((value >> 1) == 0) \
brw_inst_set_bits(inst, lo12, lo12, value & 1); \
@ -206,7 +206,7 @@ brw_inst_set_##name(const struct gen_device_info *devinfo, \
static inline uint64_t \
brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
{ \
if (devinfo->gen >= 12) { \
if (devinfo->ver >= 12) { \
return (brw_inst_bits(inst, hi12, hi12) << 1) | \
(brw_inst_bits(inst, hi12, hi12) == 0 ? \
brw_inst_bits(inst, lo12, lo12) : 1); \
@ -225,7 +225,7 @@ static inline void \
brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst *inst, uint64_t v) \
{ \
if (devinfo->gen >= 12) \
if (devinfo->ver >= 12) \
assert(v == (const12)); \
else \
brw_inst_set_bits(inst, hi4, lo4, v); \
@ -234,7 +234,7 @@ static inline uint64_t \
brw_inst_##name(const struct gen_device_info *devinfo, \
const brw_inst *inst) \
{ \
if (devinfo->gen >= 12) \
if (devinfo->ver >= 12) \
return (const12); \
else \
return brw_inst_bits(inst, hi4, lo4); \
@ -297,11 +297,11 @@ F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32, /* 12+ */ 22, 22)
F(saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
F(debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->gen >= 8)
FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->gen >= 6)
FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->gen == 5)
FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 8)
FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 6)
FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->ver == 5)
F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
FC(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo->gen >= 6)
FC(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo->ver >= 6)
F(exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
F(pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
F(pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24)
@ -404,38 +404,38 @@ REG_TYPE(src)
*/
/* Reserved 127:126 */
/* src2_reg_nr same in align16 */
FC(3src_a1_src2_subreg_nr, /* 4+ */ 117, 113, /* 12+ */ 119, 115, devinfo->gen >= 10)
FC(3src_a1_src2_hstride, /* 4+ */ 112, 111, /* 12+ */ 113, 112, devinfo->gen >= 10)
FC(3src_a1_src2_subreg_nr, /* 4+ */ 117, 113, /* 12+ */ 119, 115, devinfo->ver >= 10)
FC(3src_a1_src2_hstride, /* 4+ */ 112, 111, /* 12+ */ 113, 112, devinfo->ver >= 10)
/* Reserved 110:109. src2 vstride is an implied parameter */
FC(3src_a1_src2_hw_type, /* 4+ */ 108, 106, /* 12+ */ 82, 80, devinfo->gen >= 10)
FC(3src_a1_src2_hw_type, /* 4+ */ 108, 106, /* 12+ */ 82, 80, devinfo->ver >= 10)
/* Reserved 105 */
/* src1_reg_nr same in align16 */
FC(3src_a1_src1_subreg_nr, /* 4+ */ 96, 92, /* 12+ */ 103, 99, devinfo->gen >= 10)
FC(3src_a1_src1_hstride, /* 4+ */ 91, 90, /* 12+ */ 97, 96, devinfo->gen >= 10)
FDC(3src_a1_src1_vstride, /* 4+ */ 89, 88, /* 12+ */ 91, 91, 83, 83, devinfo->gen >= 10)
FC(3src_a1_src1_hw_type, /* 4+ */ 87, 85, /* 12+ */ 90, 88, devinfo->gen >= 10)
FC(3src_a1_src1_subreg_nr, /* 4+ */ 96, 92, /* 12+ */ 103, 99, devinfo->ver >= 10)
FC(3src_a1_src1_hstride, /* 4+ */ 91, 90, /* 12+ */ 97, 96, devinfo->ver >= 10)
FDC(3src_a1_src1_vstride, /* 4+ */ 89, 88, /* 12+ */ 91, 91, 83, 83, devinfo->ver >= 10)
FC(3src_a1_src1_hw_type, /* 4+ */ 87, 85, /* 12+ */ 90, 88, devinfo->ver >= 10)
/* Reserved 84 */
/* src0_reg_nr same in align16 */
FC(3src_a1_src0_subreg_nr, /* 4+ */ 75, 71, /* 12+ */ 71, 67, devinfo->gen >= 10)
FC(3src_a1_src0_hstride, /* 4+ */ 70, 69, /* 12+ */ 65, 64, devinfo->gen >= 10)
FDC(3src_a1_src0_vstride, /* 4+ */ 68, 67, /* 12+ */ 43, 43, 35, 35, devinfo->gen >= 10)
FC(3src_a1_src0_hw_type, /* 4+ */ 66, 64, /* 12+ */ 42, 40, devinfo->gen >= 10)
FC(3src_a1_src0_subreg_nr, /* 4+ */ 75, 71, /* 12+ */ 71, 67, devinfo->ver >= 10)
FC(3src_a1_src0_hstride, /* 4+ */ 70, 69, /* 12+ */ 65, 64, devinfo->ver >= 10)
FDC(3src_a1_src0_vstride, /* 4+ */ 68, 67, /* 12+ */ 43, 43, 35, 35, devinfo->ver >= 10)
FC(3src_a1_src0_hw_type, /* 4+ */ 66, 64, /* 12+ */ 42, 40, devinfo->ver >= 10)
/* dst_reg_nr same in align16 */
FC(3src_a1_dst_subreg_nr, /* 4+ */ 55, 54, /* 12+ */ 55, 54, devinfo->gen >= 10)
FC(3src_a1_special_acc, /* 4+ */ 55, 52, /* 12+ */ 54, 51, devinfo->gen >= 10) /* aliases dst_subreg_nr */
FC(3src_a1_dst_subreg_nr, /* 4+ */ 55, 54, /* 12+ */ 55, 54, devinfo->ver >= 10)
FC(3src_a1_special_acc, /* 4+ */ 55, 52, /* 12+ */ 54, 51, devinfo->ver >= 10) /* aliases dst_subreg_nr */
/* Reserved 51:50 */
FC(3src_a1_dst_hstride, /* 4+ */ 49, 49, /* 12+ */ 48, 48, devinfo->gen >= 10)
FC(3src_a1_dst_hw_type, /* 4+ */ 48, 46, /* 12+ */ 38, 36, devinfo->gen >= 10)
FC(3src_a1_dst_hstride, /* 4+ */ 49, 49, /* 12+ */ 48, 48, devinfo->ver >= 10)
FC(3src_a1_dst_hw_type, /* 4+ */ 48, 46, /* 12+ */ 38, 36, devinfo->ver >= 10)
FI(3src_a1_src2_reg_file, /* 4+ */ -1, -1, /* 8+ */ 45, 45, /* 12+ */ 47, 114)
FC(3src_a1_src1_reg_file, /* 4+ */ 44, 44, /* 12+ */ 98, 98, devinfo->gen >= 10)
FC(3src_a1_src1_reg_file, /* 4+ */ 44, 44, /* 12+ */ 98, 98, devinfo->ver >= 10)
FI(3src_a1_src0_reg_file, /* 4+ */ -1, -1, /* 8+ */ 43, 43, /* 12+ */ 46, 66)
F(3src_a1_src2_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
F(3src_a1_src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
/* Source Modifier fields same in align16 */
FC(3src_a1_dst_reg_file, /* 4+ */ 36, 36, /* 12+ */ 50, 50, devinfo->gen >= 10)
FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ 39, 39, devinfo->gen >= 10)
FC(3src_a1_dst_reg_file, /* 4+ */ 36, 36, /* 12+ */ 50, 50, devinfo->ver >= 10)
FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ 39, 39, devinfo->ver >= 10)
/* Fields below this same in align16 */
/** @} */
@ -481,8 +481,8 @@ static inline uint16_t
brw_inst_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
const brw_inst *insn)
{
assert(devinfo->gen >= 10);
if (devinfo->gen >= 12)
assert(devinfo->ver >= 10);
if (devinfo->ver >= 12)
return brw_inst_bits(insn, 79, 64);
else
return brw_inst_bits(insn, 82, 67);
@ -492,8 +492,8 @@ static inline uint16_t
brw_inst_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
const brw_inst *insn)
{
assert(devinfo->gen >= 10);
if (devinfo->gen >= 12)
assert(devinfo->ver >= 10);
if (devinfo->ver >= 12)
return brw_inst_bits(insn, 127, 112);
else
return brw_inst_bits(insn, 124, 109);
@ -503,8 +503,8 @@ static inline void
brw_inst_set_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
brw_inst *insn, uint16_t value)
{
assert(devinfo->gen >= 10);
if (devinfo->gen >= 12)
assert(devinfo->ver >= 10);
if (devinfo->ver >= 12)
brw_inst_set_bits(insn, 79, 64, value);
else
brw_inst_set_bits(insn, 82, 67, value);
@ -514,8 +514,8 @@ static inline void
brw_inst_set_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
brw_inst *insn, uint16_t value)
{
assert(devinfo->gen >= 10);
if (devinfo->gen >= 12)
assert(devinfo->ver >= 10);
if (devinfo->ver >= 12)
brw_inst_set_bits(insn, 127, 112, value);
else
brw_inst_set_bits(insn, 124, 109, value);
@ -530,12 +530,12 @@ static inline void
brw_inst_set_uip(const struct gen_device_info *devinfo,
brw_inst *inst, int32_t value)
{
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
brw_inst_set_src1_is_imm(devinfo, inst, 1);
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
} else {
assert(value <= (1 << 16) - 1);
@ -547,9 +547,9 @@ brw_inst_set_uip(const struct gen_device_info *devinfo,
static inline int32_t
brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
{
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
return brw_inst_bits(inst, 95, 64);
} else {
return (int16_t)brw_inst_bits(inst, 127, 112);
@ -560,12 +560,12 @@ static inline void
brw_inst_set_jip(const struct gen_device_info *devinfo,
brw_inst *inst, int32_t value)
{
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
brw_inst_set_src0_is_imm(devinfo, inst, 1);
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
} else {
assert(value <= (1 << 15) - 1);
@ -577,9 +577,9 @@ brw_inst_set_jip(const struct gen_device_info *devinfo,
static inline int32_t
brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
{
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
return brw_inst_bits(inst, 127, 96);
} else {
return (int16_t)brw_inst_bits(inst, 111, 96);
@ -603,23 +603,23 @@ brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
return brw_inst_bits(inst, high, low); \
}
FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
FC(gen4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->gen < 6)
FJ(gen6_jump_count, 63, 48, devinfo->ver == 6)
FJ(gen4_jump_count, 111, 96, devinfo->ver < 6)
FC(gen4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->ver < 6)
/** @} */
/**
* SEND instructions:
* @{
*/
FC(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ 42, 40, devinfo->gen >= 9)
FC(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1, devinfo->gen >= 9)
FC(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ 48, 48, devinfo->gen >= 9)
FC(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ 49, 49, devinfo->gen >= 9)
FC(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ 42, 40, devinfo->ver >= 9)
FC(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1, devinfo->ver >= 9)
FC(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ 48, 48, devinfo->ver >= 9)
FC(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ 49, 49, devinfo->ver >= 9)
F8(send_src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 66, 66)
FC(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ 111, 104, devinfo->gen >= 9)
FC(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ 98, 98, devinfo->gen >= 9)
FC(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ 50, 50, devinfo->gen >= 9)
FC(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ 111, 104, devinfo->ver >= 9)
FC(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ 98, 98, devinfo->ver >= 9)
FC(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ 50, 50, devinfo->ver >= 9)
/** @} */
/* Message descriptor bits */
@ -643,16 +643,16 @@ static inline void
brw_inst_set_send_desc(const struct gen_device_info *devinfo,
brw_inst *inst, uint32_t value)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_bits(inst, 123, 122, GET_BITS(value, 31, 30));
brw_inst_set_bits(inst, 71, 67, GET_BITS(value, 29, 25));
brw_inst_set_bits(inst, 55, 51, GET_BITS(value, 24, 20));
brw_inst_set_bits(inst, 121, 113, GET_BITS(value, 19, 11));
brw_inst_set_bits(inst, 91, 81, GET_BITS(value, 10, 0));
} else if (devinfo->gen >= 9) {
} else if (devinfo->ver >= 9) {
brw_inst_set_bits(inst, 126, 96, value);
assert(value >> 31 == 0);
} else if (devinfo->gen >= 5) {
} else if (devinfo->ver >= 5) {
brw_inst_set_bits(inst, 124, 96, value);
assert(value >> 29 == 0);
} else {
@ -669,15 +669,15 @@ brw_inst_set_send_desc(const struct gen_device_info *devinfo,
static inline uint32_t
brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
return (brw_inst_bits(inst, 123, 122) << 30 |
brw_inst_bits(inst, 71, 67) << 25 |
brw_inst_bits(inst, 55, 51) << 20 |
brw_inst_bits(inst, 121, 113) << 11 |
brw_inst_bits(inst, 91, 81));
} else if (devinfo->gen >= 9) {
} else if (devinfo->ver >= 9) {
return brw_inst_bits(inst, 126, 96);
} else if (devinfo->gen >= 5) {
} else if (devinfo->ver >= 5) {
return brw_inst_bits(inst, 124, 96);
} else {
return brw_inst_bits(inst, 119, 96);
@ -697,7 +697,7 @@ static inline void
brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
brw_inst *inst, uint32_t value)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_bits(inst, 127, 124, GET_BITS(value, 31, 28));
brw_inst_set_bits(inst, 97, 96, GET_BITS(value, 27, 26));
brw_inst_set_bits(inst, 65, 64, GET_BITS(value, 25, 24));
@ -705,7 +705,7 @@ brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
brw_inst_set_bits(inst, 103, 99, GET_BITS(value, 10, 6));
assert(GET_BITS(value, 5, 0) == 0);
} else {
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
@ -727,7 +727,7 @@ static inline void
brw_inst_set_sends_ex_desc(const struct gen_device_info *devinfo,
brw_inst *inst, uint32_t value)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_send_ex_desc(devinfo, inst, value);
} else {
brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
@ -746,14 +746,14 @@ static inline uint32_t
brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
const brw_inst *inst)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
return (brw_inst_bits(inst, 127, 124) << 28 |
brw_inst_bits(inst, 97, 96) << 26 |
brw_inst_bits(inst, 65, 64) << 24 |
brw_inst_bits(inst, 47, 35) << 11 |
brw_inst_bits(inst, 103, 99) << 6);
} else {
assert(devinfo->gen >= 9);
assert(devinfo->ver >= 9);
return (brw_inst_bits(inst, 94, 91) << 28 |
brw_inst_bits(inst, 88, 85) << 24 |
brw_inst_bits(inst, 83, 80) << 20 |
@ -770,7 +770,7 @@ static inline uint32_t
brw_inst_sends_ex_desc(const struct gen_device_info *devinfo,
const brw_inst *inst)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
return brw_inst_send_ex_desc(devinfo, inst);
} else {
return (brw_inst_bits(inst, 95, 80) << 16 |
@ -835,7 +835,7 @@ FF(null_rt,
/* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
/* 8: */ 80, 80,
/* 12: */ 44, 44) /* actually only Gen11+ */
FC(base_mrf, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo->gen < 6);
FC(base_mrf, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo->ver < 6);
FF(send_rta_index,
/* 4: */ -1, -1,
/* 4.5 */ -1, -1,
@ -855,10 +855,10 @@ FF(urb_per_slot_offset,
/* 7: */ MD(16), MD(16),
/* 8: */ MD(17), MD(17),
/* 12: */ MD12(17), MD12(17))
FC(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->gen >= 8)
FC(urb_complete, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen < 8)
FC(urb_used, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1, devinfo->gen < 7)
FC(urb_allocate, /* 4+ */ MD(13), MD(13), /* 12+ */ -1, -1, devinfo->gen < 7)
FC(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->ver >= 8)
FC(urb_complete, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->ver < 8)
FC(urb_used, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1, devinfo->ver < 7)
FC(urb_allocate, /* 4+ */ MD(13), MD(13), /* 12+ */ -1, -1, devinfo->ver < 7)
FF(urb_swizzle_control,
/* 4: */ MD(11), MD(10),
/* 4.5: */ MD(11), MD(10),
@ -889,11 +889,11 @@ FF(urb_opcode,
* Gen4-5 math messages:
* @{
*/
FC(math_msg_data_type, /* 4+ */ MD(7), MD(7), /* 12+ */ -1, -1, devinfo->gen < 6)
FC(math_msg_saturate, /* 4+ */ MD(6), MD(6), /* 12+ */ -1, -1, devinfo->gen < 6)
FC(math_msg_precision, /* 4+ */ MD(5), MD(5), /* 12+ */ -1, -1, devinfo->gen < 6)
FC(math_msg_signed_int, /* 4+ */ MD(4), MD(4), /* 12+ */ -1, -1, devinfo->gen < 6)
FC(math_msg_function, /* 4+ */ MD(3), MD(0), /* 12+ */ -1, -1, devinfo->gen < 6)
FC(math_msg_data_type, /* 4+ */ MD(7), MD(7), /* 12+ */ -1, -1, devinfo->ver < 6)
FC(math_msg_saturate, /* 4+ */ MD(6), MD(6), /* 12+ */ -1, -1, devinfo->ver < 6)
FC(math_msg_precision, /* 4+ */ MD(5), MD(5), /* 12+ */ -1, -1, devinfo->ver < 6)
FC(math_msg_signed_int, /* 4+ */ MD(4), MD(4), /* 12+ */ -1, -1, devinfo->ver < 6)
FC(math_msg_function, /* 4+ */ MD(3), MD(0), /* 12+ */ -1, -1, devinfo->ver < 6)
/** @} */
/**
@ -915,7 +915,7 @@ FF(sampler_msg_type,
/* 7: */ MD(16), MD(12),
/* 8: */ MD(16), MD(12),
/* 12: */ MD12(16), MD12(12))
FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->gen == 4 && !devinfo->is_g4x)
FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->ver == 4 && !devinfo->is_g4x)
FD(sampler,
/* 4: */ MD(11), MD(8),
/* 4.5: */ MD(11), MD(8),
@ -931,7 +931,7 @@ F(binding_table_index, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) /*
* Data port message function control bits:
* @{
*/
FC(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18), devinfo->gen >= 7)
FC(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18), devinfo->ver >= 7)
/* Gen4-5 store fields in different bits for read/write messages. */
FF(dp_read_msg_type,
@ -966,7 +966,7 @@ FD(dp_write_msg_control,
/* 7: */ MD(13), MD( 8),
/* 8: */ MD(13), MD( 8),
/* 12: */ MD12(13), MD12(11), MD12(10), MD12(8))
FC(dp_read_target_cache, /* 4+ */ MD(15), MD(14), /* 12+ */ -1, -1, devinfo->gen < 6);
FC(dp_read_target_cache, /* 4+ */ MD(15), MD(14), /* 12+ */ -1, -1, devinfo->ver < 6);
FF(dp_write_commit,
/* 4: */ MD(15), MD(15),
@ -997,10 +997,10 @@ FD(dp_msg_control,
* Scratch message bits (Gen7+):
* @{
*/
FC(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
FC(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1, devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
FC(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->gen >= 7)
FC(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12), devinfo->gen >= 7)
FC(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17), devinfo->ver >= 7) /* 0 = read, 1 = write */
FC(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1, devinfo->ver >= 7) /* 0 = OWord, 1 = DWord */
FC(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->ver >= 7)
FC(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12), devinfo->ver >= 7)
FD(scratch_addr_offset,
/* 4: */ -1, -1,
/* 4.5: */ -1, -1,
@ -1023,7 +1023,7 @@ FF(rt_last,
/* 7: */ MD(12), MD(12),
/* 8: */ MD(12), MD(12),
/* 12: */ MD12(12), MD12(12))
FC(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11), devinfo->gen >= 6)
FC(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11), devinfo->ver >= 6)
F(rt_message_type, /* 4+ */ MD(10), MD( 8), /* 12+ */ MD12(10), MD12(8))
/** @} */
@ -1031,8 +1031,8 @@ F(rt_message_type, /* 4+ */ MD(10), MD( 8), /* 12+ */ MD12(10), MD12(8))
* Thread Spawn message function control bits:
* @{
*/
FC(ts_resource_select, /* 4+ */ MD( 4), MD( 4), /* 12+ */ -1, -1, devinfo->gen < 11)
FC(ts_request_type, /* 4+ */ MD( 1), MD( 1), /* 12+ */ -1, -1, devinfo->gen < 11)
FC(ts_resource_select, /* 4+ */ MD( 4), MD( 4), /* 12+ */ -1, -1, devinfo->ver < 11)
FC(ts_request_type, /* 4+ */ MD( 1), MD( 1), /* 12+ */ -1, -1, devinfo->ver < 11)
F(ts_opcode, /* 4+ */ MD( 0), MD( 0), /* 12+ */ MD12(0), MD12(0))
/** @} */
@ -1069,7 +1069,7 @@ static inline uint64_t
brw_inst_imm_uq(ASSERTED const struct gen_device_info *devinfo,
const brw_inst *insn)
{
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
return brw_inst_bits(insn, 127, 64);
}
@ -1137,7 +1137,7 @@ brw_inst_set_imm_df(const struct gen_device_info *devinfo,
(void) devinfo;
dt.d = value;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_bits(insn, 95, 64, dt.u >> 32);
brw_inst_set_bits(insn, 127, 96, dt.u & 0xFFFFFFFF);
} else {
@ -1150,7 +1150,7 @@ brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
brw_inst *insn, uint64_t value)
{
(void) devinfo;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
brw_inst_set_bits(insn, 95, 64, value >> 32);
brw_inst_set_bits(insn, 127, 96, value & 0xFFFFFFFF);
} else {
@ -1198,9 +1198,9 @@ brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
unsigned value) \
{ \
assert((value & ~0x3ff) == 0); \
if (devinfo->gen >= 12) { \
if (devinfo->ver >= 12) { \
brw_inst_set_bits(inst, g12_high, g12_low, value); \
} else if (devinfo->gen >= 8) { \
} else if (devinfo->ver >= 8) { \
brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
} else { \
@ -1211,9 +1211,9 @@ static inline unsigned \
brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
const brw_inst *inst) \
{ \
if (devinfo->gen >= 12) { \
if (devinfo->ver >= 12) { \
return brw_inst_bits(inst, g12_high, g12_low); \
} else if (devinfo->gen >= 8) { \
} else if (devinfo->ver >= 8) { \
return brw_inst_bits(inst, g8_high, g8_low) | \
(brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
} else { \
@ -1232,9 +1232,9 @@ static inline void \
brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
brw_inst *inst, unsigned value) \
{ \
assert(devinfo->gen < 12); \
assert(devinfo->ver < 12); \
assert((value & ~0x3ff) == 0); \
if (devinfo->gen >= 8) { \
if (devinfo->ver >= 8) { \
assert(GET_BITS(value, 3, 0) == 0); \
brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \
brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \
@ -1246,8 +1246,8 @@ static inline unsigned \
brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
const brw_inst *inst) \
{ \
assert(devinfo->gen < 12); \
if (devinfo->gen >= 8) { \
assert(devinfo->ver < 12); \
if (devinfo->ver >= 8) { \
return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \
(brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
} else { \
@ -1360,7 +1360,7 @@ brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
brw_compact_inst *inst, unsigned v) \
{ \
assert(assertions); \
if (devinfo->gen >= 12) \
if (devinfo->ver >= 12) \
brw_compact_inst_set_bits(inst, gen12_high, gen12_low, v); \
else \
brw_compact_inst_set_bits(inst, high, low, v); \
@ -1370,7 +1370,7 @@ brw_compact_inst_##name(const struct gen_device_info *devinfo, \
const brw_compact_inst *inst) \
{ \
assert(assertions); \
if (devinfo->gen >= 12) \
if (devinfo->ver >= 12) \
return brw_compact_inst_bits(inst, gen12_high, gen12_low); \
else \
return brw_compact_inst_bits(inst, high, low); \
@ -1388,14 +1388,14 @@ F(dst_reg_nr, /* 4+ */ 47, 40, /* 12+ */ 23, 16)
F(src1_index, /* 4+ */ 39, 35, /* 12+ */ 55, 52)
F(src0_index, /* 4+ */ 34, 30, /* 12+ */ 51, 48)
F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_inst */
FC(flag_subreg_nr, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->gen <= 6)
FC(flag_subreg_nr, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver <= 6)
F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */
FC(acc_wr_control, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->gen >= 6)
FC(mask_control_ex, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->gen == 5)
FC(acc_wr_control, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->ver >= 6)
FC(mask_control_ex, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->ver == 5)
F(subreg_index, /* 4+ */ 22, 18, /* 12+ */ 39, 35)
F(datatype_index, /* 4+ */ 17, 13, /* 12+ */ 34, 30)
F(control_index, /* 4+ */ 12, 8, /* 12+ */ 28, 24)
FC(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, devinfo->gen >= 12)
FC(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, devinfo->ver >= 12)
F(debug_control, /* 4+ */ 7, 7, /* 12+ */ 7, 7)
F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */
@ -1403,7 +1403,7 @@ static inline unsigned
brw_compact_inst_imm(const struct gen_device_info *devinfo,
const brw_compact_inst *inst)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
return brw_compact_inst_bits(inst, 63, 52);
} else {
return (brw_compact_inst_bits(inst, 39, 35) << 8) |
@ -1415,26 +1415,26 @@ brw_compact_inst_imm(const struct gen_device_info *devinfo,
* (Gen8+) Compacted three-source instructions:
* @{
*/
FC(3src_src2_reg_nr, /* 4+ */ 63, 57, /* 12+ */ 55, 48, devinfo->gen >= 8)
FC(3src_src1_reg_nr, /* 4+ */ 56, 50, /* 12+ */ 63, 56, devinfo->gen >= 8)
FC(3src_src0_reg_nr, /* 4+ */ 49, 43, /* 12+ */ 47, 40, devinfo->gen >= 8)
FC(3src_src2_subreg_nr, /* 4+ */ 42, 40, /* 12+ */ -1, -1, devinfo->gen >= 8)
FC(3src_src1_subreg_nr, /* 4+ */ 39, 37, /* 12+ */ -1, -1, devinfo->gen >= 8)
FC(3src_src0_subreg_nr, /* 4+ */ 36, 34, /* 12+ */ -1, -1, devinfo->gen >= 8)
FC(3src_src2_rep_ctrl, /* 4+ */ 33, 33, /* 12+ */ -1, -1, devinfo->gen >= 8)
FC(3src_src1_rep_ctrl, /* 4+ */ 32, 32, /* 12+ */ -1, -1, devinfo->gen >= 8)
FC(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ -1, -1, devinfo->gen >= 8)
FC(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 7, 7, devinfo->gen >= 8)
FC(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29, devinfo->gen >= 8)
FC(3src_src0_rep_ctrl, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->gen >= 8)
FC(3src_src2_reg_nr, /* 4+ */ 63, 57, /* 12+ */ 55, 48, devinfo->ver >= 8)
FC(3src_src1_reg_nr, /* 4+ */ 56, 50, /* 12+ */ 63, 56, devinfo->ver >= 8)
FC(3src_src0_reg_nr, /* 4+ */ 49, 43, /* 12+ */ 47, 40, devinfo->ver >= 8)
FC(3src_src2_subreg_nr, /* 4+ */ 42, 40, /* 12+ */ -1, -1, devinfo->ver >= 8)
FC(3src_src1_subreg_nr, /* 4+ */ 39, 37, /* 12+ */ -1, -1, devinfo->ver >= 8)
FC(3src_src0_subreg_nr, /* 4+ */ 36, 34, /* 12+ */ -1, -1, devinfo->ver >= 8)
FC(3src_src2_rep_ctrl, /* 4+ */ 33, 33, /* 12+ */ -1, -1, devinfo->ver >= 8)
FC(3src_src1_rep_ctrl, /* 4+ */ 32, 32, /* 12+ */ -1, -1, devinfo->ver >= 8)
FC(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ -1, -1, devinfo->ver >= 8)
FC(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 7, 7, devinfo->ver >= 8)
FC(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29, devinfo->ver >= 8)
FC(3src_src0_rep_ctrl, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver >= 8)
/* Reserved */
FC(3src_dst_reg_nr, /* 4+ */ 18, 12, /* 12+ */ 23, 16, devinfo->gen >= 8)
FC(3src_source_index, /* 4+ */ 11, 10, /* 12+ */ 34, 30, devinfo->gen >= 8)
FC(3src_subreg_index, /* 4+ */ -1, -1, /* 12+ */ 39, 35, devinfo->gen >= 12)
FC(3src_control_index, /* 4+ */ 9, 8, /* 12+ */ 28, 24, devinfo->gen >= 8)
FC(3src_swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, devinfo->gen >= 8)
FC(3src_dst_reg_nr, /* 4+ */ 18, 12, /* 12+ */ 23, 16, devinfo->ver >= 8)
FC(3src_source_index, /* 4+ */ 11, 10, /* 12+ */ 34, 30, devinfo->ver >= 8)
FC(3src_subreg_index, /* 4+ */ -1, -1, /* 12+ */ 39, 35, devinfo->ver >= 12)
FC(3src_control_index, /* 4+ */ 9, 8, /* 12+ */ 28, 24, devinfo->ver >= 8)
FC(3src_swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, devinfo->ver >= 8)
/* Bit 7 is Reserved (for future Opcode expansion) */
FC(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0, devinfo->gen >= 8)
FC(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0, devinfo->ver >= 8)
/** @} */
#undef F

144
src/intel/compiler/brw_ir_performance.cpp
View file

@ -356,10 +356,10 @@ namespace {
case TCS_OPCODE_GET_PRIMITIVE_ID:
case TES_OPCODE_GET_PRIMITIVE_ID:
case SHADER_OPCODE_GET_DSS_ID:
if (devinfo->gen >= 11) {
if (devinfo->ver >= 11) {
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 10, 6 /* XXX */, 14, 0, 0);
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
if (type_sz(info.tx) > 4)
return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4,
0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0);
@ -379,10 +379,10 @@ namespace {
case BRW_OPCODE_ADD:
case BRW_OPCODE_MUL:
case SHADER_OPCODE_MOV_RELOC_IMM:
if (devinfo->gen >= 11) {
if (devinfo->ver >= 11) {
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 10, 6, 14, 0, 0);
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
if (type_sz(info.tx) > 4)
return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4,
0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0);
@ -396,7 +396,7 @@ namespace {
else
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 10, 6 /* XXX */, 16, 0, 0);
} else if (devinfo->gen >= 7) {
} else if (devinfo->ver >= 7) {
if (info.tx == BRW_REGISTER_TYPE_F)
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 14, 10 /* XXX */, 20, 0, 0);
@ -413,26 +413,26 @@ namespace {
case BRW_OPCODE_BFE:
case BRW_OPCODE_BFI2:
case BRW_OPCODE_CSEL:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
else if (devinfo->is_haswell)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->gen >= 7)
else if (devinfo->ver >= 7)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 12, 8 /* XXX */, 18 /* XXX */, 0, 0);
else
abort();
case BRW_OPCODE_MAD:
if (devinfo->gen >= 11) {
if (devinfo->ver >= 11) {
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0);
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
if (type_sz(info.tx) > 4)
return calculate_desc(info, unit_fpu, 0, 4, 1, 0, 4,
0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0);
@ -446,14 +446,14 @@ namespace {
else
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 10, 6 /* XXX */, 16, 0, 0);
} else if (devinfo->gen >= 7) {
} else if (devinfo->ver >= 7) {
if (info.tx == BRW_REGISTER_TYPE_F)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 14, 10 /* XXX */, 20, 0, 0);
else
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 12, 8 /* XXX */, 18, 0, 0);
} else if (devinfo->gen >= 6) {
} else if (devinfo->ver >= 6) {
return calculate_desc(info, unit_fpu, 0, 2 /* XXX */, 1 /* XXX */,
0, 2 /* XXX */,
0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */,
@ -463,16 +463,16 @@ namespace {
}
case BRW_OPCODE_F32TO16:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4,
0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
else if (devinfo->is_haswell)
return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->gen >= 7)
else if (devinfo->ver >= 7)
return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4,
0, 12, 8 /* XXX */, 18 /* XXX */, 0, 0);
else
@ -482,7 +482,7 @@ namespace {
case BRW_OPCODE_DPH:
case BRW_OPCODE_DP3:
case BRW_OPCODE_DP2:
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->is_haswell)
@ -502,7 +502,7 @@ namespace {
case SHADER_OPCODE_POW:
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
switch (info.op) {
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
@ -511,7 +511,7 @@ namespace {
case SHADER_OPCODE_LOG2:
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return calculate_desc(info, unit_em, -2, 4, 0, 0, 4,
0, 16, 0, 0, 0, 0);
else if (devinfo->is_haswell)
@ -522,7 +522,7 @@ namespace {
0, 14, 0, 0, 0, 0);
case SHADER_OPCODE_POW:
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return calculate_desc(info, unit_em, -2, 4, 0, 0, 8,
0, 24, 0, 0, 0, 0);
else if (devinfo->is_haswell)
@ -576,7 +576,7 @@ namespace {
}
case BRW_OPCODE_DO:
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
return calculate_desc(info, unit_null, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
else
@ -590,7 +590,7 @@ namespace {
case BRW_OPCODE_BREAK:
case BRW_OPCODE_CONTINUE:
case BRW_OPCODE_HALT:
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return calculate_desc(info, unit_null, 8, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
else if (devinfo->is_haswell)
@ -601,7 +601,7 @@ namespace {
0, 0, 0, 0, 0, 0);
case FS_OPCODE_LINTERP:
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4,
0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->is_haswell)
@ -612,24 +612,24 @@ namespace {
0, 12, 8 /* XXX */, 18 /* XXX */, 0, 0);
case BRW_OPCODE_LRP:
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 4, 1, 0, 4,
0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->is_haswell)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->gen >= 6)
else if (devinfo->ver >= 6)
return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2,
0, 12, 8 /* XXX */, 18 /* XXX */, 0, 0);
else
abort();
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 20, 6, 0, 0, 6,
0, 10 /* XXX */, 6 /* XXX */,
14 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 16, 6, 0, 0, 6,
0, 8 /* XXX */, 4 /* XXX */,
12 /* XXX */, 0, 0);
@ -637,7 +637,7 @@ namespace {
return calculate_desc(info, unit_fpu, 20, 6, 0, 0, 6,
0, 10 /* XXX */, 6 /* XXX */,
16 /* XXX */, 0, 0);
else if (devinfo->gen >= 7)
else if (devinfo->ver >= 7)
return calculate_desc(info, unit_fpu, 24, 6, 0, 0, 6,
0, 12 /* XXX */, 8 /* XXX */,
18 /* XXX */, 0, 0);
@ -645,11 +645,11 @@ namespace {
abort();
case SHADER_OPCODE_MOV_INDIRECT:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 34, 0, 0, 34, 0,
0, 10 /* XXX */, 6 /* XXX */,
14 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 34, 0, 0, 34, 0,
0, 8 /* XXX */, 4 /* XXX */,
12 /* XXX */, 0, 0);
@ -663,32 +663,32 @@ namespace {
18 /* XXX */, 0, 0);
case SHADER_OPCODE_BROADCAST:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 20 /* XXX */, 0, 0, 4, 0,
0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 18, 0, 0, 4, 0,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
else if (devinfo->is_haswell)
return calculate_desc(info, unit_fpu, 18, 0, 0, 4, 0,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->gen >= 7)
else if (devinfo->ver >= 7)
return calculate_desc(info, unit_fpu, 20, 0, 0, 4, 0,
0, 12, 8 /* XXX */, 18 /* XXX */, 0, 0);
else
abort();
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 2, 0, 0, 2, 0,
0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 2, 0, 0, 2, 0,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
else if (devinfo->is_haswell)
return calculate_desc(info, unit_fpu, 36, 0, 0, 6, 0,
0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0);
else if (devinfo->gen >= 7)
else if (devinfo->ver >= 7)
return calculate_desc(info, unit_fpu, 40, 0, 0, 6, 0,
0, 12, 8 /* XXX */, 18 /* XXX */, 0, 0);
else
@ -696,11 +696,11 @@ namespace {
case SHADER_OPCODE_RND_MODE:
case SHADER_OPCODE_FLOAT_CONTROL_MODE:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 24 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 0, 0, 0, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 20 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 0, 0, 0, 0, 0);
@ -708,7 +708,7 @@ namespace {
return calculate_desc(info, unit_fpu, 24 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 0, 0, 0, 0, 0);
else if (devinfo->gen >= 6)
else if (devinfo->ver >= 6)
return calculate_desc(info, unit_fpu, 28 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 0, 0, 0, 0, 0);
@ -716,12 +716,12 @@ namespace {
abort();
case SHADER_OPCODE_SHUFFLE:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 44 /* XXX */, 0, 0,
44 /* XXX */, 0,
0, 10 /* XXX */, 6 /* XXX */,
14 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 42 /* XXX */, 0, 0,
42 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */,
@ -731,7 +731,7 @@ namespace {
0, 44 /* XXX */,
0, 10 /* XXX */, 6 /* XXX */,
16 /* XXX */, 0, 0);
else if (devinfo->gen >= 6)
else if (devinfo->ver >= 6)
return calculate_desc(info, unit_fpu, 0, 46 /* XXX */, 0,
0, 46 /* XXX */,
0, 12 /* XXX */, 8 /* XXX */,
@ -740,12 +740,12 @@ namespace {
abort();
case SHADER_OPCODE_SEL_EXEC:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 10 /* XXX */, 4 /* XXX */, 0,
0, 4 /* XXX */,
0, 10 /* XXX */, 6 /* XXX */,
14 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 8 /* XXX */, 4 /* XXX */, 0,
0, 4 /* XXX */,
0, 8 /* XXX */, 4 /* XXX */,
@ -762,12 +762,12 @@ namespace {
18 /* XXX */, 0, 0);
case SHADER_OPCODE_QUAD_SWIZZLE:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 0 /* XXX */, 8 /* XXX */, 0,
0, 8 /* XXX */,
0, 10 /* XXX */, 6 /* XXX */,
14 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0 /* XXX */, 8 /* XXX */, 0,
0, 8 /* XXX */,
0, 8 /* XXX */, 4 /* XXX */,
@ -784,10 +784,10 @@ namespace {
18 /* XXX */, 0, 0);
case FS_OPCODE_DDY_FINE:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 0, 14, 0, 0, 4,
0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
else if (devinfo->is_haswell)
@ -798,11 +798,11 @@ namespace {
0, 14, 10 /* XXX */, 20 /* XXX */, 0, 0);
case FS_OPCODE_LOAD_LIVE_CHANNELS:
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
return calculate_desc(info, unit_fpu, 2 /* XXX */, 0, 0,
2 /* XXX */, 0,
0, 0, 0, 10 /* XXX */, 0, 0);
else if (devinfo->gen >= 8)
else if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 0, 2 /* XXX */, 0,
0, 2 /* XXX */,
0, 0, 0, 8 /* XXX */, 0, 0);
@ -810,7 +810,7 @@ namespace {
abort();
case VEC4_OPCODE_PACK_BYTES:
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 4 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
@ -831,7 +831,7 @@ namespace {
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case TES_OPCODE_CREATE_INPUT_READ_HEADER:
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 22 /* XXX */, 0, 0,
6 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
@ -849,7 +849,7 @@ namespace {
case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
case TCS_OPCODE_CREATE_BARRIER_HEADER:
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 32 /* XXX */, 0, 0,
8 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
@ -859,7 +859,7 @@ namespace {
8 /* XXX */, 0,
0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */,
0, 0);
else if (devinfo->gen >= 6)
else if (devinfo->ver >= 6)
return calculate_desc(info, unit_fpu, 44 /* XXX */, 0, 0,
8 /* XXX */, 0,
0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */,
@ -868,7 +868,7 @@ namespace {
abort();
case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
return calculate_desc(info, unit_fpu, 12 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
@ -878,7 +878,7 @@ namespace {
4 /* XXX */, 0,
0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */,
0, 0);
else if (devinfo->gen >= 7)
else if (devinfo->ver >= 7)
return calculate_desc(info, unit_fpu, 16 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */,
@ -930,7 +930,7 @@ namespace {
case SHADER_OPCODE_INTERLOCK:
switch (info.sfid) {
case GEN6_SFID_DATAPORT_RENDER_CACHE:
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
return calculate_desc(info, unit_dp_rc, 2, 0, 0, 30 /* XXX */, 0,
10 /* XXX */, 300 /* XXX */, 0, 0, 0, 0);
else
@ -938,7 +938,7 @@ namespace {
case GEN7_SFID_DATAPORT_DATA_CACHE:
case HSW_SFID_DATAPORT_DATA_CACHE_1:
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
return calculate_desc(info, unit_dp_dc, 2, 0, 0, 30 /* XXX */, 0,
10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0);
else
@ -955,7 +955,7 @@ namespace {
10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0);
case VEC4_OPCODE_UNTYPED_ATOMIC:
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
return calculate_desc(info, unit_dp_dc, 2, 0, 0,
30 /* XXX */, 400 /* XXX */,
10 /* XXX */, 100 /* XXX */, 0, 0,
@ -965,7 +965,7 @@ namespace {
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
return calculate_desc(info, unit_dp_dc, 2, 0, 0,
0, 20 /* XXX */,
10 /* XXX */, 100 /* XXX */, 0, 0,
@ -980,7 +980,7 @@ namespace {
10 /* XXX */, 300 /* XXX */, 0, 0, 0, 0);
case GS_OPCODE_SVB_WRITE:
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
return calculate_desc(info, unit_dp_rc, 2 /* XXX */, 0, 0,
0, 450 /* XXX */,
10 /* XXX */, 300 /* XXX */, 0, 0,
@ -1001,14 +1001,14 @@ namespace {
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
return calculate_desc(info, unit_pi, 2, 0, 0, 14 /* XXX */, 0,
0, 90 /* XXX */, 0, 0, 0, 0);
else
abort();
case SHADER_OPCODE_BARRIER:
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
return calculate_desc(info, unit_gateway, 90 /* XXX */, 0, 0,
0 /* XXX */, 0,
0, 0, 0, 0, 0, 0);
@ -1016,7 +1016,7 @@ namespace {
abort();
case CS_OPCODE_CS_TERMINATE:
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
return calculate_desc(info, unit_spawner, 2, 0, 0, 0 /* XXX */, 0,
10 /* XXX */, 0, 0, 0, 0, 0);
else
@ -1025,7 +1025,7 @@ namespace {
case SHADER_OPCODE_SEND:
switch (info.sfid) {
case GEN6_SFID_DATAPORT_RENDER_CACHE:
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
switch (brw_dp_desc_msg_type(devinfo, info.desc)) {
case GEN7_DATAPORT_RC_TYPED_ATOMIC_OP:
return calculate_desc(info, unit_dp_rc, 2, 0, 0,
@ -1038,7 +1038,7 @@ namespace {
10 /* XXX */, 300 /* XXX */, 0, 0,
0, 0);
}
} else if (devinfo->gen >= 6) {
} else if (devinfo->ver >= 6) {
return calculate_desc(info, unit_dp_rc, 2 /* XXX */, 0, 0,
0, 450 /* XXX */,
10 /* XXX */, 300 /* XXX */, 0, 0, 0, 0);
@ -1046,7 +1046,7 @@ namespace {
abort();
}
case BRW_SFID_SAMPLER: {
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
return calculate_desc(info, unit_sampler, 2, 0, 0, 0, 16,
8, 750, 0, 0, 2, 0);
else
@ -1054,7 +1054,7 @@ namespace {
}
case GEN7_SFID_DATAPORT_DATA_CACHE:
case HSW_SFID_DATAPORT_DATA_CACHE_1:
if (devinfo->gen >= 8 || devinfo->is_haswell) {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
switch (brw_dp_desc_msg_type(devinfo, info.desc)) {
case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
@ -1071,7 +1071,7 @@ namespace {
10 /* XXX */, 100 /* XXX */, 0, 0,
0, 0);
}
} else if (devinfo->gen >= 7) {
} else if (devinfo->ver >= 7) {
switch (brw_dp_desc_msg_type(devinfo, info.desc)) {
case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
return calculate_desc(info, unit_dp_dc, 2, 0, 0,
@ -1189,13 +1189,13 @@ namespace {
assert(i < dependency_id_mrf0 - dependency_id_grf0);
return dependency_id(dependency_id_grf0 + i);
} else if (r.file == MRF && devinfo->gen >= 7) {
} else if (r.file == MRF && devinfo->ver >= 7) {
const unsigned i = GEN7_MRF_HACK_START +
r.nr + r.offset / REG_SIZE + delta;
assert(i < dependency_id_mrf0 - dependency_id_grf0);
return dependency_id(dependency_id_grf0 + i);
} else if (r.file == MRF && devinfo->gen < 7) {
} else if (r.file == MRF && devinfo->ver < 7) {
const unsigned i = (r.nr & ~BRW_MRF_COMPR4) +
r.offset / REG_SIZE + delta;
assert(i < dependency_id_addr0 - dependency_id_mrf0);
@ -1269,7 +1269,7 @@ namespace {
assert(inst->reads_accumulator_implicitly() ||
inst->writes_accumulator_implicitly(devinfo));
const unsigned offset = (inst->group + i) * type_sz(tx) *
(devinfo->gen < 7 || brw_reg_type_is_floating_point(tx) ? 1 : 2);
(devinfo->ver < 7 || brw_reg_type_is_floating_point(tx) ? 1 : 2);
return offset / REG_SIZE % 2;
}
@ -1537,7 +1537,7 @@ namespace {
* previous generations, giving narrower SIMD modes a performance
* advantage in several test-cases with non-uniform discard jumps.
*/
const float discard_weight = (dispatch_width > 16 || s->devinfo->gen < 12 ?
const float discard_weight = (dispatch_width > 16 || s->devinfo->ver < 12 ?
1.0 : 0.5);
const float loop_weight = 10;
unsigned halt_count = 0;

36
src/intel/compiler/brw_nir.c
View file

@ -428,7 +428,7 @@ brw_nir_lower_fs_inputs(nir_shader *nir,
* Centroid interpolation doesn't mean anything on this hardware --
* there is no multisampling.
*/
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
var->data.centroid = false;
var->data.sample = false;
}
@ -439,7 +439,7 @@ brw_nir_lower_fs_inputs(nir_shader *nir,
lower_io_options |= nir_lower_io_force_sample_interpolation;
nir_lower_io(nir, nir_var_shader_in, type_size_vec4, lower_io_options);
if (devinfo->gen >= 11)
if (devinfo->ver >= 11)
nir_lower_interpolation(nir, ~0);
nir_shader_instructions_pass(nir, lower_barycentric_at_offset,
@ -548,7 +548,7 @@ brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
* indirects as scratch all the time, we may easily exceed this limit
* without having any fallback.
*/
if (is_scalar && devinfo->gen <= 7 && !devinfo->is_haswell)
if (is_scalar && devinfo->ver <= 7 && !devinfo->is_haswell)
indirect_mask |= nir_var_function_temp;
return indirect_mask;
@ -630,7 +630,7 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler,
nir->info.stage == MESA_SHADER_TESS_EVAL);
OPT(nir_opt_peephole_select, 0, !is_vec4_tessellation, false);
OPT(nir_opt_peephole_select, 8, !is_vec4_tessellation,
compiler->devinfo->gen >= 6);
compiler->devinfo->ver >= 6);
OPT(nir_opt_intrinsics);
OPT(nir_opt_idiv_const, 32);
@ -708,9 +708,9 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data)
case nir_op_flog2:
case nir_op_fsin:
case nir_op_fcos:
return devinfo->gen < 9 ? 32 : 0;
return devinfo->ver < 9 ? 32 : 0;
default:
if (devinfo->gen >= 11) {
if (devinfo->ver >= 11) {
if (nir_op_infos[alu->op].num_inputs >= 2 &&
alu->dest.dest.ssa.bit_size == 8)
return 16;
@ -739,7 +739,7 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data)
case nir_intrinsic_quad_swap_horizontal:
case nir_intrinsic_quad_swap_vertical:
case nir_intrinsic_quad_swap_diagonal:
if (intrin->src[0].ssa->bit_size == 8 && devinfo->gen >= 11)
if (intrin->src[0].ssa->bit_size == 8 && devinfo->ver >= 11)
return 16;
return 0;
@ -772,7 +772,7 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data)
case nir_instr_type_phi: {
nir_phi_instr *phi = nir_instr_as_phi(instr);
if (devinfo->gen >= 11 && phi->dest.ssa.bit_size == 8)
if (devinfo->ver >= 11 && phi->dest.ssa.bit_size == 8)
return 16;
return 0;
}
@ -811,10 +811,10 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
/* See also brw_nir_trig_workarounds.py */
if (compiler->precise_trig &&
!(devinfo->gen >= 10 || devinfo->is_kabylake))
!(devinfo->ver >= 10 || devinfo->is_kabylake))
OPT(brw_nir_apply_trig_workarounds);
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
OPT(brw_nir_clamp_image_1d_2d_array_sizes);
static const nir_lower_tex_options tex_options = {
@ -1106,7 +1106,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
if (OPT(nir_lower_int64))
brw_nir_optimize(nir, compiler, is_scalar, false);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
/* Try and fuse multiply-adds */
OPT(brw_nir_opt_peephole_ffma);
}
@ -1128,7 +1128,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
nir->info.stage == MESA_SHADER_TESS_EVAL);
OPT(nir_opt_peephole_select, 0, is_vec4_tessellation, false);
OPT(nir_opt_peephole_select, 1, is_vec4_tessellation,
compiler->devinfo->gen >= 6);
compiler->devinfo->ver >= 6);
}
do {
@ -1200,7 +1200,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
* run it last because it stashes data in instr->pass_flags and we don't
* want that to be squashed by other NIR passes.
*/
if (devinfo->gen <= 5)
if (devinfo->ver <= 5)
brw_nir_analyze_boolean_resolves(nir);
nir_sweep(nir);
@ -1224,11 +1224,11 @@ brw_nir_apply_sampler_key(nir_shader *nir,
};
/* Iron Lake and prior require lowering of all rectangle textures */
if (devinfo->gen < 6)
if (devinfo->ver < 6)
tex_options.lower_rect = true;
/* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
if (devinfo->gen < 8) {
if (devinfo->ver < 8) {
tex_options.saturate_s = key_tex->gl_clamp_mask[0];
tex_options.saturate_t = key_tex->gl_clamp_mask[1];
tex_options.saturate_r = key_tex->gl_clamp_mask[2];
@ -1245,7 +1245,7 @@ brw_nir_apply_sampler_key(nir_shader *nir,
}
/* Prior to Haswell, we have to lower gradients on shadow samplers */
tex_options.lower_txd_shadow = devinfo->gen < 8 && !devinfo->is_haswell;
tex_options.lower_txd_shadow = devinfo->ver < 8 && !devinfo->is_haswell;
tex_options.lower_y_uv_external = key_tex->y_uv_image_mask;
tex_options.lower_y_u_v_external = key_tex->y_u_v_image_mask;
@ -1468,9 +1468,9 @@ brw_type_for_nir_type(const struct gen_device_info *devinfo, nir_alu_type type)
case nir_type_float64:
return BRW_REGISTER_TYPE_DF;
case nir_type_int64:
return devinfo->gen < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_Q;
return devinfo->ver < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_Q;
case nir_type_uint64:
return devinfo->gen < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_UQ;
return devinfo->ver < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_UQ;
case nir_type_int16:
return BRW_REGISTER_TYPE_W;
case nir_type_uint16:

2
src/intel/compiler/brw_nir_analyze_ubo_ranges.c
View file

@ -202,7 +202,7 @@ brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
{
const struct gen_device_info *devinfo = compiler->devinfo;
if ((devinfo->gen <= 7 && !devinfo->is_haswell) ||
if ((devinfo->ver <= 7 && !devinfo->is_haswell) ||
!compiler->scalar_stage[nir->info.stage]) {
memset(out_ranges, 0, 4 * sizeof(struct brw_ubo_range));
return;

10
src/intel/compiler/brw_nir_lower_image_load_store.c
View file

@ -200,7 +200,7 @@ image_address(nir_builder *b, const struct gen_device_info *devinfo,
/* Multiply by the Bpp value. */
addr = nir_imul(b, idx, nir_channel(b, stride, 0));
if (devinfo->gen < 8 && !devinfo->is_baytrail) {
if (devinfo->ver < 8 && !devinfo->is_baytrail) {
/* Take into account the two dynamically specified shifts. Both are
* used to implement swizzling of X-tiled surfaces. For Y-tiled
* surfaces only one bit needs to be XOR-ed with bit 6 of the memory
@ -299,7 +299,7 @@ convert_color_for_load(nir_builder *b, const struct gen_device_info *devinfo,
* their least significant bits. However, the data in the high bits is
* garbage so we have to discard it.
*/
if (devinfo->gen == 7 && !devinfo->is_haswell &&
if (devinfo->ver == 7 && !devinfo->is_haswell &&
(lower_fmt == ISL_FORMAT_R16_UINT ||
lower_fmt == ISL_FORMAT_R8_UINT))
color = nir_format_mask_uvec(b, color, lower.bits);
@ -408,7 +408,7 @@ lower_image_load_instr(nir_builder *b,
nir_ssa_def *coord = intrin->src[1].ssa;
nir_ssa_def *do_load = image_coord_is_in_bounds(b, deref, coord);
if (devinfo->gen == 7 && !devinfo->is_haswell) {
if (devinfo->ver == 7 && !devinfo->is_haswell) {
/* Check whether the first stride component (i.e. the Bpp value)
* is greater than four, what on Gen7 indicates that a surface of
* type RAW has been bound for untyped access. Reading or writing
@ -556,7 +556,7 @@ lower_image_store_instr(nir_builder *b,
nir_ssa_def *coord = intrin->src[1].ssa;
nir_ssa_def *do_store = image_coord_is_in_bounds(b, deref, coord);
if (devinfo->gen == 7 && !devinfo->is_haswell) {
if (devinfo->ver == 7 && !devinfo->is_haswell) {
/* Check whether the first stride component (i.e. the Bpp value)
* is greater than four, what on Gen7 indicates that a surface of
* type RAW has been bound for untyped access. Reading or writing
@ -595,7 +595,7 @@ lower_image_atomic_instr(nir_builder *b,
const struct gen_device_info *devinfo,
nir_intrinsic_instr *intrin)
{
if (devinfo->is_haswell || devinfo->gen >= 8)
if (devinfo->is_haswell || devinfo->ver >= 8)
return false;
nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);

38
src/intel/compiler/brw_reg_type.c
View file

@ -293,19 +293,19 @@ brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
{
const struct hw_type *table;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
assert(type < ARRAY_SIZE(gen12_hw_type));
table = gen12_hw_type;
} else if (devinfo->gen >= 11) {
} else if (devinfo->ver >= 11) {
assert(type < ARRAY_SIZE(gen11_hw_type));
table = gen11_hw_type;
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
assert(type < ARRAY_SIZE(gen8_hw_type));
table = gen8_hw_type;
} else if (devinfo->gen >= 7) {
} else if (devinfo->ver >= 7) {
assert(type < ARRAY_SIZE(gen7_hw_type));
table = gen7_hw_type;
} else if (devinfo->gen >= 6) {
} else if (devinfo->ver >= 6) {
assert(type < ARRAY_SIZE(gen6_hw_type));
table = gen6_hw_type;
} else {
@ -333,15 +333,15 @@ brw_hw_type_to_reg_type(const struct gen_device_info *devinfo,
{
const struct hw_type *table;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
table = gen12_hw_type;
} else if (devinfo->gen >= 11) {
} else if (devinfo->ver >= 11) {
table = gen11_hw_type;
} else if (devinfo->gen >= 8) {
} else if (devinfo->ver >= 8) {
table = gen8_hw_type;
} else if (devinfo->gen >= 7) {
} else if (devinfo->ver >= 7) {
table = gen7_hw_type;
} else if (devinfo->gen >= 6) {
} else if (devinfo->ver >= 6) {
table = gen6_hw_type;
} else {
table = gen4_hw_type;
@ -373,10 +373,10 @@ brw_reg_type_to_a16_hw_3src_type(const struct gen_device_info *devinfo,
{
const struct hw_3src_type *table;
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
assert(type < ARRAY_SIZE(gen8_hw_3src_type));
table = gen8_hw_3src_type;
} else if (devinfo->gen >= 7) {
} else if (devinfo->ver >= 7) {
assert(type < ARRAY_SIZE(gen7_hw_3src_type));
table = gen7_hw_3src_type;
} else {
@ -396,10 +396,10 @@ unsigned
brw_reg_type_to_a1_hw_3src_type(const struct gen_device_info *devinfo,
enum brw_reg_type type)
{
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
assert(type < ARRAY_SIZE(gen12_hw_3src_type));
return gen12_hw_3src_type[type].reg_type;
} else if (devinfo->gen >= 11) {
} else if (devinfo->ver >= 11) {
assert(type < ARRAY_SIZE(gen11_hw_3src_type));
return gen11_hw_3src_type[type].reg_type;
} else {
@ -418,11 +418,11 @@ brw_a16_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
{
const struct hw_3src_type *table = NULL;
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
table = gen8_hw_3src_type;
} else if (devinfo->gen >= 7) {
} else if (devinfo->ver >= 7) {
table = gen7_hw_3src_type;
} else if (devinfo->gen >= 6) {
} else if (devinfo->ver >= 6) {
table = gen6_hw_3src_type;
}
@ -442,8 +442,8 @@ enum brw_reg_type
brw_a1_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
unsigned hw_type, unsigned exec_type)
{
const struct hw_3src_type *table = (devinfo->gen >= 12 ? gen12_hw_3src_type :
devinfo->gen >= 11 ? gen11_hw_3src_type :
const struct hw_3src_type *table = (devinfo->ver >= 12 ? gen12_hw_3src_type :
devinfo->ver >= 11 ? gen11_hw_3src_type :
gen10_hw_3src_align1_type);
for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {

10
src/intel/compiler/brw_schedule_instructions.cpp
View file

@ -934,7 +934,7 @@ schedule_node::schedule_node(backend_instruction *inst,
*/
if (!sched->post_reg_alloc)
this->latency = 1;
else if (devinfo->gen >= 6)
else if (devinfo->ver >= 6)
set_latency_gen7(devinfo->is_haswell);
else
set_latency_gen4();
@ -1101,7 +1101,7 @@ fs_instruction_scheduler::calculate_deps()
* GRF registers.
*/
schedule_node **last_grf_write;
schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->gen)];
schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->ver)];
schedule_node *last_conditional_mod[8] = {};
schedule_node *last_accumulator_write = NULL;
/* Fixed HW registers are assumed to be separate from the virtual
@ -1365,7 +1365,7 @@ void
vec4_instruction_scheduler::calculate_deps()
{
schedule_node *last_grf_write[grf_count];
schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->gen)];
schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->ver)];
schedule_node *last_conditional_mod = NULL;
schedule_node *last_accumulator_write = NULL;
/* Fixed HW registers are assumed to be separate from the virtual
@ -1613,7 +1613,7 @@ fs_instruction_scheduler::choose_instruction_to_schedule()
* then the MRFs for the next SEND, then the next SEND, then the
* MRFs, etc., without ever consuming the results of a send.
*/
if (v->devinfo->gen < 7) {
if (v->devinfo->ver < 7) {
fs_inst *chosen_inst = (fs_inst *)chosen->inst;
/* We use size_written > 4 * exec_size as our test for the kind
@ -1788,7 +1788,7 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
* the next math instruction isn't going to make progress until the first
* is done.
*/
if (devinfo->gen < 6 && chosen->inst->is_math()) {
if (devinfo->ver < 6 && chosen->inst->is_math()) {
foreach_in_list(schedule_node, n, &instructions) {
if (n->inst->is_math())
n->unblocked_time = MAX2(n->unblocked_time,

10
src/intel/compiler/brw_shader.cpp
View file

@ -168,16 +168,16 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
/* The DO instruction doesn't exist on Gen6+, but we use it to mark the
* start of a loop in the IR.
*/
if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
if (devinfo->ver >= 6 && op == BRW_OPCODE_DO)
return "do";
/* The following conversion opcodes doesn't exist on Gen8+, but we use
* then to mark that we want to do the conversion.
*/
if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
if (devinfo->ver > 7 && op == BRW_OPCODE_F32TO16)
return "f32to16";
if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
if (devinfo->ver > 7 && op == BRW_OPCODE_F16TO32)
return "f16to32";
assert(brw_opcode_desc(devinfo, op)->name);
@ -1082,11 +1082,11 @@ bool
backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
{
return writes_accumulator ||
(devinfo->gen < 6 &&
(devinfo->ver < 6 &&
((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
(opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
(opcode == FS_OPCODE_LINTERP &&
(!devinfo->has_pln || devinfo->gen <= 6));
(!devinfo->has_pln || devinfo->ver <= 6));
}
bool

34
src/intel/compiler/brw_vec4.cpp
View file

@ -238,7 +238,7 @@ vec4_instruction::size_read(unsigned arg) const
bool
vec4_instruction::can_do_source_mods(const struct gen_device_info *devinfo)
{
if (devinfo->gen == 6 && is_math())
if (devinfo->ver == 6 && is_math())
return false;
if (is_send_from_grf())
@ -296,7 +296,7 @@ vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
/* The MATH instruction on Gen6 only executes in align1 mode, which does
* not support writemasking.
*/
if (devinfo->gen == 6 && is_math())
if (devinfo->ver == 6 && is_math())
return false;
if (is_tex())
@ -1008,7 +1008,7 @@ vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)
#define IS_64BIT(reg) (reg.file != BAD_FILE && type_sz(reg.type) == 8)
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
if (IS_64BIT(inst->dst) || IS_64BIT(inst->src[0]) ||
IS_64BIT(inst->src[1]) || IS_64BIT(inst->src[2]))
return true;
@ -1132,7 +1132,7 @@ vec4_instruction::can_reswizzle(const struct gen_device_info *devinfo,
/* Gen6 MATH instructions can not execute in align16 mode, so swizzles
* are not allowed.
*/
if (devinfo->gen == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW)
if (devinfo->ver == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW)
return false;
/* If we write to the flag register changing the swizzle would change
@ -1303,7 +1303,7 @@ vec4_visitor::opt_register_coalesce()
if (scan_inst->mlen)
break;
if (devinfo->gen == 6) {
if (devinfo->ver == 6) {
/* gen6 math instructions must have the destination be
* VGRF, so no compute-to-MRF for them.
*/
@ -1608,7 +1608,7 @@ vec4_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) c
if (inst->conditional_mod) {
fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
if (!inst->predicate &&
(devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
(devinfo->ver < 5 || (inst->opcode != BRW_OPCODE_SEL &&
inst->opcode != BRW_OPCODE_CSEL &&
inst->opcode != BRW_OPCODE_IF &&
inst->opcode != BRW_OPCODE_WHILE))) {
@ -1815,7 +1815,7 @@ vec4_visitor::setup_uniforms(int reg)
/* The pre-gen6 VS requires that some push constants get loaded no
* matter what, or the GPU would hang.
*/
if (devinfo->gen < 6 && this->uniforms == 0) {
if (devinfo->ver < 6 && this->uniforms == 0) {
brw_stage_prog_data_add_params(stage_prog_data, 4);
for (unsigned int i = 0; i < 4; i++) {
unsigned int slot = this->uniforms * 4 + i;
@ -1860,7 +1860,7 @@ vec4_vs_visitor::setup_payload(void)
bool
vec4_visitor::lower_minmax()
{
assert(devinfo->gen < 6);
assert(devinfo->ver < 6);
bool progress = false;
@ -1898,7 +1898,7 @@ vec4_visitor::lower_minmax()
src_reg
vec4_visitor::get_timestamp()
{
assert(devinfo->gen == 7);
assert(devinfo->ver == 7);
src_reg ts = src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_TIMESTAMP,
@ -2127,7 +2127,7 @@ vec4_visitor::convert_to_hw_regs()
case MRF:
reg = byte_offset(brw_message_reg(dst.nr), dst.offset);
assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
reg.type = dst.type;
reg.writemask = dst.writemask;
break;
@ -2192,7 +2192,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
* 2 registers. We only need to care about this in gen7 because that is the
* only hardware that implements fp64 in Align16.
*/
if (devinfo->gen == 7 && inst->size_written > REG_SIZE) {
if (devinfo->ver == 7 && inst->size_written > REG_SIZE) {
/* Align16 8-wide double-precision SEL does not work well. Verified
* empirically.
*/
@ -2227,7 +2227,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
* compressed instruction bug in gen7, which is another reason to enforce
* this limit).
*/
if (devinfo->gen == 7 && !devinfo->is_haswell &&
if (devinfo->ver == 7 && !devinfo->is_haswell &&
(get_exec_type_size(inst) == 8 || type_sz(inst->dst.type) == 8))
lowered_width = MIN2(lowered_width, 4);
@ -2438,7 +2438,7 @@ vec4_visitor::is_supported_64bit_region(vec4_instruction *inst, unsigned arg)
case BRW_SWIZZLE_YXWZ:
return true;
default:
return devinfo->gen == 7 && is_gen7_supported_64bit_swizzle(inst, arg);
return devinfo->ver == 7 && is_gen7_supported_64bit_swizzle(inst, arg);
}
}
@ -2632,7 +2632,7 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg,
}
/* All gen7-specific supported swizzles require the vstride=0 exploit */
if (devinfo->gen == 7 && is_gen7_supported_64bit_swizzle(inst, arg))
if (devinfo->ver == 7 && is_gen7_supported_64bit_swizzle(inst, arg))
hw_reg->vstride = BRW_VERTICAL_STRIDE_0;
/* Any 64-bit source with an offset at 16B is intended to address the
@ -2643,7 +2643,7 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg,
* execsize > 4
*/
if (hw_reg->subnr % REG_SIZE == 16) {
assert(devinfo->gen == 7);
assert(devinfo->ver == 7);
hw_reg->vstride = BRW_VERTICAL_STRIDE_0;
}
@ -2743,7 +2743,7 @@ vec4_visitor::run()
OPT(dead_code_eliminate);
}
if (devinfo->gen <= 5 && OPT(lower_minmax)) {
if (devinfo->ver <= 5 && OPT(lower_minmax)) {
OPT(opt_cmod_propagation);
OPT(opt_cse);
OPT(opt_copy_propagation);
@ -2931,7 +2931,7 @@ brw_compile_vs(const struct brw_compiler *compiler,
const unsigned vue_entries =
MAX2(nr_attribute_slots, (unsigned)prog_data->base.vue_map.num_slots);
if (compiler->devinfo->gen == 6) {
if (compiler->devinfo->ver == 6) {
prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 8);
} else {
prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 4);

12
src/intel/compiler/brw_vec4_builder.h
View file

@ -510,7 +510,7 @@ namespace brw {
IF(const src_reg &src0, const src_reg &src1,
brw_conditional_mod condition) const
{
assert(shader->devinfo->gen == 6);
assert(shader->devinfo->ver == 6);
return set_condmod(condition,
emit(BRW_OPCODE_IF,
null_reg_d(),
@ -528,7 +528,7 @@ namespace brw {
/* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
* we need to reorder the operands.
*/
assert(shader->devinfo->gen >= 6 && shader->devinfo->gen <= 9);
assert(shader->devinfo->ver >= 6 && shader->devinfo->ver <= 9);
return emit(BRW_OPCODE_LRP, dst, a, y, x);
}
@ -597,8 +597,8 @@ namespace brw {
* For gen7, keep the operand as-is, except if immediate, which gen7 still
* can't use.
*/
if (shader->devinfo->gen == 6 ||
(shader->devinfo->gen == 7 && src.file == IMM)) {
if (shader->devinfo->ver == 6 ||
(shader->devinfo->ver == 7 && src.file == IMM)) {
const dst_reg tmp = vgrf(src.type);
MOV(tmp, src);
return src_reg(tmp);
@ -613,13 +613,13 @@ namespace brw {
instruction *
fix_math_instruction(instruction *inst) const
{
if (shader->devinfo->gen == 6 &&
if (shader->devinfo->ver == 6 &&
inst->dst.writemask != WRITEMASK_XYZW) {
const dst_reg tmp = vgrf(inst->dst.type);
MOV(inst->dst, src_reg(tmp));
inst->dst = tmp;
} else if (shader->devinfo->gen < 6) {
} else if (shader->devinfo->ver < 6) {
const unsigned sources = (inst->src[1].file == BAD_FILE ? 1 : 2);
inst->base_mrf = 1;
inst->mlen = sources;

2
src/intel/compiler/brw_vec4_copy_propagation.cpp
View file

@ -354,7 +354,7 @@ try_copy_propagate(const struct gen_device_info *devinfo,
/* Reject cases that would violate register regioning restrictions. */
if ((value.file == UNIFORM || value.swizzle != BRW_SWIZZLE_XYZW) &&
((devinfo->gen == 6 && inst->is_math()) ||
((devinfo->ver == 6 && inst->is_math()) ||
inst->is_send_from_grf() ||
inst->uses_indirect_addressing())) {
return false;

90
src/intel/compiler/brw_vec4_generator.cpp
View file

@ -117,7 +117,7 @@ generate_tex(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
int msg_type = -1;
if (devinfo->gen >= 5) {
if (devinfo->ver >= 5) {
switch (inst->opcode) {
case SHADER_OPCODE_TEX:
case SHADER_OPCODE_TXL:
@ -140,13 +140,13 @@ generate_tex(struct brw_codegen *p,
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_CMS:
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
else
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_MCS:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
break;
case SHADER_OPCODE_TXS:
@ -211,7 +211,7 @@ generate_tex(struct brw_codegen *p,
* use an implied move from g0 to the first message register.
*/
if (inst->header_size != 0) {
if (devinfo->gen < 6 && !inst->offset) {
if (devinfo->ver < 6 && !inst->offset) {
/* Set up an implied move from g0 to the MRF. */
src = brw_vec8_grf(0, 0);
} else {
@ -437,7 +437,7 @@ generate_gs_set_write_offset(struct brw_codegen *p,
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
assert(p->devinfo->gen >= 7 &&
assert(p->devinfo->ver >= 7 &&
src1.file == BRW_IMMEDIATE_VALUE &&
src1.type == BRW_REGISTER_TYPE_UD &&
src1.ud <= USHRT_MAX);
@ -1090,7 +1090,7 @@ generate_oword_dual_block_offsets(struct brw_codegen *p,
{
int second_vertex_offset;
if (p->devinfo->gen >= 6)
if (p->devinfo->ver >= 6)
second_vertex_offset = 1;
else
second_vertex_offset = 16;
@ -1156,16 +1156,16 @@ generate_scratch_read(struct brw_codegen *p,
uint32_t msg_type;
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else if (devinfo->gen == 5 || devinfo->is_g4x)
else if (devinfo->ver == 5 || devinfo->is_g4x)
msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else
msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
const unsigned target_cache =
devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_READ;
/* Each of the 8 channel enables is considered for whether each
@ -1175,7 +1175,7 @@ generate_scratch_read(struct brw_codegen *p,
brw_inst_set_sfid(devinfo, send, target_cache);
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (devinfo->gen < 6)
if (devinfo->ver < 6)
brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
brw_set_desc(p, send,
brw_message_desc(devinfo, 2, 1, true) |
@ -1194,8 +1194,8 @@ generate_scratch_write(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
(devinfo->ver >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_WRITE);
struct brw_reg header = brw_vec8_grf(0, 0);
bool write_commit;
@ -1216,9 +1216,9 @@ generate_scratch_write(struct brw_codegen *p,
uint32_t msg_type;
if (devinfo->gen >= 7)
if (devinfo->ver >= 7)
msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
else if (devinfo->gen == 6)
else if (devinfo->ver == 6)
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
else
msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
@ -1230,7 +1230,7 @@ generate_scratch_write(struct brw_codegen *p,
* guaranteed and write commits only matter for inter-thread
* synchronization.
*/
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
write_commit = false;
} else {
/* The visitor set up our destination register to be g0. This
@ -1251,7 +1251,7 @@ generate_scratch_write(struct brw_codegen *p,
brw_inst_set_sfid(p->devinfo, send, target_cache);
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (devinfo->gen < 6)
if (devinfo->ver < 6)
brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
brw_set_desc(p, send,
brw_message_desc(devinfo, 3, write_commit, true) |
@ -1272,7 +1272,7 @@ generate_pull_constant_load(struct brw_codegen *p,
{
const struct gen_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_SAMPLER_CACHE :
(devinfo->ver >= 6 ? GEN6_SFID_DATAPORT_SAMPLER_CACHE :
BRW_SFID_DATAPORT_READ);
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
@ -1282,7 +1282,7 @@ generate_pull_constant_load(struct brw_codegen *p,
gen6_resolve_implied_move(p, &header, inst->base_mrf);
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
if (offset.file == BRW_IMMEDIATE_VALUE) {
brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
BRW_REGISTER_TYPE_D),
@ -1300,9 +1300,9 @@ generate_pull_constant_load(struct brw_codegen *p,
uint32_t msg_type;
if (devinfo->gen >= 6)
if (devinfo->ver >= 6)
msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else if (devinfo->gen == 5 || devinfo->is_g4x)
else if (devinfo->ver == 5 || devinfo->is_g4x)
msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else
msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
@ -1314,7 +1314,7 @@ generate_pull_constant_load(struct brw_codegen *p,
brw_inst_set_sfid(devinfo, send, target_cache);
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (devinfo->gen < 6)
if (devinfo->ver < 6)
brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
brw_set_desc(p, send,
brw_message_desc(devinfo, 2, 1, true) |
@ -1331,7 +1331,7 @@ generate_get_buffer_size(struct brw_codegen *p,
struct brw_reg src,
struct brw_reg surf_index)
{
assert(p->devinfo->gen >= 7);
assert(p->devinfo->ver >= 7);
assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
surf_index.file == BRW_IMMEDIATE_VALUE);
@ -1409,7 +1409,7 @@ generate_mov_indirect(struct brw_codegen *p,
struct brw_reg indirect)
{
assert(indirect.type == BRW_REGISTER_TYPE_UD);
assert(p->devinfo->gen >= 6);
assert(p->devinfo->ver >= 6);
unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2);
@ -1522,7 +1522,7 @@ generate_code(struct brw_codegen *p,
inst->opcode != VEC4_OPCODE_SET_HIGH_32BIT;
unsigned exec_size = inst->exec_size;
if (devinfo->gen == 7 && !devinfo->is_haswell && is_df)
if (devinfo->ver == 7 && !devinfo->is_haswell && is_df)
exec_size *= 2;
brw_set_default_exec_size(p, cvt(exec_size) - 1);
@ -1530,7 +1530,7 @@ generate_code(struct brw_codegen *p,
if (!inst->force_writemask_all)
brw_set_default_group(p, inst->group);
assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->ver));
assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
unsigned pre_emit_nr_insn = p->nr_insn;
@ -1551,7 +1551,7 @@ generate_code(struct brw_codegen *p,
break;
case BRW_OPCODE_MAD:
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
brw_MAD(p, dst, src[0], src[1], src[2]);
break;
@ -1617,31 +1617,31 @@ generate_code(struct brw_codegen *p,
break;
case BRW_OPCODE_F32TO16:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_F32TO16(p, dst, src[0]);
break;
case BRW_OPCODE_F16TO32:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_F16TO32(p, dst, src[0]);
break;
case BRW_OPCODE_LRP:
assert(devinfo->gen >= 6);
assert(devinfo->ver >= 6);
brw_LRP(p, dst, src[0], src[1], src[2]);
break;
case BRW_OPCODE_BFREV:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
case BRW_OPCODE_FBH:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_FBH(p, retype(dst, src[0].type), src[0]);
break;
case BRW_OPCODE_FBL:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
@ -1649,16 +1649,16 @@ generate_code(struct brw_codegen *p,
brw_LZD(p, dst, src[0]);
break;
case BRW_OPCODE_CBIT:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
case BRW_OPCODE_ADDC:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_ADDC(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SUBB:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_SUBB(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_MAC:
@ -1666,23 +1666,23 @@ generate_code(struct brw_codegen *p,
break;
case BRW_OPCODE_BFE:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_BFE(p, dst, src[0], src[1], src[2]);
break;
case BRW_OPCODE_BFI1:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_BFI1(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_BFI2:
assert(devinfo->gen >= 7);
assert(devinfo->ver >= 7);
brw_BFI2(p, dst, src[0], src[1], src[2]);
break;
case BRW_OPCODE_IF:
if (!inst->src[0].is_null()) {
/* The instruction has an embedded compare (only allowed on gen6) */
assert(devinfo->gen == 6);
assert(devinfo->ver == 6);
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
} else {
brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
@ -1723,10 +1723,10 @@ generate_code(struct brw_codegen *p,
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
brw_null_reg());
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
generate_math_gen6(p, inst, dst, src[0], brw_null_reg());
} else {
generate_math1_gen4(p, inst, dst, src[0]);
@ -1738,9 +1738,9 @@ generate_code(struct brw_codegen *p,
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
} else if (devinfo->gen == 6) {
} else if (devinfo->ver == 6) {
generate_math_gen6(p, inst, dst, src[0], src[1]);
} else {
generate_math2_gen4(p, inst, dst, src[0], src[1]);
@ -1956,7 +1956,7 @@ generate_code(struct brw_codegen *p,
* need to explicitly set stride 2, but 1.
*/
struct brw_reg spread_dst;
if (devinfo->gen == 7 && !devinfo->is_haswell)
if (devinfo->ver == 7 && !devinfo->is_haswell)
spread_dst = stride(dst, 8, 4, 1);
else
spread_dst = stride(dst, 8, 4, 2);

20
src/intel/compiler/brw_vec4_gs_visitor.cpp
View file

@ -631,11 +631,11 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
prog_data->invocations = nir->info.gs.invocations;
if (compiler->devinfo->gen >= 8)
if (compiler->devinfo->ver >= 8)
nir_gs_count_vertices_and_primitives(
nir, &prog_data->static_vertex_count, nullptr, 1u);
if (compiler->devinfo->gen >= 7) {
if (compiler->devinfo->ver >= 7) {
if (nir->info.gs.output_primitive == GL_POINTS) {
/* When the output type is points, the geometry shader may output data
* to multiple streams, and EndPrimitive() has no effect. So we
@ -723,7 +723,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
*
*/
unsigned output_vertex_size_bytes = prog_data->base.vue_map.num_slots * 16;
assert(compiler->devinfo->gen == 6 ||
assert(compiler->devinfo->ver == 6 ||
output_vertex_size_bytes <= GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES);
prog_data->output_vertex_size_hwords =
ALIGN(output_vertex_size_bytes, 32) / 32;
@ -761,7 +761,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
* a single vertex. Also, gen6 does not have a control data header.
*/
unsigned output_size_bytes;
if (compiler->devinfo->gen >= 7) {
if (compiler->devinfo->ver >= 7) {
output_size_bytes =
prog_data->output_vertex_size_hwords * 32 * nir->info.gs.vertices_out;
output_size_bytes += 32 * prog_data->control_data_header_size_hwords;
@ -772,7 +772,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
/* Broadwell stores "Vertex Count" as a full 8 DWord (32 byte) URB output,
* which comes before the control header.
*/
if (compiler->devinfo->gen >= 8)
if (compiler->devinfo->ver >= 8)
output_size_bytes += 32;
/* Shaders can technically set max_vertices = 0, at which point we
@ -783,7 +783,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
output_size_bytes = 1;
unsigned max_output_size_bytes = GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES;
if (compiler->devinfo->gen == 6)
if (compiler->devinfo->ver == 6)
max_output_size_bytes = GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES;
if (output_size_bytes > max_output_size_bytes)
return NULL;
@ -792,7 +792,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
/* URB entry sizes are stored as a multiple of 64 bytes in gen7+ and
* a multiple of 128 bytes in gen6.
*/
if (compiler->devinfo->gen >= 7) {
if (compiler->devinfo->ver >= 7) {
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
} else {
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 128) / 128;
@ -847,7 +847,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
return NULL;
}
if (compiler->devinfo->gen >= 7) {
if (compiler->devinfo->ver >= 7) {
/* Compile the geometry shader in DUAL_OBJECT dispatch mode, if we can do
* so without spilling. If the GS invocations count > 1, then we can't use
* dual object mode.
@ -918,7 +918,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
* mode is more performant when invocations > 1. Gen6 only supports
* SINGLE mode.
*/
if (prog_data->invocations <= 1 || compiler->devinfo->gen < 7)
if (prog_data->invocations <= 1 || compiler->devinfo->ver < 7)
prog_data->base.dispatch_mode = DISPATCH_MODE_4X1_SINGLE;
else
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_INSTANCE;
@ -926,7 +926,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
brw::vec4_gs_visitor *gs = NULL;
const unsigned *ret = NULL;
if (compiler->devinfo->gen >= 7)
if (compiler->devinfo->ver >= 7)
gs = new brw::vec4_gs_visitor(compiler, log_data, &c, prog_data,
nir, mem_ctx, false /* no_spills */,
shader_time_index, debug_enabled);

22
src/intel/compiler/brw_vec4_nir.cpp
View file

@ -283,7 +283,7 @@ static src_reg
setup_imm_df(const vec4_builder &bld, double v)
{
const gen_device_info *devinfo = bld.shader->devinfo;
assert(devinfo->gen == 7);
assert(devinfo->ver == 7);
/* gen7.5 does not support DF immediates straighforward but the DIM
* instruction allows to set the 64-bit immediate value.
@ -460,7 +460,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
}
case nir_intrinsic_store_ssbo: {
assert(devinfo->gen == 7);
assert(devinfo->ver == 7);
/* brw_nir_lower_mem_access_bit_sizes takes care of this */
assert(nir_src_bit_size(instr->src[0]) == 32);
@ -522,7 +522,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
}
case nir_intrinsic_load_ssbo: {
assert(devinfo->gen == 7);
assert(devinfo->ver == 7);
/* brw_nir_lower_mem_access_bit_sizes takes care of this */
assert(nir_dest_bit_size(instr->dest) == 32);
@ -1202,14 +1202,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
if (nir_src_is_const(instr->src[0].src) &&
nir_alu_instr_src_read_mask(instr, 0) == 1 &&
const_src_fits_in_16_bits(instr->src[0].src, op[0].type)) {
if (devinfo->gen < 7)
if (devinfo->ver < 7)
emit(MUL(dst, op[0], op[1]));
else
emit(MUL(dst, op[1], op[0]));
} else if (nir_src_is_const(instr->src[1].src) &&
nir_alu_instr_src_read_mask(instr, 1) == 1 &&
const_src_fits_in_16_bits(instr->src[1].src, op[1].type)) {
if (devinfo->gen < 7)
if (devinfo->ver < 7)
emit(MUL(dst, op[1], op[0]));
else
emit(MUL(dst, op[0], op[1]));
@ -1335,7 +1335,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_ftrunc:
inst = emit(RNDZ(dst, op[0]));
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
inst->conditional_mod = BRW_CONDITIONAL_R;
inst = emit(ADD(dst, src_reg(dst), brw_imm_f(1.0f)));
inst->predicate = BRW_PREDICATE_NORMAL;
@ -1367,7 +1367,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_fround_even:
inst = emit(RNDE(dst, op[0]));
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
inst->conditional_mod = BRW_CONDITIONAL_R;
inst = emit(ADD(dst, src_reg(dst), brw_imm_f(1.0f)));
inst->predicate = BRW_PREDICATE_NORMAL;
@ -1670,7 +1670,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
vec4_builder bld = vec4_builder(this).at_end();
src_reg src(dst);
if (devinfo->gen < 7) {
if (devinfo->ver < 7) {
emit_find_msb_using_lzd(bld, dst, op[0], true);
} else {
emit(FBH(retype(dst, BRW_REGISTER_TYPE_UD), op[0]));
@ -1693,7 +1693,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
assert(nir_dest_bit_size(instr->dest.dest) < 64);
vec4_builder bld = vec4_builder(this).at_end();
if (devinfo->gen < 7) {
if (devinfo->ver < 7) {
dst_reg temp = bld.vgrf(BRW_REGISTER_TYPE_D);
/* (x & -x) generates a value that consists of only the LSB of x.
@ -1894,7 +1894,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
/* If we need to do a boolean resolve, replace the result with -(x & 1)
* to sign extend the low bit to 0/~0
*/
if (devinfo->gen <= 5 &&
if (devinfo->ver <= 5 &&
(instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) ==
BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
dst_reg masked = dst_reg(this, glsl_type::int_type);
@ -2068,7 +2068,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
if (instr->op == nir_texop_txf_ms ||
instr->op == nir_texop_samples_identical) {
assert(coord_type != NULL);
if (devinfo->gen >= 7 &&
if (devinfo->ver >= 7 &&
key_tex->compressed_multisample_layout_mask & (1 << texture)) {
mcs = emit_mcs_fetch(coord_type, coordinate, texture_reg);
} else {

4
src/intel/compiler/brw_vec4_reg_allocate.cpp
View file

@ -92,7 +92,7 @@ extern "C" void
brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
{
int base_reg_count =
compiler->devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
compiler->devinfo->ver >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
/* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
* SEND-from-GRF sources cannot be split, so we also need classes for each
@ -114,7 +114,7 @@ brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
compiler->vec4_reg_set.ra_reg_to_grf = ralloc_array(compiler, uint8_t, ra_reg_count);
ralloc_free(compiler->vec4_reg_set.regs);
compiler->vec4_reg_set.regs = ra_alloc_reg_set(compiler, ra_reg_count, false);
if (compiler->devinfo->gen >= 6)
if (compiler->devinfo->ver >= 6)
ra_set_allocate_round_robin(compiler->vec4_reg_set.regs);
ralloc_free(compiler->vec4_reg_set.classes);
compiler->vec4_reg_set.classes = ralloc_array(compiler, int, class_count);

6
src/intel/compiler/brw_vec4_tcs.cpp
View file

@ -105,7 +105,7 @@ vec4_tcs_visitor::emit_thread_end()
emit(BRW_OPCODE_ENDIF);
}
if (devinfo->gen == 7) {
if (devinfo->ver == 7) {
struct brw_tcs_prog_data *tcs_prog_data =
(struct brw_tcs_prog_data *) prog_data;
@ -399,8 +399,8 @@ brw_compile_tcs(const struct brw_compiler *compiler,
prog_data->patch_count_threshold = brw::get_patch_count_threshold(key->input_vertices);
if (compiler->use_tcs_8_patch &&
nir->info.tess.tcs_vertices_out <= (devinfo->gen >= 12 ? 32 : 16) &&
2 + has_primitive_id + key->input_vertices <= (devinfo->gen >= 12 ? 63 : 31)) {
nir->info.tess.tcs_vertices_out <= (devinfo->ver >= 12 ? 32 : 16) &&
2 + has_primitive_id + key->input_vertices <= (devinfo->ver >= 12 ? 63 : 31)) {
/* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the
* "Instance" field limits the number of output vertices to [1, 16] on
* gen11 and below, or [1, 32] on gen12 and above. Secondly, the

56
src/intel/compiler/brw_vec4_visitor.cpp
View file

@ -150,7 +150,7 @@ vec4_visitor::emit(enum opcode opcode)
vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
const src_reg &src1, const src_reg &src2) \
{ \
assert(devinfo->gen >= 6); \
assert(devinfo->ver >= 6); \
return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
src0, src1, src2); \
}
@ -206,7 +206,7 @@ vec4_instruction *
vec4_visitor::IF(src_reg src0, src_reg src1,
enum brw_conditional_mod condition)
{
assert(devinfo->gen == 6);
assert(devinfo->ver == 6);
vec4_instruction *inst;
@ -259,7 +259,7 @@ vec4_visitor::SCRATCH_READ(const dst_reg &dst, const src_reg &index)
inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ,
dst, index);
inst->base_mrf = FIRST_SPILL_MRF(devinfo->gen) + 1;
inst->base_mrf = FIRST_SPILL_MRF(devinfo->ver) + 1;
inst->mlen = 2;
return inst;
@ -273,7 +273,7 @@ vec4_visitor::SCRATCH_WRITE(const dst_reg &dst, const src_reg &src,
inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE,
dst, src, index);
inst->base_mrf = FIRST_SPILL_MRF(devinfo->gen);
inst->base_mrf = FIRST_SPILL_MRF(devinfo->ver);
inst->mlen = 3;
return inst;
@ -308,7 +308,7 @@ vec4_visitor::fix_3src_operand(const src_reg &src)
src_reg
vec4_visitor::fix_math_operand(const src_reg &src)
{
if (devinfo->gen < 6 || src.file == BAD_FILE)
if (devinfo->ver < 6 || src.file == BAD_FILE)
return src;
/* The gen6 math instruction ignores the source modifiers --
@ -322,7 +322,7 @@ vec4_visitor::fix_math_operand(const src_reg &src)
* can't use.
*/
if (devinfo->gen == 7 && src.file != IMM)
if (devinfo->ver == 7 && src.file != IMM)
return src;
dst_reg expanded = dst_reg(this, glsl_type::vec4_type);
@ -339,12 +339,12 @@ vec4_visitor::emit_math(enum opcode opcode,
vec4_instruction *math =
emit(opcode, dst, fix_math_operand(src0), fix_math_operand(src1));
if (devinfo->gen == 6 && dst.writemask != WRITEMASK_XYZW) {
if (devinfo->ver == 6 && dst.writemask != WRITEMASK_XYZW) {
/* MATH on Gen6 must be align1, so we can't do writemasks. */
math->dst = dst_reg(this, glsl_type::vec4_type);
math->dst.type = dst.type;
math = emit(MOV(dst, src_reg(math->dst)));
} else if (devinfo->gen < 6) {
} else if (devinfo->ver < 6) {
math->base_mrf = 1;
math->mlen = src1.file == BAD_FILE ? 1 : 2;
}
@ -355,7 +355,7 @@ vec4_visitor::emit_math(enum opcode opcode,
void
vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0)
{
if (devinfo->gen < 7) {
if (devinfo->ver < 7) {
unreachable("ir_unop_pack_half_2x16 should be lowered");
}
@ -432,7 +432,7 @@ vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0)
void
vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0)
{
if (devinfo->gen < 7) {
if (devinfo->ver < 7) {
unreachable("ir_unop_unpack_half_2x16 should be lowered");
}
@ -740,7 +740,7 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
vec4_instruction *pull;
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
dst_reg grf_offset = dst_reg(this, glsl_type::uint_type);
grf_offset.type = offset_reg.type;
@ -762,7 +762,7 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
dst,
surf_index,
offset_reg);
pull->base_mrf = FIRST_PULL_LOAD_MRF(devinfo->gen) + 1;
pull->base_mrf = FIRST_PULL_LOAD_MRF(devinfo->ver) + 1;
pull->mlen = 1;
}
@ -879,7 +879,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
* - Sampleinfo message - takes no parameters, but mlen = 0 is illegal
*/
inst->header_size =
(devinfo->gen < 5 ||
(devinfo->ver < 5 ||
inst->offset != 0 || op == ir_tg4 ||
op == ir_texture_samples ||
is_high_sampler(sampler_reg)) ? 1 : 0;
@ -895,7 +895,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
int param_base = inst->base_mrf + inst->header_size;
if (op == ir_txs || op == ir_query_levels) {
int writemask = devinfo->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
int writemask = devinfo->ver == 4 ? WRITEMASK_W : WRITEMASK_X;
emit(MOV(dst_reg(MRF, param_base, lod.type, writemask), lod));
inst->mlen++;
} else if (op == ir_texture_samples) {
@ -925,7 +925,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
/* Load the LOD info */
if (op == ir_tex || op == ir_txl) {
int mrf, writemask;
if (devinfo->gen >= 5) {
if (devinfo->ver >= 5) {
mrf = param_base + 1;
if (shadow_comparator.file != BAD_FILE) {
writemask = WRITEMASK_Y;
@ -934,7 +934,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
writemask = WRITEMASK_X;
inst->mlen++;
}
} else /* devinfo->gen == 4 */ {
} else /* devinfo->ver == 4 */ {
mrf = param_base;
writemask = WRITEMASK_W;
}
@ -944,7 +944,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
} else if (op == ir_txf_ms) {
emit(MOV(dst_reg(MRF, param_base + 1, sample_index.type, WRITEMASK_X),
sample_index));
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
/* MCS data is in the first channel of `mcs`, but we need to get it into
* the .y channel of the second vec4 of params, so replicate .x across
* the whole vec4 and then mask off everything except .y
@ -957,7 +957,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
} else if (op == ir_txd) {
const brw_reg_type type = lod.type;
if (devinfo->gen >= 5) {
if (devinfo->ver >= 5) {
lod.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
lod2.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XZ), lod));
@ -977,7 +977,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
shadow_comparator));
}
}
} else /* devinfo->gen == 4 */ {
} else /* devinfo->ver == 4 */ {
emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XYZ), lod));
emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_XYZ), lod2));
inst->mlen += 2;
@ -999,13 +999,13 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
/* fixup num layers (z) for cube arrays: hardware returns faces * layers;
* spec requires layers.
*/
if (op == ir_txs && devinfo->gen < 7) {
if (op == ir_txs && devinfo->ver < 7) {
/* Gen4-6 return 0 instead of 1 for single layer surfaces. */
emit_minmax(BRW_CONDITIONAL_GE, writemask(inst->dst, WRITEMASK_Z),
src_reg(inst->dst), brw_imm_d(1));
}
if (devinfo->gen == 6 && op == ir_tg4) {
if (devinfo->ver == 6 && op == ir_tg4) {
emit_gen6_gather_wa(key_tex->gen6_gather_wa[surface], inst->dst);
}
@ -1087,7 +1087,7 @@ vec4_visitor::emit_ndc_computation()
void
vec4_visitor::emit_psiz_and_flags(dst_reg reg)
{
if (devinfo->gen < 6 &&
if (devinfo->ver < 6 &&
((prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) ||
output_reg[VARYING_SLOT_CLIP_DIST0][0].file != BAD_FILE ||
devinfo->has_negative_rhw_bug)) {
@ -1145,7 +1145,7 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
}
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1)));
} else if (devinfo->gen < 6) {
} else if (devinfo->ver < 6) {
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u)));
} else {
emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), brw_imm_d(0)));
@ -1247,7 +1247,7 @@ vec4_visitor::emit_urb_slot(dst_reg reg, int varying)
static unsigned
align_interleaved_urb_mlen(const struct gen_device_info *devinfo, unsigned mlen)
{
if (devinfo->gen >= 6) {
if (devinfo->ver >= 6) {
/* URB data written (does not include the message header reg) must
* be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
* section 5.4.3.2.2: URB_INTERLEAVED.
@ -1282,7 +1282,7 @@ vec4_visitor::emit_vertex()
* may need to unspill a register or load from an array. Those
* reads would use MRFs 14-15.
*/
int max_usable_mrf = FIRST_SPILL_MRF(devinfo->gen);
int max_usable_mrf = FIRST_SPILL_MRF(devinfo->ver);
/* The following assertion verifies that max_usable_mrf causes an
* even-numbered amount of URB write data, which will meet gen6's
@ -1295,7 +1295,7 @@ vec4_visitor::emit_vertex()
*/
emit_urb_write_header(mrf++);
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
emit_ndc_computation();
}
@ -1347,7 +1347,7 @@ vec4_visitor::get_scratch_offset(bblock_t *block, vec4_instruction *inst,
/* Pre-gen6, the message header uses byte offsets instead of vec4
* (16-byte) offset units.
*/
if (devinfo->gen < 6)
if (devinfo->ver < 6)
message_header_scale *= 16;
if (reladdr) {
@ -1785,7 +1785,7 @@ vec4_visitor::vec4_visitor(const struct brw_compiler *compiler,
memset(this->output_num_components, 0, sizeof(this->output_num_components));
this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->max_grf = devinfo->ver >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->uniforms = 0;

4
src/intel/compiler/brw_vue_map.c
View file

@ -67,7 +67,7 @@ brw_compute_vue_map(const struct gen_device_info *devinfo,
* the SSO layout when using geometry/tessellation shaders or 32 FS input
* varyings, which only exist on Gen >= 6. It's also a bit more efficient.
*/
if (devinfo->gen < 6)
if (devinfo->ver < 6)
separate = false;
if (separate) {
@ -112,7 +112,7 @@ brw_compute_vue_map(const struct gen_device_info *devinfo,
* See the Sandybridge PRM, Volume 2 Part 1, section 1.5.1 (page 30),
* "Vertex URB Entry (VUE) Formats" which describes the VUE header layout.
*/
if (devinfo->gen < 6) {
if (devinfo->ver < 6) {
/* There are 8 dwords in VUE header pre-Ironlake:
* dword 0-3 is indices, point width, clip flags.
* dword 4-7 is ndc position

2
src/intel/compiler/gen6_gs_visitor.cpp
View file

@ -347,7 +347,7 @@ gen6_gs_visitor::emit_thread_end()
* may need to unspill a register or load from an array. Those
* reads would use MRFs 21..23
*/
int max_usable_mrf = FIRST_SPILL_MRF(devinfo->gen);
int max_usable_mrf = FIRST_SPILL_MRF(devinfo->ver);
/* Issue the FF_SYNC message and obtain the initial VUE handle. */
this->current_annotation = "gen6 thread end: ff_sync";

16
src/intel/compiler/test_eu_compact.cpp
View file

@ -74,7 +74,7 @@ clear_pad_bits(const struct gen_device_info *devinfo, brw_inst *inst)
brw_inst_set_bits(inst, 127, 111, 0);
}
if (devinfo->gen == 8 && !devinfo->is_cherryview &&
if (devinfo->ver == 8 && !devinfo->is_cherryview &&
is_3src(devinfo, brw_inst_opcode(devinfo, inst))) {
brw_inst_set_bits(inst, 105, 105, 0);
brw_inst_set_bits(inst, 84, 84, 0);
@ -94,7 +94,7 @@ skip_bit(const struct gen_device_info *devinfo, brw_inst *src, int bit)
return true;
if (is_3src(devinfo, brw_inst_opcode(devinfo, src))) {
if (devinfo->gen >= 9 || devinfo->is_cherryview) {
if (devinfo->ver >= 9 || devinfo->is_cherryview) {
if (bit == 127)
return true;
} else {
@ -114,14 +114,14 @@ skip_bit(const struct gen_device_info *devinfo, brw_inst *src, int bit)
if (bit == 47)
return true;
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
if (bit == 11)
return true;
if (bit == 95)
return true;
} else {
if (devinfo->gen < 7 && bit == 90)
if (devinfo->ver < 7 && bit == 90)
return true;
if (bit >= 91 && bit <= 95)
@ -295,7 +295,7 @@ run_tests(const struct gen_device_info *devinfo)
for (int align_16 = 0; align_16 <= 1; align_16++) {
/* Align16 support is not present on Gen11+ */
if (devinfo->gen >= 11 && align_16)
if (devinfo->ver >= 11 && align_16)
continue;
struct brw_codegen *p = rzalloc(NULL, struct brw_codegen);
@ -333,11 +333,11 @@ main(UNUSED int argc, UNUSED char **argv)
struct gen_device_info *devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
bool fail = false;
for (devinfo->gen = 5; devinfo->gen <= 12; devinfo->gen++) {
if (devinfo->gen == 10)
for (devinfo->ver = 5; devinfo->ver <= 12; devinfo->ver++) {
if (devinfo->ver == 10)
continue;
devinfo->verx10 = devinfo->gen * 10;
devinfo->verx10 = devinfo->ver * 10;
fail |= run_tests(devinfo);
}

132
src/intel/compiler/test_eu_validate.cpp
View file

@ -152,7 +152,7 @@ TEST_P(validation_test, src1_null_reg)
TEST_P(validation_test, math_src0_null_reg)
{
if (devinfo.gen >= 6) {
if (devinfo.ver >= 6) {
gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, null, null);
} else {
gen4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, null, BRW_MATH_PRECISION_FULL);
@ -163,7 +163,7 @@ TEST_P(validation_test, math_src0_null_reg)
TEST_P(validation_test, math_src1_null_reg)
{
if (devinfo.gen >= 6) {
if (devinfo.ver >= 6) {
gen6_math(p, g0, BRW_MATH_FUNCTION_POW, g0, null);
EXPECT_FALSE(validate(p));
} else {
@ -182,7 +182,7 @@ TEST_P(validation_test, opcode46)
*/
brw_next_insn(p, brw_opcode_decode(&devinfo, 46));
if (devinfo.gen == 7) {
if (devinfo.ver == 7) {
EXPECT_FALSE(validate(p));
} else {
EXPECT_TRUE(validate(p));
@ -232,13 +232,13 @@ TEST_P(validation_test, invalid_exec_size_encoding)
TEST_P(validation_test, invalid_file_encoding)
{
/* Register file on Gen12 is only one bit */
if (devinfo.gen >= 12)
if (devinfo.ver >= 12)
return;
brw_MOV(p, g0, g0);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_MESSAGE_REGISTER_FILE, BRW_REGISTER_TYPE_F);
if (devinfo.gen > 6) {
if (devinfo.ver > 6) {
EXPECT_FALSE(validate(p));
} else {
EXPECT_TRUE(validate(p));
@ -246,14 +246,14 @@ TEST_P(validation_test, invalid_file_encoding)
clear_instructions(p);
if (devinfo.gen < 6) {
if (devinfo.ver < 6) {
gen4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, g0, BRW_MATH_PRECISION_FULL);
} else {
gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null);
}
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_MESSAGE_REGISTER_FILE, BRW_REGISTER_TYPE_F);
if (devinfo.gen > 6) {
if (devinfo.ver > 6) {
EXPECT_FALSE(validate(p));
} else {
EXPECT_TRUE(validate(p));
@ -269,7 +269,7 @@ TEST_P(validation_test, invalid_type_encoding)
for (unsigned i = 0; i < ARRAY_SIZE(files); i++) {
const enum brw_reg_file file = files[i];
const int num_bits = devinfo.gen >= 8 ? 4 : 3;
const int num_bits = devinfo.ver >= 8 ? 4 : 3;
const int num_encodings = 1 << num_bits;
/* The data types are encoded into <num_bits> bits to be used in hardware
@ -282,10 +282,10 @@ TEST_P(validation_test, invalid_type_encoding)
enum brw_reg_type type;
bool expected_result;
} test_case[] = {
{ BRW_REGISTER_TYPE_NF, devinfo.gen == 11 && file != IMM },
{ BRW_REGISTER_TYPE_DF, devinfo.has_64bit_float && (devinfo.gen >= 8 || file != IMM) },
{ BRW_REGISTER_TYPE_NF, devinfo.ver == 11 && file != IMM },
{ BRW_REGISTER_TYPE_DF, devinfo.has_64bit_float && (devinfo.ver >= 8 || file != IMM) },
{ BRW_REGISTER_TYPE_F, true },
{ BRW_REGISTER_TYPE_HF, devinfo.gen >= 8 },
{ BRW_REGISTER_TYPE_HF, devinfo.ver >= 8 },
{ BRW_REGISTER_TYPE_VF, file == IMM },
{ BRW_REGISTER_TYPE_Q, devinfo.has_64bit_int },
{ BRW_REGISTER_TYPE_UQ, devinfo.has_64bit_int },
@ -296,7 +296,7 @@ TEST_P(validation_test, invalid_type_encoding)
{ BRW_REGISTER_TYPE_B, file == FIXED_GRF },
{ BRW_REGISTER_TYPE_UB, file == FIXED_GRF },
{ BRW_REGISTER_TYPE_V, file == IMM },
{ BRW_REGISTER_TYPE_UV, devinfo.gen >= 6 && file == IMM },
{ BRW_REGISTER_TYPE_UV, devinfo.ver >= 6 && file == IMM },
};
/* Initially assume all hardware encodings are invalid */
@ -374,10 +374,10 @@ TEST_P(validation_test, invalid_type_encoding)
TEST_P(validation_test, invalid_type_encoding_3src_a16)
{
/* 3-src instructions in align16 mode only supported on Gen6-10 */
if (devinfo.gen < 6 || devinfo.gen > 10)
if (devinfo.ver < 6 || devinfo.ver > 10)
return;
const int num_bits = devinfo.gen >= 8 ? 3 : 2;
const int num_bits = devinfo.ver >= 8 ? 3 : 2;
const int num_encodings = 1 << num_bits;
/* The data types are encoded into <num_bits> bits to be used in hardware
@ -390,11 +390,11 @@ TEST_P(validation_test, invalid_type_encoding_3src_a16)
enum brw_reg_type type;
bool expected_result;
} test_case[] = {
{ BRW_REGISTER_TYPE_DF, devinfo.gen >= 7 },
{ BRW_REGISTER_TYPE_DF, devinfo.ver >= 7 },
{ BRW_REGISTER_TYPE_F, true },
{ BRW_REGISTER_TYPE_HF, devinfo.gen >= 8 },
{ BRW_REGISTER_TYPE_D, devinfo.gen >= 7 },
{ BRW_REGISTER_TYPE_UD, devinfo.gen >= 7 },
{ BRW_REGISTER_TYPE_HF, devinfo.ver >= 8 },
{ BRW_REGISTER_TYPE_D, devinfo.ver >= 7 },
{ BRW_REGISTER_TYPE_UD, devinfo.ver >= 7 },
};
/* Initially assume all hardware encodings are invalid */
@ -445,7 +445,7 @@ TEST_P(validation_test, invalid_type_encoding_3src_a16)
clear_instructions(p);
if (devinfo.gen == 6)
if (devinfo.ver == 6)
break;
}
}
@ -454,7 +454,7 @@ TEST_P(validation_test, invalid_type_encoding_3src_a16)
TEST_P(validation_test, invalid_type_encoding_3src_a1)
{
/* 3-src instructions in align1 mode only supported on Gen10+ */
if (devinfo.gen < 10)
if (devinfo.ver < 10)
return;
const int num_bits = 3 + 1 /* for exec_type */;
@ -472,7 +472,7 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1)
bool expected_result;
} test_case[] = {
#define E(x) ((unsigned)BRW_ALIGN1_3SRC_EXEC_TYPE_##x)
{ BRW_REGISTER_TYPE_NF, E(FLOAT), devinfo.gen == 11 },
{ BRW_REGISTER_TYPE_NF, E(FLOAT), devinfo.ver == 11 },
{ BRW_REGISTER_TYPE_DF, E(FLOAT), devinfo.has_64bit_float },
{ BRW_REGISTER_TYPE_F, E(FLOAT), true },
{ BRW_REGISTER_TYPE_HF, E(FLOAT), true },
@ -552,23 +552,23 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1)
TEST_P(validation_test, 3src_inst_access_mode)
{
/* 3-src instructions only supported on Gen6+ */
if (devinfo.gen < 6)
if (devinfo.ver < 6)
return;
/* No access mode bit on Gen12+ */
if (devinfo.gen >= 12)
if (devinfo.ver >= 12)
return;
const struct {
unsigned mode;
bool expected_result;
} test_case[] = {
{ BRW_ALIGN_1, devinfo.gen >= 10 },
{ BRW_ALIGN_16, devinfo.gen <= 10 },
{ BRW_ALIGN_1, devinfo.ver >= 10 },
{ BRW_ALIGN_16, devinfo.ver <= 10 },
};
for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) {
if (devinfo.gen < 10)
if (devinfo.ver < 10)
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MAD(p, g0, g0, g0, g0);
@ -751,7 +751,7 @@ TEST_P(validation_test, dst_horizontal_stride_0)
clear_instructions(p);
/* Align16 does not exist on Gen11+ */
if (devinfo.gen >= 11)
if (devinfo.ver >= 11)
return;
brw_set_default_access_mode(p, BRW_ALIGN_16);
@ -802,7 +802,7 @@ TEST_P(validation_test, must_not_cross_grf_boundary_in_a_width)
TEST_P(validation_test, dst_hstride_on_align16_must_be_1)
{
/* Align16 does not exist on Gen11+ */
if (devinfo.gen >= 11)
if (devinfo.ver >= 11)
return;
brw_set_default_access_mode(p, BRW_ALIGN_16);
@ -824,7 +824,7 @@ TEST_P(validation_test, dst_hstride_on_align16_must_be_1)
TEST_P(validation_test, vstride_on_align16_must_be_0_or_4)
{
/* Align16 does not exist on Gen11+ */
if (devinfo.gen >= 11)
if (devinfo.ver >= 11)
return;
const struct {
@ -833,7 +833,7 @@ TEST_P(validation_test, vstride_on_align16_must_be_0_or_4)
} vstride[] = {
{ BRW_VERTICAL_STRIDE_0, true },
{ BRW_VERTICAL_STRIDE_1, false },
{ BRW_VERTICAL_STRIDE_2, devinfo.is_haswell || devinfo.gen >= 8 },
{ BRW_VERTICAL_STRIDE_2, devinfo.is_haswell || devinfo.ver >= 8 },
{ BRW_VERTICAL_STRIDE_4, true },
{ BRW_VERTICAL_STRIDE_8, false },
{ BRW_VERTICAL_STRIDE_16, false },
@ -988,7 +988,7 @@ TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one)
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
if (devinfo.gen >= 9) {
if (devinfo.ver >= 9) {
EXPECT_TRUE(validate(p));
} else {
EXPECT_FALSE(validate(p));
@ -1000,7 +1000,7 @@ TEST_P(validation_test, dst_elements_must_be_evenly_split_between_registers)
brw_ADD(p, g0, g0, g0);
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 4);
if (devinfo.gen >= 9) {
if (devinfo.ver >= 9) {
EXPECT_TRUE(validate(p));
} else {
EXPECT_FALSE(validate(p));
@ -1015,7 +1015,7 @@ TEST_P(validation_test, dst_elements_must_be_evenly_split_between_registers)
clear_instructions(p);
if (devinfo.gen >= 6) {
if (devinfo.ver >= 6) {
gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null);
EXPECT_TRUE(validate(p));
@ -1042,7 +1042,7 @@ TEST_P(validation_test, two_src_two_dst_source_offsets_must_be_same)
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
if (devinfo.gen <= 7) {
if (devinfo.ver <= 7) {
EXPECT_FALSE(validate(p));
} else {
EXPECT_TRUE(validate(p));
@ -1075,7 +1075,7 @@ TEST_P(validation_test, two_src_two_dst_each_dst_must_be_derived_from_one_src)
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
if (devinfo.gen <= 7) {
if (devinfo.ver <= 7) {
EXPECT_FALSE(validate(p));
} else {
EXPECT_TRUE(validate(p));
@ -1090,7 +1090,7 @@ TEST_P(validation_test, two_src_two_dst_each_dst_must_be_derived_from_one_src)
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2);
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
if (devinfo.gen <= 7) {
if (devinfo.ver <= 7) {
EXPECT_FALSE(validate(p));
} else {
EXPECT_TRUE(validate(p));
@ -1128,7 +1128,7 @@ TEST_P(validation_test, one_src_two_dst)
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
if (devinfo.gen >= 8) {
if (devinfo.ver >= 8) {
EXPECT_TRUE(validate(p));
} else {
EXPECT_FALSE(validate(p));
@ -1146,7 +1146,7 @@ TEST_P(validation_test, one_src_two_dst)
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
if (devinfo.gen >= 8) {
if (devinfo.ver >= 8) {
EXPECT_TRUE(validate(p));
} else {
EXPECT_FALSE(validate(p));
@ -1234,7 +1234,7 @@ TEST_P(validation_test, byte_destination_relaxed_alignment)
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 1);
if (devinfo.gen > 4 || devinfo.is_g4x) {
if (devinfo.ver > 4 || devinfo.is_g4x) {
EXPECT_TRUE(validate(p));
} else {
EXPECT_FALSE(validate(p));
@ -1281,7 +1281,7 @@ TEST_P(validation_test, byte_64bit_conversion)
#undef INST
};
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -1383,7 +1383,7 @@ TEST_P(validation_test, half_float_conversion)
#undef INST_S
};
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -1416,7 +1416,7 @@ TEST_P(validation_test, half_float_conversion)
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
}
if (devinfo.is_cherryview || devinfo.gen >= 9)
if (devinfo.is_cherryview || devinfo.ver >= 9)
EXPECT_EQ(inst[i].expected_result_chv_gen9, validate(p));
else
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
@ -1470,7 +1470,7 @@ TEST_P(validation_test, mixed_float_source_indirect_addressing)
#undef INST
};
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -1524,7 +1524,7 @@ TEST_P(validation_test, mixed_float_align1_simd16)
#undef INST
};
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -1591,7 +1591,7 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst_acc_read_offset_0)
#undef INST
};
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -1603,7 +1603,7 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst_acc_read_offset_0)
brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, inst[i].subnr);
if (devinfo.is_cherryview || devinfo.gen >= 9)
if (devinfo.is_cherryview || devinfo.ver >= 9)
EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
else
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
@ -1667,7 +1667,7 @@ TEST_P(validation_test, mixed_float_fp16_dest_with_acc)
#undef INST
};
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -1686,7 +1686,7 @@ TEST_P(validation_test, mixed_float_fp16_dest_with_acc)
brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
if (devinfo.is_cherryview || devinfo.gen >= 9)
if (devinfo.is_cherryview || devinfo.ver >= 9)
EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
else
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
@ -1734,7 +1734,7 @@ TEST_P(validation_test, mixed_float_align1_math_strided_fp16_inputs)
};
/* No half-float math in gen8 */
if (devinfo.gen < 9)
if (devinfo.ver < 9)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -1809,7 +1809,7 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst)
#undef INST
};
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -1830,7 +1830,7 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst)
brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
if (devinfo.is_cherryview || devinfo.gen >= 9)
if (devinfo.is_cherryview || devinfo.ver >= 9)
EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
else
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
@ -1878,7 +1878,7 @@ TEST_P(validation_test, mixed_float_align16_packed_data)
#undef INST
};
if (devinfo.gen < 8 || devinfo.gen >= 11)
if (devinfo.ver < 8 || devinfo.ver >= 11)
return;
brw_set_default_access_mode(p, BRW_ALIGN_16);
@ -1929,7 +1929,7 @@ TEST_P(validation_test, mixed_float_align16_no_simd16)
#undef INST
};
if (devinfo.gen < 8 || devinfo.gen >= 11)
if (devinfo.ver < 8 || devinfo.ver >= 11)
return;
brw_set_default_access_mode(p, BRW_ALIGN_16);
@ -1980,7 +1980,7 @@ TEST_P(validation_test, mixed_float_align16_no_acc_read)
#undef INST
};
if (devinfo.gen < 8 || devinfo.gen >= 11)
if (devinfo.ver < 8 || devinfo.ver >= 11)
return;
brw_set_default_access_mode(p, BRW_ALIGN_16);
@ -2035,7 +2035,7 @@ TEST_P(validation_test, mixed_float_align16_math_packed_format)
};
/* Align16 Math for mixed float mode is not supported in gen8 */
if (devinfo.gen < 9 || devinfo.gen >= 11)
if (devinfo.ver < 9 || devinfo.ver >= 11)
return;
brw_set_default_access_mode(p, BRW_ALIGN_16);
@ -2079,7 +2079,7 @@ TEST_P(validation_test, vector_immediate_destination_alignment)
for (unsigned i = 0; i < ARRAY_SIZE(move); i++) {
/* UV type is Gen6+ */
if (devinfo.gen < 6 &&
if (devinfo.ver < 6 &&
move[i].src_type == BRW_REGISTER_TYPE_UV)
continue;
@ -2121,7 +2121,7 @@ TEST_P(validation_test, vector_immediate_destination_stride)
for (unsigned i = 0; i < ARRAY_SIZE(move); i++) {
/* UV type is Gen6+ */
if (devinfo.gen < 6 &&
if (devinfo.ver < 6 &&
move[i].src_type == BRW_REGISTER_TYPE_UV)
continue;
@ -2272,11 +2272,11 @@ TEST_P(validation_test, qword_low_power_align1_regioning_restrictions)
};
/* These restrictions only apply to Gen8+ */
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
/* NoDDChk/NoDDClr does not exist on Gen12+ */
if (devinfo.gen >= 12)
if (devinfo.ver >= 12)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -2408,7 +2408,7 @@ TEST_P(validation_test, qword_low_power_no_indirect_addressing)
};
/* These restrictions only apply to Gen8+ */
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -2556,7 +2556,7 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf)
};
/* These restrictions only apply to Gen8+ */
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -2661,11 +2661,11 @@ TEST_P(validation_test, align16_64_bit_integer)
};
/* 64-bit integer types exist on Gen8+ */
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
/* Align16 does not exist on Gen11+ */
if (devinfo.gen >= 11)
if (devinfo.ver >= 11)
return;
brw_set_default_access_mode(p, BRW_ALIGN_16);
@ -2769,11 +2769,11 @@ TEST_P(validation_test, qword_low_power_no_depctrl)
};
/* These restrictions only apply to Gen8+ */
if (devinfo.gen < 8)
if (devinfo.ver < 8)
return;
/* NoDDChk/NoDDClr does not exist on Gen12+ */
if (devinfo.gen >= 12)
if (devinfo.ver >= 12)
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
@ -2887,7 +2887,7 @@ TEST_P(validation_test, gen11_no_byte_src_1_2)
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
/* Skip instruction not meant for this gen. */
if (devinfo.gen != inst[i].gen)
if (devinfo.ver != inst[i].gen)
continue;
brw_push_insn_state(p);

4
src/intel/compiler/test_fs_cmod_propagation.cpp
View file

@ -76,8 +76,8 @@ void cmod_propagation_test::SetUp()
v = new cmod_propagation_fs_visitor(compiler, ctx, prog_data, shader);
devinfo->gen = 7;
devinfo->verx10 = devinfo->gen * 10;
devinfo->ver = 7;
devinfo->verx10 = devinfo->ver * 10;
}
void cmod_propagation_test::TearDown()

4
src/intel/compiler/test_fs_copy_propagation.cpp
View file

@ -66,8 +66,8 @@ void copy_propagation_test::SetUp()
v = new copy_propagation_fs_visitor(compiler, ctx, prog_data, shader);
devinfo->gen = 4;
devinfo->verx10 = devinfo->gen * 10;
devinfo->ver = 4;
devinfo->verx10 = devinfo->ver * 10;
}
void copy_propagation_test::TearDown()

4
src/intel/compiler/test_fs_saturate_propagation.cpp
View file

@ -66,8 +66,8 @@ void saturate_propagation_test::SetUp()
v = new saturate_propagation_fs_visitor(compiler, ctx, prog_data, shader);
devinfo->gen = 6;
devinfo->verx10 = devinfo->gen * 10;
devinfo->ver = 6;
devinfo->verx10 = devinfo->ver * 10;
}
void saturate_propagation_test::TearDown()

4
src/intel/compiler/test_fs_scoreboard.cpp
View file

@ -54,8 +54,8 @@ void scoreboard_test::SetUp()
v = new fs_visitor(compiler, NULL, ctx, NULL, &prog_data->base, shader, 8, -1, false);
devinfo->gen = 12;
devinfo->verx10 = devinfo->gen * 10;
devinfo->ver = 12;
devinfo->verx10 = devinfo->ver * 10;
}
void scoreboard_test::TearDown()

4
src/intel/compiler/test_vec4_cmod_propagation.cpp
View file

@ -109,8 +109,8 @@ void cmod_propagation_test::SetUp()
v = new cmod_propagation_vec4_visitor(compiler, ctx, shader, prog_data);
devinfo->gen = 4;
devinfo->verx10 = devinfo->gen * 10;
devinfo->ver = 4;
devinfo->verx10 = devinfo->ver * 10;
}
void cmod_propagation_test::TearDown()

4
src/intel/compiler/test_vec4_copy_propagation.cpp
View file

@ -101,8 +101,8 @@ void copy_propagation_test::SetUp()
v = new copy_propagation_vec4_visitor(compiler, ctx, shader, prog_data);
devinfo->gen = 4;
devinfo->verx10 = devinfo->gen * 10;
devinfo->ver = 4;
devinfo->verx10 = devinfo->ver * 10;
}
void copy_propagation_test::TearDown()

4
src/intel/compiler/test_vec4_dead_code_eliminate.cpp
View file

@ -99,8 +99,8 @@ void dead_code_eliminate_test::SetUp()
v = new dead_code_eliminate_vec4_visitor(compiler, ctx, shader, prog_data);
devinfo->gen = 4;
devinfo->verx10 = devinfo->gen * 10;
devinfo->ver = 4;
devinfo->verx10 = devinfo->ver * 10;
}
void dead_code_eliminate_test::TearDown()

4
src/intel/compiler/test_vec4_register_coalesce.cpp
View file

@ -105,8 +105,8 @@ void register_coalesce_test::SetUp()
v = new register_coalesce_vec4_visitor(compiler, ctx, shader, prog_data);
devinfo->gen = 4;
devinfo->verx10 = devinfo->gen * 10;
devinfo->ver = 4;
devinfo->verx10 = devinfo->ver * 10;
}
void register_coalesce_test::TearDown()

42
src/intel/dev/gen_device_info.c
View file

@ -84,13 +84,13 @@ gen_device_name_to_pci_device_id(const char *name)
}
static const struct gen_device_info gen_device_info_gen3 = {
.gen = 3,
.ver = 3,
.simulator_id = -1,
.cs_prefetch_size = 512,
};
static const struct gen_device_info gen_device_info_i965 = {
.gen = 4,
.ver = 4,
.has_negative_rhw_bug = true,
.num_slices = 1,
.num_subslices = { 1, },
@ -108,7 +108,7 @@ static const struct gen_device_info gen_device_info_i965 = {
};
static const struct gen_device_info gen_device_info_g4x = {
.gen = 4,
.ver = 4,
.verx10 = 45,
.has_pln = true,
.has_compr4 = true,
@ -130,7 +130,7 @@ static const struct gen_device_info gen_device_info_g4x = {
};
static const struct gen_device_info gen_device_info_ilk = {
.gen = 5,
.ver = 5,
.has_pln = true,
.has_compr4 = true,
.has_surface_tile_offset = true,
@ -150,7 +150,7 @@ static const struct gen_device_info gen_device_info_ilk = {
};
static const struct gen_device_info gen_device_info_snb_gt1 = {
.gen = 6,
.ver = 6,
.gt = 1,
.has_hiz_and_separate_stencil = true,
.has_llc = true,
@ -180,7 +180,7 @@ static const struct gen_device_info gen_device_info_snb_gt1 = {
};
static const struct gen_device_info gen_device_info_snb_gt2 = {
.gen = 6,
.ver = 6,
.gt = 2,
.has_hiz_and_separate_stencil = true,
.has_llc = true,
@ -210,7 +210,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 = {
};
#define GEN7_FEATURES \
.gen = 7, \
.ver = 7, \
.has_hiz_and_separate_stencil = true, \
.must_use_separate_stencil = true, \
.has_llc = true, \
@ -401,7 +401,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = {
* so keep things conservative for now and set has_sample_with_hiz = false.
*/
#define GEN8_FEATURES \
.gen = 8, \
.ver = 8, \
.has_hiz_and_separate_stencil = true, \
.has_resource_streamer = true, \
.must_use_separate_stencil = true, \
@ -522,7 +522,7 @@ static const struct gen_device_info gen_device_info_chv = {
};
#define GEN9_HW_INFO \
.gen = 9, \
.ver = 9, \
.max_vs_threads = 336, \
.max_gs_threads = 336, \
.max_tcs_threads = 336, \
@ -807,7 +807,7 @@ static const struct gen_device_info gen_device_info_cfl_gt3 = {
#define subslices(args...) { args, }
#define GEN11_HW_INFO \
.gen = 11, \
.ver = 11, \
.has_pln = false, \
.max_vs_threads = 364, \
.max_gs_threads = 224, \
@ -926,7 +926,7 @@ static const struct gen_device_info gen_device_info_ehl_2x4 = {
}
#define GEN12_HW_INFO \
.gen = 12, \
.ver = 12, \
.has_pln = false, \
.has_sample_with_hiz = false, \
.has_aux_map = true, \
@ -1103,7 +1103,7 @@ update_from_topology(struct gen_device_info *devinfo,
}
assert(n_subslices > 0);
if (devinfo->gen >= 11) {
if (devinfo->ver >= 11) {
/* On current ICL+ hardware we only have one slice. */
assert(devinfo->slice_masks == 1);
@ -1114,7 +1114,7 @@ update_from_topology(struct gen_device_info *devinfo,
* each pixel pipe only takes 2 bits in the mask even though it's still
* 4 subslices.
*/
const unsigned ppipe_bits = devinfo->gen >= 12 ? 2 : 4;
const unsigned ppipe_bits = devinfo->ver >= 12 ? 2 : 4;
for (unsigned p = 0; p < GEN_DEVICE_MAX_PIXEL_PIPES; p++) {
const unsigned ppipe_mask = BITFIELD_RANGE(p * ppipe_bits, ppipe_bits);
devinfo->ppipe_subslices[p] =
@ -1122,7 +1122,7 @@ update_from_topology(struct gen_device_info *devinfo,
}
}
if (devinfo->gen == 12 && devinfo->num_slices == 1) {
if (devinfo->ver == 12 && devinfo->num_slices == 1) {
if (n_subslices >= 6) {
assert(n_subslices == 6);
devinfo->l3_banks = 8;
@ -1260,7 +1260,7 @@ gen_get_device_info_from_pci_id(int pci_id,
* calculated for a particular shader stage.
*/
switch(devinfo->gen) {
switch(devinfo->ver) {
case 9:
devinfo->max_wm_threads = 64 /* threads-per-PSD */
* devinfo->num_slices
@ -1273,14 +1273,14 @@ gen_get_device_info_from_pci_id(int pci_id,
* 8; /* subslices per slice */
break;
default:
assert(devinfo->gen < 9);
assert(devinfo->ver < 9);
break;
}
assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
if (devinfo->verx10 == 0)
devinfo->verx10 = devinfo->gen * 10;
devinfo->verx10 = devinfo->ver * 10;
devinfo->chipset_id = pci_id;
return true;
@ -1324,7 +1324,7 @@ getparam_topology(struct gen_device_info *devinfo, int fd)
/* Only with Gen8+ are we starting to see devices with fusing that can only
* be detected at runtime.
*/
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
mesa_logw("Kernel 4.1 required to properly query GPU properties.");
return false;
@ -1444,7 +1444,7 @@ gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
devinfo->no_hw = false;
}
if (devinfo->gen == 10) {
if (devinfo->ver == 10) {
mesa_loge("Gen10 support is redacted.");
return false;
}
@ -1457,7 +1457,7 @@ gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
&timestamp_frequency))
devinfo->timestamp_frequency = timestamp_frequency;
else if (devinfo->gen >= 10) {
else if (devinfo->ver >= 10) {
mesa_loge("Kernel 4.15 required to read the CS timestamp frequency.");
return false;
}
@ -1466,7 +1466,7 @@ gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
devinfo->revision = 0;
if (!query_topology(devinfo, fd)) {
if (devinfo->gen >= 10) {
if (devinfo->ver >= 10) {
/* topology uAPI required for CNL+ (kernel 4.17+) */
return false;
}

4
src/intel/dev/gen_device_info.h
View file

@ -46,8 +46,8 @@ struct drm_i915_query_topology_info;
*/
struct gen_device_info
{
int gen; /**< Generation number: 4, 5, 6, 7, ... */
/* Driver internal number used to differentiate platforms. */
/* Driver internal numbers used to differentiate platforms. */
int ver;
int verx10;
int revision;
int gt;

2
src/intel/dev/gen_device_info_test.c
View file

@ -23,7 +23,7 @@ main(int argc, char *argv[])
assert(gen_get_device_info_from_pci_id(chipsets[i].pci_id, &devinfo));
assert(devinfo.gen != 0);
assert(devinfo.ver != 0);
assert(devinfo.num_eu_per_subslice != 0);
assert(devinfo.num_thread_per_eu != 0);
assert(devinfo.timestamp_frequency != 0);

2
src/intel/dev/intel_device_info.c
View file

@ -73,7 +73,7 @@ main(int argc, char *argv[])
fprintf(stdout, "%s:\n", path);
fprintf(stdout, " name: %s\n", gen_get_device_name(devinfo.chipset_id));
fprintf(stdout, " gen: %u\n", devinfo.gen);
fprintf(stdout, " gen: %u\n", devinfo.ver);
fprintf(stdout, " PCI id: 0x%x\n", devinfo.chipset_id);
fprintf(stdout, " revision: %u\n", devinfo.revision);

14
src/intel/isl/isl.c
View file

@ -98,7 +98,7 @@ __isl_finishme(const char *file, int line, const char *fmt, ...)
static void
isl_device_setup_mocs(struct isl_device *dev)
{
if (dev->info->gen >= 12) {
if (dev->info->ver >= 12) {
if (dev->info->is_dg1) {
/* L3CC=WB */
dev->mocs.internal = 5 << 1;
@ -116,12 +116,12 @@ isl_device_setup_mocs(struct isl_device *dev)
/* L1 - HDC:L1 + L3 + LLC */
dev->mocs.l1_hdc_l3_llc = 48 << 1;
}
} else if (dev->info->gen >= 9) {
} else if (dev->info->ver >= 9) {
/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
dev->mocs.external = 1 << 1;
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
dev->mocs.internal = 2 << 1;
} else if (dev->info->gen >= 8) {
} else if (dev->info->ver >= 8) {
/* MEMORY_OBJECT_CONTROL_STATE:
* .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
* .TargetCache = L3DefertoPATforLLCeLLCselection,
@ -134,7 +134,7 @@ isl_device_setup_mocs(struct isl_device *dev)
* .AgeforQUADLRU = 0
*/
dev->mocs.internal = 0x78;
} else if (dev->info->gen >= 7) {
} else if (dev->info->ver >= 7) {
if (dev->info->is_haswell) {
/* MEMORY_OBJECT_CONTROL_STATE:
* .LLCeLLCCacheabilityControlLLCCC = 0,
@ -167,7 +167,7 @@ isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
if (external)
return dev->mocs.external;
if (dev->info->gen >= 12 && !dev->info->is_dg1) {
if (dev->info->ver >= 12 && !dev->info->is_dg1) {
if (usage & ISL_SURF_USAGE_STAGING_BIT)
return dev->mocs.internal;
@ -194,7 +194,7 @@ isl_device_init(struct isl_device *dev,
bool has_bit6_swizzling)
{
/* Gen8+ don't have bit6 swizzling, ensure callsite is not confused. */
assert(!(has_bit6_swizzling && info->gen >= 8));
assert(!(has_bit6_swizzling && info->ver >= 8));
dev->info = info;
dev->use_separate_stencil = ISL_GFX_VER(dev) >= 6;
@ -2809,7 +2809,7 @@ isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
* order will be written."
*/
return true;
} else if (devinfo->gen <= 7) {
} else if (devinfo->ver <= 7) {
/* Ivy Bridge and early doesn't have any swizzling */
return isl_swizzle_is_identity(swizzle);
} else {

8
src/intel/isl/isl.h
View file

@ -60,13 +60,13 @@ struct brw_image_param;
* You can define this as a compile-time constant in the CFLAGS. For example,
* `gcc -DISL_GFX_VER(dev)=9 ...`.
*/
#define ISL_GFX_VER(__dev) ((__dev)->info->gen)
#define ISL_GFX_VERX10(__dev) ((__dev)->info->genx10)
#define ISL_GFX_VER(__dev) ((__dev)->info->ver)
#define ISL_GFX_VERX10(__dev) ((__dev)->info->verx10)
#define ISL_GFX_VER_SANITIZE(__dev)
#else
#define ISL_GFX_VER_SANITIZE(__dev) \
(assert(ISL_GFX_VER(__dev) == (__dev)->info->gen) && \
ISL_GFX_VERX10(__dev) == (__dev)->info->genx10))
(assert(ISL_GFX_VER(__dev) == (__dev)->info->ver) && \
ISL_GFX_VERX10(__dev) == (__dev)->info->verx10))
#endif
#ifndef ISL_DEV_IS_G4X

2
src/intel/isl/isl_drm.c
View file

@ -144,7 +144,7 @@ isl_drm_modifier_get_score(const struct gen_device_info *devinfo,
return 3;
case I915_FORMAT_MOD_Y_TILED_CCS:
/* Gen12's CCS layout differs from Gen9-11. */
if (devinfo->gen >= 12)
if (devinfo->ver >= 12)
return 0;
if (INTEL_DEBUG & DEBUG_NO_RBC)

8
src/intel/isl/isl_format.c
View file

@ -675,7 +675,7 @@ isl_format_for_pipe_format(enum pipe_format pf)
static unsigned
format_gen(const struct gen_device_info *devinfo)
{
return devinfo->gen * 10 + (devinfo->is_g4x || devinfo->is_haswell) * 5;
return devinfo->ver * 10 + (devinfo->is_g4x || devinfo->is_haswell) * 5;
}
static bool
@ -835,7 +835,7 @@ isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
/* Clear-only compression was first added on Ivy Bridge and was last
* implemented on Ice lake (see BSpec: 43862).
*/
if (devinfo->gen < 7 || devinfo->gen > 11)
if (devinfo->ver < 7 || devinfo->ver > 11)
return false;
if (!isl_format_supports_rendering(devinfo, format))
@ -897,8 +897,8 @@ isl_format_supports_multisampling(const struct gen_device_info *devinfo,
/* On SKL+, HiZ is always single-sampled even when the primary surface
* is multisampled. See also isl_surf_get_hiz_surf().
*/
return devinfo->gen <= 8;
} else if (devinfo->gen < 7 && isl_format_get_layout(format)->bpb > 64) {
return devinfo->ver <= 8;
} else if (devinfo->ver < 7 && isl_format_get_layout(format)->bpb > 64) {
return false;
} else if (isl_format_is_compressed(format)) {
return false;

44
src/intel/isl/isl_storage_image.c
View file

@ -107,8 +107,8 @@ isl_lower_storage_image_format(const struct gen_device_info *devinfo,
case ISL_FORMAT_R32G32_UINT:
case ISL_FORMAT_R32G32_SINT:
case ISL_FORMAT_R32G32_FLOAT:
return (devinfo->gen >= 9 ? format :
devinfo->gen >= 8 || devinfo->is_haswell ?
return (devinfo->ver >= 9 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
ISL_FORMAT_R16G16B16A16_UINT :
ISL_FORMAT_R32G32_UINT);
@ -124,31 +124,31 @@ isl_lower_storage_image_format(const struct gen_device_info *devinfo,
*/
case ISL_FORMAT_R8G8B8A8_UINT:
case ISL_FORMAT_R8G8B8A8_SINT:
return (devinfo->gen >= 9 ? format :
devinfo->gen >= 8 || devinfo->is_haswell ?
return (devinfo->ver >= 9 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT);
case ISL_FORMAT_R16G16_UINT:
case ISL_FORMAT_R16G16_SINT:
case ISL_FORMAT_R16G16_FLOAT:
return (devinfo->gen >= 9 ? format :
devinfo->gen >= 8 || devinfo->is_haswell ?
return (devinfo->ver >= 9 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT);
case ISL_FORMAT_R8G8_UINT:
case ISL_FORMAT_R8G8_SINT:
return (devinfo->gen >= 9 ? format :
devinfo->gen >= 8 || devinfo->is_haswell ?
return (devinfo->ver >= 9 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT);
case ISL_FORMAT_R16_UINT:
case ISL_FORMAT_R16_FLOAT:
case ISL_FORMAT_R16_SINT:
return (devinfo->gen >= 9 ? format : ISL_FORMAT_R16_UINT);
return (devinfo->ver >= 9 ? format : ISL_FORMAT_R16_UINT);
case ISL_FORMAT_R8_UINT:
case ISL_FORMAT_R8_SINT:
return (devinfo->gen >= 9 ? format : ISL_FORMAT_R8_UINT);
return (devinfo->ver >= 9 ? format : ISL_FORMAT_R8_UINT);
/* Neither the 2/10/10/10 nor the 11/11/10 packed formats are supported
* by the hardware.
@ -161,36 +161,36 @@ isl_lower_storage_image_format(const struct gen_device_info *devinfo,
/* No normalized fixed-point formats are supported by the hardware. */
case ISL_FORMAT_R16G16B16A16_UNORM:
case ISL_FORMAT_R16G16B16A16_SNORM:
return (devinfo->gen >= 11 ? format :
devinfo->gen >= 8 || devinfo->is_haswell ?
return (devinfo->ver >= 11 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
ISL_FORMAT_R16G16B16A16_UINT :
ISL_FORMAT_R32G32_UINT);
case ISL_FORMAT_R8G8B8A8_UNORM:
case ISL_FORMAT_R8G8B8A8_SNORM:
return (devinfo->gen >= 11 ? format :
devinfo->gen >= 8 || devinfo->is_haswell ?
return (devinfo->ver >= 11 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT);
case ISL_FORMAT_R16G16_UNORM:
case ISL_FORMAT_R16G16_SNORM:
return (devinfo->gen >= 11 ? format :
devinfo->gen >= 8 || devinfo->is_haswell ?
return (devinfo->ver >= 11 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT);
case ISL_FORMAT_R8G8_UNORM:
case ISL_FORMAT_R8G8_SNORM:
return (devinfo->gen >= 11 ? format :
devinfo->gen >= 8 || devinfo->is_haswell ?
return (devinfo->ver >= 11 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT);
case ISL_FORMAT_R16_UNORM:
case ISL_FORMAT_R16_SNORM:
return (devinfo->gen >= 11 ? format : ISL_FORMAT_R16_UINT);
return (devinfo->ver >= 11 ? format : ISL_FORMAT_R16_UINT);
case ISL_FORMAT_R8_UNORM:
case ISL_FORMAT_R8_SNORM:
return (devinfo->gen >= 11 ? format : ISL_FORMAT_R8_UINT);
return (devinfo->ver >= 11 ? format : ISL_FORMAT_R8_UINT);
default:
assert(!"Unknown image format");
@ -202,9 +202,9 @@ bool
isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
enum isl_format fmt)
{
if (devinfo->gen >= 9) {
if (devinfo->ver >= 9) {
return true;
} else if (devinfo->gen >= 8 || devinfo->is_haswell) {
} else if (devinfo->ver >= 8 || devinfo->is_haswell) {
return isl_format_get_layout(fmt)->bpb <= 64;
} else {
return isl_format_get_layout(fmt)->bpb <= 32;

28
src/intel/perf/gen_perf.c
View file

@ -182,7 +182,7 @@ register_oa_config(struct gen_perf_config *perf,
gen_perf_append_query_info(perf, 0);
*registered_query = *query;
registered_query->oa_format = devinfo->gen >= 8 ?
registered_query->oa_format = devinfo->ver >= 8 ?
I915_OA_FORMAT_A32u40_A4u32_B8_C8 : I915_OA_FORMAT_A45_B8_C8;
registered_query->oa_metrics_set_id = config_id;
DBG("metric set registered: id = %" PRIu64", guid = %s\n",
@ -392,7 +392,7 @@ compute_topology_builtins(struct gen_perf_config *perf,
*/
perf->sys_vars.subslice_mask = 0;
int bits_per_subslice = devinfo->gen == 11 ? 8 : 3;
int bits_per_subslice = devinfo->ver == 11 ? 8 : 3;
for (int s = 0; s < util_last_bit(devinfo->slice_masks); s++) {
for (int ss = 0; ss < (devinfo->subslice_slice_stride * 8); ss++) {
@ -464,7 +464,7 @@ get_register_queries_function(const struct gen_device_info *devinfo)
if (devinfo->gt == 3)
return gen_oa_register_queries_cflgt3;
}
if (devinfo->gen == 11) {
if (devinfo->ver == 11) {
if (devinfo->is_elkhartlake)
return gen_oa_register_queries_ehl;
return gen_oa_register_queries_icl;
@ -518,7 +518,7 @@ load_pipeline_statistic_metrics(struct gen_perf_config *perf_cfg,
gen_perf_query_add_basic_stat_reg(query, VS_INVOCATION_COUNT,
"N vertex shader invocations");
if (devinfo->gen == 6) {
if (devinfo->ver == 6) {
gen_perf_query_add_stat_reg(query, GEN6_SO_PRIM_STORAGE_NEEDED, 1, 1,
"SO_PRIM_STORAGE_NEEDED",
"N geometry shader stream-out primitives (total)");
@ -567,7 +567,7 @@ load_pipeline_statistic_metrics(struct gen_perf_config *perf_cfg,
gen_perf_query_add_basic_stat_reg(query, CL_PRIMITIVES_COUNT,
"N primitives leaving clipping");
if (devinfo->is_haswell || devinfo->gen == 8) {
if (devinfo->is_haswell || devinfo->ver == 8) {
gen_perf_query_add_stat_reg(query, PS_INVOCATION_COUNT, 1, 4,
"N fragment shader invocations",
"N fragment shader invocations");
@ -579,7 +579,7 @@ load_pipeline_statistic_metrics(struct gen_perf_config *perf_cfg,
gen_perf_query_add_basic_stat_reg(query, PS_DEPTH_COUNT,
"N z-pass fragments");
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
gen_perf_query_add_basic_stat_reg(query, CS_INVOCATION_COUNT,
"N compute shader invocations");
}
@ -1026,7 +1026,7 @@ gen_perf_query_result_read_frequencies(struct gen_perf_query_result *result,
* Documentation says this should be available on Gen9+ but experimentation
* shows that Gen8 reports similar values, so we enable it there too.
*/
if (devinfo->gen < 8)
if (devinfo->ver < 8)
return;
gen8_read_report_clock_ratios(start,
@ -1040,7 +1040,7 @@ gen_perf_query_result_read_frequencies(struct gen_perf_query_result *result,
static inline bool
can_use_mi_rpc_bc_counters(const struct gen_device_info *devinfo)
{
return devinfo->gen <= 11;
return devinfo->ver <= 11;
}
void
@ -1116,7 +1116,7 @@ gen_perf_query_result_read_gt_frequency(struct gen_perf_query_result *result,
const uint32_t start,
const uint32_t end)
{
switch (devinfo->gen) {
switch (devinfo->ver) {
case 7:
case 8:
result->gt_frequency[0] = GET_FIELD(start, GEN7_RPSTAT1_CURR_GT_FREQ) * 50ULL;
@ -1313,7 +1313,7 @@ gen_perf_init_query_fields(struct gen_perf_config *perf_cfg,
add_query_register(layout, GEN_PERF_QUERY_FIELD_TYPE_MI_RPC,
0, 256, 0);
if (devinfo->gen <= 11) {
if (devinfo->ver <= 11) {
struct gen_perf_query_field *field =
add_query_register(layout,
GEN_PERF_QUERY_FIELD_TYPE_SRM_PERFCNT,
@ -1326,20 +1326,20 @@ gen_perf_init_query_fields(struct gen_perf_config *perf_cfg,
field->mask = PERF_CNT_VALUE_MASK;
}
if (devinfo->gen == 8 && !devinfo->is_cherryview) {
if (devinfo->ver == 8 && !devinfo->is_cherryview) {
add_query_register(layout,
GEN_PERF_QUERY_FIELD_TYPE_SRM_RPSTAT,
GEN7_RPSTAT1, 4, 0);
}
if (devinfo->gen >= 9) {
if (devinfo->ver >= 9) {
add_query_register(layout,
GEN_PERF_QUERY_FIELD_TYPE_SRM_RPSTAT,
GEN9_RPSTAT0, 4, 0);
}
if (!can_use_mi_rpc_bc_counters(devinfo)) {
if (devinfo->gen >= 8 && devinfo->gen <= 11) {
if (devinfo->ver >= 8 && devinfo->ver <= 11) {
for (uint32_t i = 0; i < GEN8_N_OA_PERF_B32; i++) {
add_query_register(layout, GEN_PERF_QUERY_FIELD_TYPE_SRM_OA_B,
GEN8_OA_PERF_B32(i), 4, i);
@ -1348,7 +1348,7 @@ gen_perf_init_query_fields(struct gen_perf_config *perf_cfg,
add_query_register(layout, GEN_PERF_QUERY_FIELD_TYPE_SRM_OA_C,
GEN8_OA_PERF_C32(i), 4, i);
}
} else if (devinfo->gen == 12) {
} else if (devinfo->ver == 12) {
for (uint32_t i = 0; i < GEN12_N_OAG_PERF_B32; i++) {
add_query_register(layout, GEN_PERF_QUERY_FIELD_TYPE_SRM_OA_B,
GEN12_OAG_PERF_B32(i), 4, i);

14
src/intel/perf/gen_perf_mdapi.c
View file

@ -37,7 +37,7 @@ gen_perf_query_result_write_mdapi(void *data, uint32_t data_size,
const struct gen_perf_query_info *query,
const struct gen_perf_query_result *result)
{
switch (devinfo->gen) {
switch (devinfo->ver) {
case 7: {
struct gen7_mdapi_metrics *mdapi_data = (struct gen7_mdapi_metrics *) data;
@ -140,7 +140,7 @@ void
gen_perf_register_mdapi_statistic_query(struct gen_perf_config *perf_cfg,
const struct gen_device_info *devinfo)
{
if (!(devinfo->gen >= 7 && devinfo->gen <= 12))
if (!(devinfo->ver >= 7 && devinfo->ver <= 12))
return;
struct gen_perf_query_info *query =
@ -164,7 +164,7 @@ gen_perf_register_mdapi_statistic_query(struct gen_perf_config *perf_cfg,
"N primitives entering clipping");
gen_perf_query_add_basic_stat_reg(query, CL_PRIMITIVES_COUNT,
"N primitives leaving clipping");
if (devinfo->is_haswell || devinfo->gen == 8) {
if (devinfo->is_haswell || devinfo->ver == 8) {
gen_perf_query_add_stat_reg(query, PS_INVOCATION_COUNT, 1, 4,
"N fragment shader invocations",
"N fragment shader invocations");
@ -176,12 +176,12 @@ gen_perf_register_mdapi_statistic_query(struct gen_perf_config *perf_cfg,
"N TCS shader invocations");
gen_perf_query_add_basic_stat_reg(query, DS_INVOCATION_COUNT,
"N TES shader invocations");
if (devinfo->gen >= 7) {
if (devinfo->ver >= 7) {
gen_perf_query_add_basic_stat_reg(query, CS_INVOCATION_COUNT,
"N compute shader invocations");
}
if (devinfo->gen >= 10) {
if (devinfo->ver >= 10) {
/* Reuse existing CS invocation register until we can expose this new
* one.
*/
@ -237,10 +237,10 @@ gen_perf_register_mdapi_oa_query(struct gen_perf_config *perf,
/* MDAPI requires different structures for pretty much every generation
* (right now we have definitions for gen 7 to 12).
*/
if (!(devinfo->gen >= 7 && devinfo->gen <= 12))
if (!(devinfo->ver >= 7 && devinfo->ver <= 12))
return;
switch (devinfo->gen) {
switch (devinfo->ver) {
case 7: {
query = gen_perf_append_query_info(perf, 1 + 45 + 16 + 7);
query->oa_format = I915_OA_FORMAT_A45_B8_C8;

2
src/intel/perf/gen_perf_mdapi.h
View file

@ -136,7 +136,7 @@ static inline void gen_perf_query_mdapi_write_marker(void *data, uint32_t data_s
const struct gen_device_info *devinfo,
uint64_t value)
{
switch (devinfo->gen) {
switch (devinfo->ver) {
case 8: {
if (data_size < sizeof(struct gen8_mdapi_metrics))
return;

10
src/intel/perf/gen_perf_query.c
View file

@ -780,7 +780,7 @@ gen_perf_begin_query(struct gen_perf_context *perf_ctx,
*/
int a_counter_in_bits = 32;
if (devinfo->gen >= 8)
if (devinfo->ver >= 8)
a_counter_in_bits = 40;
uint64_t overflow_period = pow(2, a_counter_in_bits) / (perf_cfg->sys_vars.n_eus *
@ -1194,8 +1194,8 @@ static bool
oa_report_ctx_id_valid(const struct gen_device_info *devinfo,
const uint32_t *report)
{
assert(devinfo->gen >= 8);
if (devinfo->gen == 8)
assert(devinfo->ver >= 8);
if (devinfo->ver == 8)
return (report[0] & (1 << 25)) != 0;
return (report[0] & (1 << 16)) != 0;
}
@ -1247,7 +1247,7 @@ accumulate_oa_reports(struct gen_perf_context *perf_ctx,
/* On Gen12+ OA reports are sourced from per context counters, so we don't
* ever have to look at the global OA buffer. Yey \o/
*/
if (perf_ctx->devinfo->gen >= 12) {
if (perf_ctx->devinfo->ver >= 12) {
last = start;
goto end;
}
@ -1309,7 +1309,7 @@ accumulate_oa_reports(struct gen_perf_context *perf_ctx,
* For Haswell we can rely on the HW to stop the progress
* of OA counters while any other context is acctive.
*/
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
/* Consider that the current report matches our context only if
* the report says the report ID is valid.
*/

2
src/intel/tools/aub_read.c
View file

@ -139,7 +139,7 @@ handle_trace_block(struct aub_read *read, const uint32_t *p)
int header_length = p[0] & 0xffff;
enum drm_i915_gem_engine_class engine = I915_ENGINE_CLASS_RENDER;
const void *data = p + header_length + 2;
uint64_t address = intel_48b_address((read->devinfo.gen >= 8 ? ((uint64_t) p[5] << 32) : 0) |
uint64_t address = intel_48b_address((read->devinfo.ver >= 8 ? ((uint64_t) p[5] << 32) : 0) |
((uint64_t) p[3]));
uint32_t size = p[4];

10
src/intel/tools/aub_write.c
View file

@ -161,7 +161,7 @@ aub_file_init(struct aub_file *aub, FILE *file, FILE *debug, uint16_t pci_id, co
aub->pci_id = pci_id;
fail_if(!gen_get_device_info_from_pci_id(pci_id, &aub->devinfo),
"failed to identify chipset=0x%x\n", pci_id);
aub->addr_bits = aub->devinfo.gen >= 8 ? 48 : 32;
aub->addr_bits = aub->devinfo.ver >= 8 ? 48 : 32;
aub_write_header(aub, app_name);
@ -478,9 +478,9 @@ get_context_init(const struct gen_device_info *devinfo,
[I915_ENGINE_CLASS_VIDEO] = gen10_video_context_init,
};
assert(devinfo->gen >= 8);
assert(devinfo->ver >= 8);
if (devinfo->gen <= 10)
if (devinfo->ver <= 10)
gen8_contexts[engine_class](params, data, size);
else
gen10_contexts[engine_class](params, data, size);
@ -743,7 +743,7 @@ aub_dump_ring_buffer_execlist(struct aub_file *aub,
static void
aub_dump_execlist(struct aub_file *aub, const struct engine *cs, uint64_t descriptor)
{
if (aub->devinfo.gen >= 11) {
if (aub->devinfo.ver >= 11) {
register_write_out(aub, cs->elsq_reg, descriptor & 0xFFFFFFFF);
register_write_out(aub, cs->elsq_reg + sizeof(uint32_t), descriptor >> 32);
register_write_out(aub, cs->control_reg, 1);
@ -758,7 +758,7 @@ aub_dump_execlist(struct aub_file *aub, const struct engine *cs, uint64_t descri
dword_out(aub, cs->status_reg);
dword_out(aub, AUB_MEM_TRACE_REGISTER_SIZE_DWORD |
AUB_MEM_TRACE_REGISTER_SPACE_MMIO);
if (aub->devinfo.gen >= 11) {
if (aub->devinfo.ver >= 11) {
dword_out(aub, 0x00000001); /* mask lo */
dword_out(aub, 0x00000000); /* mask hi */
dword_out(aub, 0x00000001);

4
src/intel/tools/aub_write.h
View file

@ -109,7 +109,7 @@ void aub_file_finish(struct aub_file *aub);
static inline bool aub_use_execlists(const struct aub_file *aub)
{
return aub->devinfo.gen >= 8;
return aub->devinfo.ver >= 8;
}
uint32_t aub_gtt_size(struct aub_file *aub);
@ -117,7 +117,7 @@ uint32_t aub_gtt_size(struct aub_file *aub);
static inline void
aub_write_reloc(const struct gen_device_info *devinfo, void *p, uint64_t v)
{
if (devinfo->gen >= 8) {
if (devinfo->ver >= 8) {
*(uint64_t *)p = intel_canonical_address(v);
} else {
*(uint32_t *)p = v;

10
src/intel/tools/aubinator_error_decode.c
View file

@ -177,7 +177,7 @@ instdone_register_for_ring(const struct gen_device_info *devinfo,
switch (class) {
case I915_ENGINE_CLASS_RENDER:
if (devinfo->gen == 6)
if (devinfo->ver == 6)
return "INSTDONE_2";
else
return "INSTDONE_1";
@ -261,9 +261,9 @@ print_i965_fence(struct gen_device_info *devinfo, uint64_t fence)
static void
print_fence(struct gen_device_info *devinfo, uint64_t fence)
{
if (devinfo->gen == 6 || devinfo->gen == 7) {
if (devinfo->ver == 6 || devinfo->ver == 7) {
return print_snb_fence(devinfo, fence);
} else if (devinfo->gen == 4 || devinfo->gen == 5) {
} else if (devinfo->ver == 4 || devinfo->ver == 5) {
return print_i965_fence(devinfo, fence);
}
}
@ -273,7 +273,7 @@ print_fault_data(struct gen_device_info *devinfo, uint32_t data1, uint32_t data0
{
uint64_t address;
if (devinfo->gen < 8)
if (devinfo->ver < 8)
return;
address = ((uint64_t)(data0) << 12) | ((uint64_t)data1 & 0xf) << 44;
@ -512,7 +512,7 @@ read_data_file(FILE *file)
exit(EXIT_FAILURE);
}
printf("Detected GEN%i chipset\n", devinfo.gen);
printf("Detected GEN%i chipset\n", devinfo.ver);
if (xml_path == NULL)
spec = intel_spec_load(&devinfo);

12
src/intel/tools/i965_asm.c
View file

@ -123,7 +123,7 @@ i965_disasm_init(uint16_t pci_id)
static bool
i965_postprocess_labels()
{
if (p->devinfo->gen < 6) {
if (p->devinfo->ver < 6) {
return true;
}
@ -150,9 +150,9 @@ i965_postprocess_labels()
case BRW_OPCODE_ELSE:
case BRW_OPCODE_ENDIF:
case BRW_OPCODE_WHILE:
if (p->devinfo->gen >= 7) {
if (p->devinfo->ver >= 7) {
brw_inst_set_jip(p->devinfo, inst, relative_offset);
} else if (p->devinfo->gen == 6) {
} else if (p->devinfo->ver == 6) {
brw_inst_set_gen6_jump_count(p->devinfo, inst, relative_offset);
}
break;
@ -169,11 +169,11 @@ i965_postprocess_labels()
switch (opcode) {
case BRW_OPCODE_IF:
case BRW_OPCODE_ELSE:
if (p->devinfo->gen > 7) {
if (p->devinfo->ver > 7) {
brw_inst_set_uip(p->devinfo, inst, relative_offset);
} else if (p->devinfo->gen == 7) {
} else if (p->devinfo->ver == 7) {
brw_inst_set_uip(p->devinfo, inst, relative_offset);
} else if (p->devinfo->gen == 6) {
} else if (p->devinfo->ver == 6) {
// Nothing
}
break;

78
src/intel/tools/i965_gram.y
View file

@ -292,7 +292,7 @@ i965_asm_set_instruction_options(struct brw_codegen *p,
options.no_dd_clear);
brw_inst_set_debug_control(p->devinfo, brw_last_inst,
options.debug_control);
if (p->devinfo->gen >= 6)
if (p->devinfo->ver >= 6)
brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
options.acc_wr_control);
brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
@ -304,7 +304,7 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
struct brw_reg *reg,
struct options options)
{
if (p->devinfo->gen <= 6) {
if (p->devinfo->ver <= 6) {
if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
!options.is_compr)
@ -679,7 +679,7 @@ unaryinstruction:
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
$4.cond_modifier);
if (p->devinfo->gen >= 7) {
if (p->devinfo->ver >= 7) {
if ($2 != BRW_OPCODE_DIM) {
brw_inst_set_flag_reg_nr(p->devinfo,
brw_last_inst,
@ -700,7 +700,7 @@ unaryinstruction:
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
$8.qtr_ctrl);
if (p->devinfo->gen >= 7)
if (p->devinfo->ver >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$8.nib_ctrl);
}
@ -735,7 +735,7 @@ binaryinstruction:
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
$4.cond_modifier);
if (p->devinfo->gen >= 7) {
if (p->devinfo->ver >= 7) {
brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
$4.flag_reg_nr);
brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
@ -748,7 +748,7 @@ binaryinstruction:
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
$9.qtr_ctrl);
if (p->devinfo->gen >= 7)
if (p->devinfo->ver >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$9.nib_ctrl);
@ -787,7 +787,7 @@ binaryaccinstruction:
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
$4.cond_modifier);
if (p->devinfo->gen >= 7) {
if (p->devinfo->ver >= 7) {
if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
brw_inst_set_flag_reg_nr(p->devinfo,
brw_last_inst,
@ -804,7 +804,7 @@ binaryaccinstruction:
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
$9.qtr_ctrl);
if (p->devinfo->gen >= 7)
if (p->devinfo->ver >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$9.nib_ctrl);
}
@ -837,7 +837,7 @@ mathinstruction:
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
$9.qtr_ctrl);
if (p->devinfo->gen >= 7)
if (p->devinfo->ver >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$9.nib_ctrl);
@ -882,7 +882,7 @@ ternaryinstruction:
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
$4.cond_modifier);
if (p->devinfo->gen >= 7) {
if (p->devinfo->ver >= 7) {
brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
$4.flag_reg_nr);
brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
@ -895,7 +895,7 @@ ternaryinstruction:
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
$10.qtr_ctrl);
if (p->devinfo->gen >= 7)
if (p->devinfo->ver >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$10.nib_ctrl);
}
@ -946,7 +946,7 @@ sendinstruction:
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
$8.qtr_ctrl);
if (p->devinfo->gen >= 7)
if (p->devinfo->ver >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$8.nib_ctrl);
@ -969,7 +969,7 @@ sendinstruction:
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
$9.qtr_ctrl);
if (p->devinfo->gen >= 7)
if (p->devinfo->ver >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$9.nib_ctrl);
@ -988,7 +988,7 @@ sendinstruction:
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
$9.qtr_ctrl);
if (p->devinfo->gen >= 7)
if (p->devinfo->ver >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$9.nib_ctrl);
@ -1016,7 +1016,7 @@ sendinstruction:
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
$10.qtr_ctrl);
if (p->devinfo->gen >= 7)
if (p->devinfo->ver >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$10.nib_ctrl);
@ -1040,7 +1040,7 @@ sendinstruction:
brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
$10.qtr_ctrl);
if (p->devinfo->gen >= 7)
if (p->devinfo->ver >= 7)
brw_inst_set_nib_control(p->devinfo, brw_last_inst,
$10.nib_ctrl);
@ -1108,13 +1108,13 @@ branchinstruction:
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen == 6) {
if (p->devinfo->ver == 6) {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
} else if (p->devinfo->gen == 7) {
} else if (p->devinfo->ver == 7) {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
@ -1153,13 +1153,13 @@ branchinstruction:
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
if (p->devinfo->gen == 6) {
if (p->devinfo->ver == 6) {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
} else if (p->devinfo->gen == 7) {
} else if (p->devinfo->ver == 7) {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
@ -1168,7 +1168,7 @@ branchinstruction:
} else {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
if (p->devinfo->gen < 12)
if (p->devinfo->ver < 12)
brw_set_src0(p, brw_last_inst, brw_imm_d(0));
}
}
@ -1197,7 +1197,7 @@ branchinstruction:
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen == 6) {
if (p->devinfo->ver == 6) {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
brw_set_src0(p, brw_last_inst,
vec1(retype(brw_null_reg(),
@ -1205,7 +1205,7 @@ branchinstruction:
brw_set_src1(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
} else if (p->devinfo->gen == 7) {
} else if (p->devinfo->ver == 7) {
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
@ -1217,7 +1217,7 @@ branchinstruction:
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
if (p->devinfo->gen < 12)
if (p->devinfo->ver < 12)
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
}
@ -1249,14 +1249,14 @@ branchinstruction:
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen == 6) {
if (p->devinfo->ver == 6) {
brw_set_src0(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
brw_set_src1(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
} else if (p->devinfo->gen == 7) {
} else if (p->devinfo->ver == 7) {
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
@ -1268,7 +1268,7 @@ branchinstruction:
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
if (p->devinfo->gen < 12)
if (p->devinfo->ver < 12)
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
}
@ -1304,7 +1304,7 @@ breakinstruction:
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen >= 8) {
if (p->devinfo->ver >= 8) {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
@ -1344,7 +1344,7 @@ breakinstruction:
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
if (p->devinfo->gen >= 8) {
if (p->devinfo->ver >= 8) {
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
} else {
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
@ -1364,7 +1364,7 @@ breakinstruction:
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, brw_ip_reg());
if (p->devinfo->gen >= 8) {
if (p->devinfo->ver >= 8) {
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
} else {
brw_set_src0(p, brw_last_inst, brw_ip_reg());
@ -1400,12 +1400,12 @@ loopinstruction:
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen >= 8) {
if (p->devinfo->ver >= 8) {
brw_set_dest(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
} else if (p->devinfo->gen == 7) {
} else if (p->devinfo->ver == 7) {
brw_set_dest(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
@ -1443,7 +1443,7 @@ loopinstruction:
| DO execsize instoptions
{
brw_next_insn(p, $1);
if (p->devinfo->gen < 6) {
if (p->devinfo->ver < 6) {
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
i965_asm_set_instruction_options(p, $3);
brw_set_dest(p, brw_last_inst, brw_null_reg());
@ -1823,7 +1823,7 @@ indirectmsgreg:
addrreg:
ADDRREG subregnum
{
int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
int subnr = (p->devinfo->ver >= 8) ? 16 : 8;
if ($2 > subnr)
error(&@2, "Address sub register number %d"
@ -1839,7 +1839,7 @@ accreg:
ACCREG subregnum
{
int nr_reg;
if (p->devinfo->gen < 8)
if (p->devinfo->ver < 8)
nr_reg = 2;
else
nr_reg = 10;
@ -1859,7 +1859,7 @@ flagreg:
FLAGREG subregnum
{
// SNB = 1 flag reg and IVB+ = 2 flag reg
int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
int nr_reg = (p->devinfo->ver >= 7) ? 2 : 1;
int subnr = nr_reg;
if ($1 > nr_reg)
@ -1891,7 +1891,7 @@ maskreg:
notifyreg:
NOTIFYREG subregnum
{
int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
int subnr = (p->devinfo->ver >= 11) ? 2 : 3;
if ($2 > subnr)
error(&@2, "Notification sub register number %d"
" out of range\n", $2);
@ -1957,9 +1957,9 @@ performancereg:
PERFORMANCEREG subregnum
{
int subnr;
if (p->devinfo->gen >= 10)
if (p->devinfo->ver >= 10)
subnr = 5;
else if (p->devinfo->gen <= 8)
else if (p->devinfo->ver <= 8)
subnr = 3;
else
subnr = 4;

12
src/intel/tools/intel_dump_gpu.c
View file

@ -124,7 +124,7 @@ ensure_device_info(int fd)
fail_if(!gen_get_device_info_from_fd(fd, &devinfo),
"failed to identify chipset.\n");
device = devinfo.chipset_id;
} else if (devinfo.gen == 0) {
} else if (devinfo.ver == 0) {
fail_if(!gen_get_device_info_from_pci_id(device, &devinfo),
"failed to identify chipset.\n");
}
@ -229,7 +229,7 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2 *execbuffer2)
if (verbose)
printf("[running, output file %s, chipset id 0x%04x, gen %d]\n",
output_filename, device, devinfo.gen);
output_filename, device, devinfo.ver);
}
if (aub_use_execlists(&aub_file))
@ -490,7 +490,7 @@ maybe_init(int fd)
if (verbose)
printf("[running, output file %s, chipset id 0x%04x, gen %d]\n",
output_filename, device, devinfo.gen);
output_filename, device, devinfo.ver);
}
__attribute__ ((visibility ("default"))) int
@ -560,7 +560,7 @@ ioctl(int fd, unsigned long request, ...)
return 0;
case I915_PARAM_HAS_EXEC_SOFTPIN:
*getparam->value = devinfo.gen >= 8 && !devinfo.is_cherryview;
*getparam->value = devinfo.ver >= 8 && !devinfo.is_cherryview;
return 0;
default:
@ -581,7 +581,7 @@ ioctl(int fd, unsigned long request, ...)
case I915_CONTEXT_PARAM_GTT_SIZE:
if (devinfo.is_elkhartlake)
getparam->value = 1ull << 36;
else if (devinfo.gen >= 8 && !devinfo.is_cherryview)
else if (devinfo.ver >= 8 && !devinfo.is_cherryview)
getparam->value = 1ull << 48;
else
getparam->value = 1ull << 31;
@ -777,7 +777,7 @@ munmap_init_helper(void *addr, size_t length)
static void __attribute__ ((destructor))
fini(void)
{
if (devinfo.gen != 0) {
if (devinfo.ver != 0) {
free(output_filename);
if (!capture_finished)
aub_file_finish(&aub_file);

8
src/intel/tools/intel_noop_drm_shim.c
View file

@ -124,7 +124,7 @@ i915_ioctl_gem_context_getparam(int fd, unsigned long request, void *arg)
struct drm_i915_gem_context_param *param = arg;
if (param->param == I915_CONTEXT_PARAM_GTT_SIZE) {
if (i915.devinfo.gen >= 8 && !i915.devinfo.is_cherryview)
if (i915.devinfo.ver >= 8 && !i915.devinfo.is_cherryview)
param->value = 1ull << 48;
else
param->value = 1ull << 31;
@ -151,9 +151,9 @@ i915_ioctl_get_param(int fd, unsigned long request, void *arg)
*gp->value = i915.devinfo.timestamp_frequency;
return 0;
case I915_PARAM_HAS_ALIASING_PPGTT:
if (i915.devinfo.gen < 6)
if (i915.devinfo.ver < 6)
*gp->value = I915_GEM_PPGTT_NONE;
else if (i915.devinfo.gen <= 7)
else if (i915.devinfo.ver <= 7)
*gp->value = I915_GEM_PPGTT_ALIASING;
else
*gp->value = I915_GEM_PPGTT_FULL;
@ -318,7 +318,7 @@ i915_gem_get_aperture(int fd, unsigned long request, void *arg)
{
struct drm_i915_gem_get_aperture *aperture = arg;
if (i915.devinfo.gen >= 8 &&
if (i915.devinfo.ver >= 8 &&
!i915.devinfo.is_cherryview) {
aperture->aper_size = 1ull << 48;
aperture->aper_available_size = 1ull << 48;

12
src/intel/vulkan/anv_allocator.c
View file

@ -1455,18 +1455,18 @@ anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool,
* For, Gen11+, scratch space allocation is based on the number of threads
* in the base configuration.
*/
if (devinfo->gen == 12)
if (devinfo->ver == 12)
subslices = (devinfo->is_dg1 || devinfo->gt == 2 ? 6 : 2);
else if (devinfo->gen == 11)
else if (devinfo->ver == 11)
subslices = 8;
else if (devinfo->gen >= 9)
else if (devinfo->ver >= 9)
subslices = 4 * devinfo->num_slices;
unsigned scratch_ids_per_subslice;
if (devinfo->gen >= 12) {
if (devinfo->ver >= 12) {
/* Same as ICL below, but with 16 EUs. */
scratch_ids_per_subslice = 16 * 8;
} else if (devinfo->gen == 11) {
} else if (devinfo->ver == 11) {
/* The MEDIA_VFE_STATE docs say:
*
* "Starting with this configuration, the Maximum Number of
@ -1611,7 +1611,7 @@ anv_device_get_bo_align(struct anv_device *device,
enum anv_bo_alloc_flags alloc_flags)
{
/* Gen12 CCS surface addresses need to be 64K aligned. */
if (device->info.gen >= 12 && (alloc_flags & ANV_BO_ALLOC_IMPLICIT_CCS))
if (device->info.ver >= 12 && (alloc_flags & ANV_BO_ALLOC_IMPLICIT_CCS))
return 64 * 1024;
return 4096;

2
src/intel/vulkan/anv_batch_chain.c
View file

@ -586,7 +586,7 @@ emit_batch_buffer_start(struct anv_cmd_buffer *cmd_buffer,
GEN8_MI_BATCH_BUFFER_START_length - GEN8_MI_BATCH_BUFFER_START_length_bias;
anv_batch_emit(&cmd_buffer->batch, GEN8_MI_BATCH_BUFFER_START, bbs) {
bbs.DWordLength = cmd_buffer->device->info.gen < 8 ?
bbs.DWordLength = cmd_buffer->device->info.ver < 8 ?
gen7_length : gen8_length;
bbs.SecondLevelBatchBuffer = Firstlevelbatch;
bbs.AddressSpaceIndicator = ASI_PPGTT;

4
src/intel/vulkan/anv_blorp.c
View file

@ -96,7 +96,7 @@ anv_device_init_blorp(struct anv_device *device)
device->blorp.compiler = device->physical->compiler;
device->blorp.lookup_shader = lookup_blorp_shader;
device->blorp.upload_shader = upload_blorp_shader;
switch (device->info.genx10) {
switch (device->info.verx10) {
case 70:
device->blorp.exec = gen7_blorp_exec;
break;
@ -257,7 +257,7 @@ get_blorp_surf_for_anv_image(const struct anv_device *device,
anv_image_get_clear_color_addr(device, image, aspect);
blorp_surf->clear_color_addr = anv_to_blorp_address(clear_color_addr);
} else if (aspect & VK_IMAGE_ASPECT_DEPTH_BIT) {
if (device->info.gen >= 10) {
if (device->info.ver >= 10) {
/* Vulkan always clears to 1.0. On gen < 10, we set that directly
* in the state packet. For gen >= 10, must provide the clear
* value in a buffer. We have a single global buffer that stores

2
src/intel/vulkan/anv_cmd_buffer.c
View file

@ -1063,7 +1063,7 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
return (struct anv_state) { .offset = 0 };
const unsigned push_constant_alignment =
cmd_buffer->device->info.gen < 8 ? 32 : 64;
cmd_buffer->device->info.ver < 8 ? 32 : 64;
const unsigned aligned_total_push_constants_size =
ALIGN(total_push_constants_size, push_constant_alignment);
struct anv_state state;

4
src/intel/vulkan/anv_descriptor_set.c
View file

@ -70,7 +70,7 @@ anv_descriptor_data_for_type(const struct anv_physical_device *device,
case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
data = ANV_DESCRIPTOR_SURFACE_STATE;
if (device->info.gen < 9)
if (device->info.ver < 9)
data |= ANV_DESCRIPTOR_IMAGE_PARAM;
if (device->has_bindless_images)
data |= ANV_DESCRIPTOR_STORAGE_IMAGE;
@ -110,7 +110,7 @@ anv_descriptor_data_for_type(const struct anv_physical_device *device,
* VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT because they already must
* have identity swizzle.
*/
if (device->info.gen == 7 && !device->info.is_haswell &&
if (device->info.ver == 7 && !device->info.is_haswell &&
(type == VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE ||
type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER))
data |= ANV_DESCRIPTOR_TEXTURE_SWIZZLE;

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