v2: rework to use Rust closure for worker job function
v3: split preparatory restructuring into separate commit
v4: parallelize link and compile, adjust thread/job count
v5: split out naming changes to later commit, move validation to api/
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
v2: rework to use Rust closures for passed-in job function
v3: drop mutability requirement on queue for adding a job
v4: prevent external creation of fences, return from add_job_sync()
v5: add CPU count utility function based on util_get_cpu_caps()
v6: use &CStr for queue name for convenience
v7: make fence Send + Sync and don't require mutability for waiting
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
This allows for a later refactor to share linking code between
clBuildProgram and clLinkProgram in which the device build is borrowed
mutably.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
We need to release user_ptr resources earlier, so we don't keep stale
references around, but for that to happen we also need to know which
resource is a user_ptr one in the first place.
Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36701>
error: hiding a lifetime that's elided elsewhere is confusing
--> ../src/gallium/frontends/rusticl/util/ptr.rs:166:18
|
166 | pub fn entry(&mut self, ptr: P) -> Entry<P, T> {
| ^^^^^^^^^ ----------- the same lifetime is hidden here
| |
| the lifetime is elided here
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36747>
Now that we lower all load_per_vertex_input to
r600_load_per_vertex_input we can remove some dead code
and also change the intrinsic to use only one source value.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
Extend the lowering of indirect GS array inputs to include
all indirect access. This replaces
r600_gs_load_deref_io_to_indirect_per_vertex_input
which was restricted to vec4 POS inputs. The
new lowering pass works in all vayings and all types, so we
can also drop the call to nir_lower_indirect_derefs.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
When the code is first generated constants are loaded to registers, so to
avoid indirect array register access that can be resolved as a direct direct
access we have to check whether the address register is loaded
with a constant value.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
nir_intrinsic_load_per_vertex_input has two source values, indirect access
by using the first value is already handled, but accessing arrays with
the second index was missing but became relevant with handling most IO
optimizations with nir_opt_varyings.
Fixes: 37ae4df3e4 ("glsl: remove most IO optimizations that are replaced by nir_opt_varyings")
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
This is a preparation for the next patch that will fix
indirect access using the second index of load_per_vertex_input
Fixes: 37ae4df3e4 ("glsl: remove most IO optimizations that are replaced by nir_opt_varyings")
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
In the case where gbm fails to init, we use our entire format list. That
became a problem in commit 642c4cf2b2 when some formats were added to the
list that X can't handle. This leads to X crashing when using glx and
trying to use certain visuals.
An easily testable manifestation of this crash is to run piglit's
glx-create-context-ext-no-config-context under Xwayland in a virtual
machine that has no gpu, whilst using zink. Much like our CI does for some
jobs.
Fixes: 642c4cf2b2 ("dril: add BGR{X,A}8888 and RGB{X,A}8888")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36575>
util_perfetto_init() was called in some places, util_cpu_trace_init()
was called in other places, and some places used tracing without ever
calling either of them
util_cpu_trace_init() is now guaranteed to be called:
* on gallium screen create
* on VK instance create
thus no driver/frontend/etc should ever need to call this manually
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36628>
GFX12 seems to behave slightly differently. Setting these bits to TRUE
causes zero-area triangles to not pass the primitive clipping stage.
So, the actual number of primitives output by the primitive clipping
stage was wrong.
After digging a lot, it seems PAL doesn't set these bits either on
GFX12.
CC: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36670>
We only do minimal checks to ensure that copy propagation doesn't break
the readport setup, but we don't update the groups readport setup. So
before scheduling the group do this update. Also check the readport
constellation when scheduling a group is finished.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36572>
- If a readport reservation is not successful then we have to reset the
readport reservation.
- Since the scheduler can add instructions in any order, we have to
update the readports in the same order the slots were filled when
re-evaluating.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36572>
Now that we track the free slots right away, we can make use of this
information when testing whether a vec instruction can be scheduled into
a trans slot.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36584>
Lowering u2f64 and i2f64 will create such instructions and with that
the ALU groups are filled without the need to do scheduler trickery with
two-slot ops that have also two dest registers.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36587>
