If the last owner thread has just unset the alive status and released
the watchdog, the new owner thread could have acquired to abort
unexpectedly if the ownership transfer occurs right before the next
owner's warn order. So we must set watchdog alive for new owner so that
it can properly check ring alive status in the next warn order.
Cc: mesa-stable
Acked-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34135>
A recent change now requires the kvm runner tag to be explicitly listed
for jobs that need to run on runners with KVM capability.
This ensures the jobs are scheduled on compatible runners.
Cc: mesa-stable
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34120>
Register spilling can cause us to require thread local storage (tls).
However, we were not adjusting the tls stack size space to account for
the tls needed for the extra xfb shader when transform feedback is
needed. We noticed this when testing register allocation in the
OpenGL CTS (for testing we had forced spilling where none happened
before).
Cc: mesa-stable
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33935>
Both GC7000 GPUs have the RA_WRITES_DEPTH feature, which needs a bit
more prodding to have valid fragcoord.zw components present in the
shader. This has been fixed by the previous commit, so we can remove
the related fails from the CI expectation.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34081>
On GPUs with the RA_WRITE_DEPTH feature, passing Z and/or W values
to SH can be gated. It doesn't have any impact on performance, so
maybe it's just to be able to free those register slots for other,
currently unknown, values. For now simply enable passing both Z and
W to SH unconditionally to make those GPUs behave like the ones
without the RA_WRITE_DEPTH feature.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34081>
Update to rnndb commit 51dbdbd9b83a
("rnndb: document RA depth W forwarding gate").
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34081>
require_full_quads is incorrect because it isn't actually enabled by
quad operations. Use the newly-introduced needs_quad_helper_invocations
instead.
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Fixes: 264d8a6766 ("ir3: Set need_full_quad depending on info.fs.require_full_quads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33862>
This is needed on Qualcomm, where there are separate fields to enable
just 3 fragments and all 4 fragments.
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Fixes: 264d8a6766 ("ir3: Set need_full_quad depending on info.fs.require_full_quads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33862>
This currently treats coarse and fine derivatives the same, but Qualcomm
needs to know whether just coarse derivatives are used or fine
derivatives/quad ops are also used. Rename this to
needs_coarse_quad_helper_invocations make clear the difference from the
new field, needs_full_quad_helper_invocations.
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Fixes: 264d8a6766 ("ir3: Set need_full_quad depending on info.fs.require_full_quads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33862>
We no longer need finalize_nir and thus we don't need to support
texcoord as well. This is a nice rs state cleanup.
This effectivelly reverts commits
0ac6801970 and
d4b8e8a481. Also import the previous
location fixup from the state tracker, which was removed when the
unconditional nir_opt_varying pass was introduced.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33961>
This was added so we could report compile failures. Since we can
now just do that simply from create_vs/fs_state there is no need
for finalize_nir anymore.
Move the optimization loop to the beginning of create_vs/fs_state.
This could be probably optimized a bit more, but right now there
should be no functional change, we can improve the pass order later.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33961>
these fields are misleading and should always be replaced by either:
* the framebuffer width/height
* explicit function params to specify width/height
Co-authored-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33946>
The register is usually a few dwords ahead of the memory value used by
the kernel, which can lead to an inaccurate calculation of where the SQE
is.
To compensate for the more accurate rptr, increase the lookback
slightly.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34063>
For RB, it's not convenient to use a gpuaddr because of how the GPU
addresses wrap around. Instead pass the host address to the renamed
highlight_addr(), so that we can use it directly.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34063>
This is needed for SPIR-V 1.6 support in OpenCL. This capability enables
the Uniform and UniformId decorations which prior were Shader only.
The CTS ends up using those decorations on function arguments, but we can
just ignore handling them there for now.
Fixes the spirv16_uniformdecoration_uniform and
spirv16_uniformdecoration_uniformid CL CTS test inside test_spirv_new.
Fixes: bb6d371c0e ("rusticl: support SPIR-V 1.5 and 1.6")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34004>
