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Author SHA1 Message Date
Francisco Jerez
4868408e6e intel/genxml: Add 3DSTATE_PS definitions needed for dual-SIMD8 dispatch on Gfx12+. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
 2023-12-22 18:05:31 +00:00
Jordan Justen
30faa7a483 anv, iris, intel/genxml: Update 3DSTATE_HS for xe2 
Update 3DSTATE_HS programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen
8ba9988858 anv, iris, intel/genxml: Update 3DSTATE_GS for xe2 
Update 3DSTATE_GS programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen
a659b1f0c0 anv, blorp, iris, intel/genxml: Update 3DSTATE_PS_EXTRA for xe2 
Update 3DSTATE_PS_EXTRA programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen
5548e6a478 anv, blorp, iris, intel/genxml: Update 3DSTATE_VS for xe2 
Update 3DSTATE_VS programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen
f170995e66 anv, blorp, iris: Update 3DSTATE_PS programming for xe2 
Rework:
 * Jordan: Move code into intel_update_ps_state()

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun
80d9294d2d intel/isl: update 3DSTATE_STENCIL_BUFFER (xe2) 
Update xml file and adjust driver code to compile.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun
2a49a598ce intel/genxml: update 3DSTATE_DEPTH_BUFFER instruction (xe2) 
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Jordan Justen
99eadc2ecb intel/genxml: Add UNIFIED_COMPRESSION_FORMAT enum for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun
2c41811808 intel/genxml: update 3DSTATE_WM_HZ_OP instruction (xe2) 
The depth clear value is provided from 3DSTATE_WM_HZ_OP now.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun
5d4a995294 intel/genxml: Remove 3DSTATE_CLEAR_PARAMS instruction (xe2) 
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Sagar Ghuge
2aea09c8de intel/genxml: Add BCS/VD0 aux table base address register 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26409>
 2023-12-14 00:53:15 +00:00
José Roberto de Souza
6d42333b16 intel/genxml/xe2: Update PIPELINE_SELECT 
'Media Sampler DOP Clock Gate Enable' and 'Force Media Awake' don't
exist anymore.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26403>
 2023-12-07 14:16:18 +00:00
José Roberto de Souza
9898c719a2 intel/genxml/xe2: Update PIPE_CONTROL 
'Tile Cache Flush Enable' and 'Generic Media State Clear' are now
reserved bits in gfx20+.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26403>
 2023-12-07 14:16:18 +00:00
Yonggang Luo
36480b4d02 intel: Generate source file with utf-8 encoding from mako template 
Make them generated in consistent way

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26515>
 2023-12-07 12:41:07 +00:00
Jordan Justen
05632fc9eb intel/genxml: Update 3DSTATE_TE for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26438>
 2023-12-02 02:22:07 +00:00
Rohan Garg
a499be0ee3 intel/genxml: Update IDD for new fields 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Rohan Garg
c916038b89 intel/genxml: Update COMPUTE_WALKER_BODY for xe2 
Reworks:
 * Caio: Change patch to only add COMPUTE_WALKER_BODY and
   EXECUTE_INDIRECT_DISPATCH (that uses it).

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Rohan Garg
ef1c1ca821 intel/genxml: Add the preferred slm size enum for xe2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Jordan Justen
bdb9c70f84 intel/genxml: Update INTERFACE_DESCRIPTOR_DATA for xe2 
Reworks:
 * Caio: Remove "Mask Stack Exception Enable", not present in BSpec.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Jordan Justen
aafdf59dfe intel/genxml: Update COMPUTE_WALKER for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Rohan Garg
7a9e82e82f genxml/12.5: Add the EXECUTE_INDIRECT_DISPATCH instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
4229757309 genxml/12.5: Add the EXECUTE_INDIRECT_DRAW instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00
Paulo Zanoni
544c5c006c intel/genxml: add the Gen12+ TR-TT registers 
These are the registers we're going to use for now.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26036>
 2023-11-04 02:06:52 +00:00
Francisco Jerez
f0d24b155b intel/xehp+: Adjust TBIMR batch size based on slice count. 
This programs a TBIMR batch size equal to 128 polygons per slice in
order to match the hardware spec recommendation (BSpec 68436).  This
has been confirmed to improve performance slightly relative to the
hardware default batch size of 256 polygons.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493>
 2023-10-27 14:50:42 -07:00
Francisco Jerez
7cdacaf493 intel/xehp: Adjust TBIMR performance chicken bits. 
This enables a couple of TBIMR performance tunables in
CHICKEN_RASTER_2 that default to disabled.  TBIMR fast clip appears to
help slightly with some geometry-bound workloads.  TBIMR open batch
allows the rasterizer to start working immediately on the first tile
of the framebuffer, even before the batch has been closed, which helps
reduce the latency cost of the tile walk.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493>
 2023-10-27 14:50:42 -07:00
Francisco Jerez
cec5541b02 intel/xehp+: Add TBIMR-related genxml definitions. 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493>
 2023-10-27 14:48:29 -07:00
Rohan Garg
26c2c96d62 anv: enable FCV for Gen12.5 
Now that we have proper handling of FCV_CCS_E everywhere, we can turn
this on for Gen12.5.

This helps fix a performance regression where enabling fast
clears to non-zero values with CCS_E caused additional partial resolves,
regressing performance on certain games. Performance is helped on the
following games:
  - F1'22: +45%
  - RDR2: +6%

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25589>
 2023-10-11 12:18:15 +00:00
Rohan Garg
300c98dbb2 intel/genxml: fix 3DSTATE_3D_MODE length to align with BSpec 
Closes: #8632
Fixes: 569afd37f1 ('intel/genxml: Copy gen12.xml to gen125.xml')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25589>
 2023-10-11 12:18:15 +00:00
Tapani Pälli
1c4d57568a intel/genxml: remove HDC from gen11.xml, it is not available 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25399>
 2023-10-02 12:05:54 +00:00
Jordan Justen
961aa68b23 intel/genxml: Build with gen20.xml 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253>
 2023-09-21 18:24:01 +00:00
Jordan Justen
6f1b1d6330 intel/genxml: Auto-import genxml files using genxml_import.py 
$ src/intel/genxml/genxml_import.py --import

This can be reversed with:

$ src/intel/genxml/genxml_import.py --flatten

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593>
 2023-09-14 11:05:16 -07:00
Jordan Justen
cd0c758f32 intel/genxml: Start Xe2 support 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593>
 2023-09-14 11:05:16 -07:00
Jordan Justen
0495f952d4 intel/genxml: Add genxml_import.py script 
This script can:
 * validate that genxml files do not duplicate imported items
 * add imports to genxml files and optimize the file by dropping
   duplicate items
 * reverse the import operation by flattening genxml files

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593>
 2023-09-14 11:05:16 -07:00
Jordan Justen
6ad2f39bab intel/genxml: Add GenXml.flatten_xml() method 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593>
 2023-09-14 11:05:16 -07:00
Jordan Justen
c0f7feb239 intel/genxml: Add GenXml.add_xml_imports method 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593>
 2023-09-14 11:05:16 -07:00
Jordan Justen
9e5190ad1f intel/genxml: Drop assertion to allow for importing 
For example, gen11.xml will import the HEVC_ARBITRATION_PRIORITY
struct from gen9.xml.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593>
 2023-09-14 11:05:16 -07:00
Jordan Justen
614aa2e62b intel/genxml: Add GenXml.optimize_xml_import() 
This function drops duplicated items from a genxml file when they are
equivalent to the same item imported from another genxml file.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593>
 2023-09-14 11:05:16 -07:00
Jordan Justen
1285337218 intel/genxml: Add all xml files as pack dependencies 
Since the output can now depend on other imported xml files, we need
to add them all as dependencies to ensure that if any xml file is
changed, then all pack files are rebuilt.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593>
 2023-09-14 11:05:16 -07:00
Jordan Justen
b076b4f99b intel/genxml: Add support for excluding items when importing 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593>
 2023-09-14 11:05:15 -07:00
Jordan Justen
6cc21dc8b5 intel/genxml: Support importing from another genxml file 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593>
 2023-09-14 11:05:15 -07:00
Rohan Garg
9eba1d9187 intel/genxml: update PIPE_CONTROL instruction for dg2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25124>
 2023-09-12 19:04:24 +00:00
Sagar Ghuge
f0d5c7848a intel/genxml: Add STATE_COMPUTE_MODE instruction 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24508>
 2023-09-08 23:08:26 +00:00
Jordan Justen
8c8fca53fd intel/genxml: Fix comparing xml when node counts differ 
This fix is more relevant to MR !20593. Normally when sorting the
number of nodes will be equivalent today, so this bug will not be
encountered. But in !20593, we can shrink (--import) or grow the
number of elements (--flatten) when the genxml_import.py tool is used.

Fixes: e60a0b1616 ("intel/genxml: Move sorting & writing into GenXml class")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24902>
 2023-09-06 07:18:47 +00:00
Jordan Justen
d8038c8d09 intel/genxml: Ignore tail leading/trailing whitespace in node_validator() 
When importing or flattening genxml with the genxml_import.py script
in MR !20593, it can lead to the tail portion of xml items differing
in whitespace.

If we strip the trailing and leading whitespace from the tail string,
and the strings are equivalent, then we can consider the xml items to
be equivalent.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24903>
 2023-09-06 06:51:48 +00:00
Lionel Landwerlin
3e9f366b70 genxml/gfx12: rename Tiled Resource Mode 
To match documentation.

BSpec 46965

TGL PRMs, Volume 2d: Command Reference: Structures, 3DSTATE_HIER_DEPTH_BUFFER_BODY

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin
cc985bb2ad genxml/gfx11: remove Tiled Resource Mode field from HIER_DEPTH_BUFFER 
This field doesn't exist according to documentation. Only a MBZ.

BSpec 6511

ICL PRMs, Volume 2a - Command Reference: Instructions (Command
Opcodes) 3DSTATE_HIER_DEPTH_BUFFER

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:16 +00:00
Jordan Justen
c1a0bdae1c intel/genxml: Update xml with gen_sort_tags.py output 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24605>
 2023-08-14 23:09:36 +00:00
Jordan Justen
549540ca7c intel/genxml: Add final newline to output when saving xml 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24605>
 2023-08-14 23:09:36 +00:00
Jordan Justen
548a0bc7d2 intel/genxml: Don't rewrite sorted xml if the contents didn't change 
Rework:
 * Make better use of pathlib. (Dylan)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24605>
 2023-08-14 23:09:36 +00:00