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intel/genxml/xe2: Update PIPELINE_SELECT

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'Media Sampler DOP Clock Gate Enable' and 'Force Media Awake' don't
exist anymore.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26403>
This commit is contained in:
José Roberto de Souza 2022-12-26 09:57:17 -08:00 • committed by Marge Bot
parent 9898c719a2
commit 6d42333b16
3 changed files with 21 additions and 5 deletions
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8
src/gallium/drivers/iris/iris_state.c
View file

@ -744,9 +744,11 @@ emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline)
iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
#if GFX_VER >= 9
sel.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
sel.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
#endif
sel.MaskBits = GFX_VER == 12 ? 0x13 : 0x3;
#if GFX_VER == 12
sel.MediaSamplerDOPClockGateEnable = true;
#endif /* if GFX_VER == 12 */
#endif /* if GFX_VER >= 9 */
sel.PipelineSelection = pipeline;
}
}

12
src/intel/genxml/gen20.xml
View file

@ -299,6 +299,18 @@
<field name="Argument Buffer Start Address" start="130" end="191" type="address" />
<field name="COMPUTE_WALKER_BODY" start="192" end="1439" type="COMPUTE_WALKER_BODY" />
</instruction>
<instruction name="PIPELINE_SELECT" bias="1" length="1" engine="render">
<field name="Pipeline Selection" start="0" end="1" type="uint">
<value name="3D" value="0" />
<value name="Media" value="1" />
<value name="GPGPU" value="2" />
</field>
<field name="Mask Bits" start="8" end="15" type="uint" />
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="4" />
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1" />
<field name="Command SubType" start="27" end="28" type="uint" default="1" />
<field name="Command Type" start="29" end="31" type="uint" default="3" />
</instruction>
<instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="4" />
<field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool" />

6
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -6749,8 +6749,10 @@ void
genX(emit_pipeline_select)(struct anv_batch *batch, uint32_t pipeline)
{
anv_batch_emit(batch, GENX(PIPELINE_SELECT), ps) {
ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
ps.MaskBits = GFX_VER == 12 ? 0x13 : 0x3;
#if GFX_VER == 12
ps.MediaSamplerDOPClockGateEnable = true;
#endif
ps.PipelineSelection = pipeline;
}
}