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anv, blorp, iris, intel/genxml: Update 3DSTATE_VS for xe2

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Update 3DSTATE_VS programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
This commit is contained in:
Jordan Justen 2022-08-03 11:18:10 -07:00 • committed by Marge Bot
parent f170995e66
commit 5548e6a478
4 changed files with 51 additions and 3 deletions
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2
src/gallium/drivers/iris/iris_state.c
View file

@ -4955,7 +4955,9 @@ iris_store_vs_state(const struct intel_device_info *devinfo,
iris_pack_command(GENX(3DSTATE_VS), shader->derived_data, vs) {
INIT_THREAD_DISPATCH_FIELDS(vs, Vertex, MESA_SHADER_VERTEX);
vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
#if GFX_VER < 20
vs.SIMD8DispatchEnable = true;
#endif
vs.UserClipDistanceCullTestEnableBitmask =
vue_prog_data->cull_distance_mask;
}

7
src/intel/blorp/blorp_genX_exec.h
View file

@ -729,9 +729,10 @@ blorp_emit_vs_config(struct blorp_batch *batch,
vs.MaximumNumberofThreads =
batch->blorp->isl_dev->info->max_vs_threads - 1;
#if GFX_VER >= 8
vs.SIMD8DispatchEnable =
vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
assert(GFX_VER < 8 ||
vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
#if GFX_VER >= 8 && GFX_VER < 20
vs.SIMD8DispatchEnable = true;
#endif
}
}

43
src/intel/genxml/gen20.xml
View file

@ -391,6 +391,49 @@
<field name="Maximum Tessellation Factor Not Odd" start="96" end="127" type="float" />
<field name="Tessellation Scale Factor" start="128" end="159" type="float" />
</instruction>
<instruction name="3DSTATE_VS" bias="2" length="9" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="7" />
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="16" />
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0" />
<field name="Command SubType" start="27" end="28" type="uint" default="3" />
<field name="Command Type" start="29" end="31" type="uint" default="3" />
<field name="Kernel Start Pointer" start="38" end="95" type="offset" />
<field name="Software Exception Enable" start="103" end="103" type="bool" />
<field name="Accesses UAV" start="108" end="108" type="bool" />
<field name="Illegal Opcode Exception Enable" start="109" end="109" type="bool" />
<field name="Floating Point Mode" start="112" end="112" type="uint">
<value name="IEEE-754" value="0" />
<value name="Alternate" value="1" />
</field>
<field name="Thread Dispatch Priority" start="113" end="113" type="uint">
<value name="Normal" value="0" />
<value name="High" value="1" />
</field>
<field name="Binding Table Entry Count" start="114" end="121" type="uint" />
<field name="Sampler Count" start="123" end="125" type="uint">
<value name="No Samplers" value="0" />
<value name="1-4 Samplers" value="1" />
<value name="5-8 Samplers" value="2" />
<value name="9-12 Samplers" value="3" />
<value name="13-16 Samplers" value="4" />
</field>
<field name="Vector Mask Enable" start="126" end="126" type="uint">
<value name="Dmask" value="0" />
</field>
<field name="Scratch Space Buffer" start="138" end="159" type="uint" />
<field name="Vertex URB Entry Read Offset" start="196" end="201" type="uint" />
<field name="Vertex URB Entry Read Length" start="203" end="208" type="uint" />
<field name="Dispatch GRF Start Register For URB Data" start="212" end="216" type="uint" />
<field name="Enable" start="224" end="224" type="bool" />
<field name="Vertex Cache Disable" start="225" end="225" type="bool" />
<field name="SIMD8 Single Instance Dispatch Enable" start="233" end="233" type="bool" />
<field name="Statistics Enable" start="234" end="234" type="bool" />
<field name="Maximum Number of Threads" start="246" end="255" type="uint" />
<field name="User Clip Distance Cull Test Enable Bitmask" start="256" end="263" type="uint" />
<field name="User Clip Distance Clip Test Enable Bitmask" start="264" end="271" type="uint" />
<field name="Vertex URB Entry Output Length" start="272" end="276" type="uint" />
<field name="Vertex URB Entry Output Read Offset" start="277" end="282" type="uint" />
</instruction>
<instruction name="3DSTATE_WM_HZ_OP" bias="2" length="6" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="4" />
<field name="Predicate Enable" start="8" end="8" type="bool" />

2
src/intel/vulkan/genX_pipeline.c
View file

@ -1183,8 +1183,10 @@ emit_3dstate_vs(struct anv_graphics_pipeline *pipeline)
vs.Enable = true;
vs.StatisticsEnable = true;
vs.KernelStartPointer = vs_bin->kernel.offset;
#if GFX_VER < 20
vs.SIMD8DispatchEnable =
vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
#endif
assert(!vs_prog_data->base.base.use_alt_mode);
#if GFX_VER < 11