Commit graph

144239 commits

Author SHA1 Message Date
Ian Romanick
47f0cdc449 intel/fs: cmod propagate from MOV with any condition
There were tests related to propagating conditional modifiers from a MOV
to an instruction with a .SAT modifier for a very long time, but they
were #if'ed out.

There are restrictions later in the function that limit the kinds of MOV
instructions that can propagate.  This avoids the dangers of
type-converting MOVs that may generate flags in different ways.

v2: Update the added comment to look more like the existing comment.
That makes the small differences between the two cases more obvious.
Noticed by Marcin.

All Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 19827127 -> 19826924 (<.01%)
instructions in affected programs: 62024 -> 61821 (-0.33%)
helped: 201
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.01 x̃: 1
helped stats (rel) min: 0.13% max: 0.60% x̄: 0.35% x̃: 0.36%
95% mean confidence interval for instructions value: -1.02 -1.00
95% mean confidence interval for instructions %-change: -0.36% -0.34%
Instructions are helped.

total cycles in shared programs: 954655879 -> 954655356 (<.01%)
cycles in affected programs: 1212877 -> 1212354 (-0.04%)
helped: 155
HURT: 6
helped stats (abs) min: 1 max: 6 x̄: 3.65 x̃: 4
helped stats (rel) min: <.01% max: 0.17% x̄: 0.07% x̃: 0.07%
HURT stats (abs)   min: 2 max: 12 x̄: 7.00 x̃: 8
HURT stats (rel)   min: 0.04% max: 0.23% x̄: 0.14% x̃: 0.15%
95% mean confidence interval for cycles value: -3.60 -2.90
95% mean confidence interval for cycles %-change: -0.07% -0.05%
Cycles are helped.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>
2021-08-30 14:00:14 -07:00
Ian Romanick
a9120eccff intel/compiler: Move type_is_unsigned_int to brw_reg_type.h
...and rename it to brw_reg_type_is_unsigned_integer.  It is now next to
brw_reg_type_is_floating_point and brw_reg_type_is_integer.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>
2021-08-30 14:00:14 -07:00
Ian Romanick
b23432c540 intel/fs: Fix a cmod prop bug when the source type of a mov doesn't match the dest type of scan_inst
We were previously operating with the mindset "a MOV is just a compare
with zero."  As a result, we were trying to share as much code between
the MOV path and the CMP path as possible.  However, MOV instructions
can perform type conversions that affect the result of the comparison.
There was some code added to better handle this for cases like

    and(16)         g31<1>UD       g20<8,8,1>UD   g22<8,8,1>UD
    mov.nz.f0(16)   null<1>F       g31<8,8,1>D

The flaw in these changed special cases is that it allowed things like

    or(8)           dest:D  src0:D  src1:D
    mov.nz(8)       null:D  dest:F

Because both destinations were integer types, the propagation was
allowed.  The source type of the MOV and the destination type of the OR
do not match, so type conversion rules have to be accounted for.

My solution was to just split the MOV and non-MOV paths with completely
separate checks.  The "else" path in this commit is basically the old
code with the BRW_OPCODE_MOV special case removed.

The new MOV code further splits into "destination of scan_inst is float"
and "destination of scan_inst is integer" paths.  For each case I
enumerate the rules that I belive apply.  For the integer path, only the
"Z or NZ" rules are listed as only NZ is currently allowed (hence the
conditional_mod assertion in that path).  A later commit relaxes this
and adds the rule.

The new rules slightly relax one of the previous rules.  Previously the
sizes of the MOV destination and the MOV source had to be the same.  In
some cases now the sizes can be different by the following conditions:

  - Floating point to integer conversion are not allowed.

  - If the conversion is integer to floating point, the size of the
    floating point value does not matter as it will not affect the
    comparison result.

  - If the conversion is float to float, the size of the destination
    must be greater than or equal to the size of the source.

  - If the conversion is integer to integer, the size of the destination
    must be greater than or equal to the size of the source.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>
2021-08-30 14:00:14 -07:00
Ian Romanick
0797388dc2 intel/fs: Add many cmod propagation tests involving MOV instructions
Of particular interest are the tests where the MOV performs a type
conversion.  If the restriction on conditional modifier for a MOV is
ever relaxed, some of these cases must still be disallowed.

v2: s/NZ/Z/ in one of the comments.  Notice by Marcin.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>
2021-08-30 14:00:14 -07:00
Ian Romanick
4f6c5da025 intel/fs: Remove redundant inst->opcode checks in cmod prop
This foreach_inst_in_block_reverse_starting_from loop only applies
CMP, MOV, and AND.  AND instructions break out of the loop before this
point.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>
2021-08-30 14:00:14 -07:00
Ian Romanick
3afefb0818 intel/fs: Refactor some cmod propagation tests
This will simplify some later changes to these tests.

v2: Combine test_positive_saturate_prop and test_negative_saturate_prop
into a single function.  Suggested by Marcin.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>
2021-08-30 14:00:14 -07:00
Mike Blumenkrantz
66fa676e8d radv: ignore dynamic line stipple if line stipple isn't enabled
==244108== Conditional jump or move depends on uninitialised value(s)
==244108==    at 0x48498D5: bcmp (vg_replace_strmem.c:1129)
==244108==    by 0x1C37B7DD: radv_bind_dynamic_state (radv_cmd_buffer.c:237)
==244108==    by 0x1C388027: radv_CmdBindPipeline (radv_cmd_buffer.c:4794)
==244108==    by 0x14E9C01E: bool update_gfx_pipeline<true>(zink_context*, zink_batch_state*, pipe_prim_type) (zink_draw.cpp:406)
==244108==    by 0x14E9AAB9: void zink_draw_vbo<(zink_multidraw)1, (zink_dynamic_state)1, (zink_dynamic_state2)1, (zink_dynamic_vertex_input)1, true>(pipe_cont>
==244108==    by 0x14B017EB: tc_call_draw_single (u_threaded_context.c:3033)
==244108==    by 0x14AF9C0E: tc_batch_execute (u_threaded_context.c:190)
==244108==    by 0x14AFA24F: _tc_sync (u_threaded_context.c:341)
==244108==    by 0x14B006E7: tc_texture_subdata (u_threaded_context.c:2549)
==244108==    by 0x14238F8C: st_TexSubImage (st_cb_texture.c:2134)
==244108==    by 0x14239931: st_TexImage (st_cb_texture.c:2363)
==244108==    by 0x1453698A: teximage (teximage.c:3154)
==244108==    by 0x1453698A: teximage_err (teximage.c:3181)
==244108==    by 0x145388BD: _mesa_TexImage2D (teximage.c:3252)
==244108==    by 0x5E88D4: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5E9527: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5E9B72: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5F1092: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5F10AC: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x48CC66: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x48DDC7: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x40D525: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x4FF7B74: (below main) (in /usr/lib64/libc-2.33.so)
==244108==  Uninitialised value was created by a stack allocation
==244108==    at 0x14ECDF55: zink_create_gfx_pipeline (zink_pipeline.c:53)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12618>
2021-08-30 19:24:29 +00:00
Mike Blumenkrantz
90a0556c27 radv: use pool stride when copying single query results
the specified stride is irrelevant for this case since there's only one
result to write

Cc: mesa-stable

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12619>
2021-08-30 19:02:40 +00:00
Samuel Pitoiset
906f7f4296 radv: advertise VK_EXT_primitive_topology_list_restart
Everything should be already supported, except patch list.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12611>
2021-08-30 18:39:20 +00:00
Samuel Pitoiset
d465095fc0 vulkan: Update the XML and headers to 1.2.190
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12611>
2021-08-30 18:39:20 +00:00
Neha Bhende
98fded8a39 svga/drm: use pb_usage_flags instead of pipe_map_flags in vmw_svga_winsys_buffer_map
This patch basically maps pipe_map_flags to pb_flags. Since we are mapping it,
STATIC_ASSERTS won't be required.

Fixes: 00c30dad78 ("gallium: renumber PIPE_MAP_* enums to remove holes")

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12606>
2021-08-30 17:32:11 +00:00
Samuel Pitoiset
2d1b85fe22 radv: add support for clearing multi layers with normal gfx clear path
Allow to clear range of layers with vkCmdClear{Color,DepthStencil}Image().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12557>
2021-08-30 16:19:29 +00:00
Rohan Garg
a6a89aaa2f ci: Fix a minor issue in prepare-artifacts.sh script
bash is whitespace sensitive.
https://github.com/koalaman/shellcheck/wiki/SC1020

This was noticed from the logs of a CI job
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/13158779
There was no fallout from this bug as not having this variable defined
leads to the right behavior, and defining it to 1 leads to a error
which consequently also leads to the right behaviour.

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12562>
2021-08-30 14:52:08 +00:00
Rhys Perry
9df9fe7dfa aco: include utility in isel
For std::exchange().

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: c1d11bb92c ("aco: Add loop creation helpers.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5301
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12614>
2021-08-30 14:28:00 +00:00
Timur Kristóf
548b383310 nir: Fix local_invocation_index upper bound for non-compute-like stages.
The lowered LS and NGG stages use local_invocation_index and they
can benefit from the unsigned upper bound because they can emit a
less expensive integer multiplication instruction.
This was working in the past, but accidentally borked by a refactor.

Fossil DB changes on Sienna Cichlid:

Totals from 956 (0.74% of 128647) affected shaders:
CodeSize: 2354172 -> 2344712 (-0.40%)
Instrs: 434359 -> 434327 (-0.01%)
Latency: 1883949 -> 1876814 (-0.38%)
InvThroughput: 762638 -> 757405 (-0.69%)

Fossil DB changes on Sienna Cichlid (with NGGC enabled):

Totals from 57873 (44.99% of 128647) affected shaders:
CodeSize: 155844192 -> 155607064 (-0.15%)
Instrs: 29799184 -> 29799152 (-0.00%)
Latency: 130959764 -> 130814224 (-0.11%); split: -0.11%, +0.00%
InvThroughput: 21100300 -> 20928635 (-0.81%); split: -0.81%, +0.00%

Fixes: 8af6766062
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12558>
2021-08-30 14:05:33 +00:00
Timur Kristóf
a25fd1787a nir: Add unsigned upper bound for extract opcodes.
This helps with some cases of extract, such as:
- Emitting more optimal integer multiplications
- Better address calculation
- Possibly others

Fossil DB results on Sienna Cichlid:

Totals from 4064 (3.16% of 128647) affected shaders:
VGPRs: 262040 -> 262032 (-0.00%)
CodeSize: 28856648 -> 28811892 (-0.16%); split: -0.18%, +0.02%
Instrs: 5370279 -> 5367827 (-0.05%); split: -0.08%, +0.04%
Latency: 74230112 -> 74016671 (-0.29%); split: -0.29%, +0.01%
InvThroughput: 12082532 -> 12036365 (-0.38%); split: -0.39%, +0.01%
VClause: 108506 -> 108721 (+0.20%); split: -0.03%, +0.22%
SClause: 217731 -> 216602 (-0.52%); split: -0.67%, +0.15%
Copies: 265689 -> 270811 (+1.93%); split: -0.26%, +2.19%
PreSGPRs: 201982 -> 204907 (+1.45%); split: -0.01%, +1.46%
PreVGPRs: 236099 -> 236079 (-0.01%)

Fossil DB results on Sienna Cichlid with NGGC enabled:

Totals from 60375 (46.93% of 128647) affected shaders:
VGPRs: 2212576 -> 2212568 (-0.00%)
CodeSize: 180870420 -> 179684816 (-0.66%); split: -0.66%, +0.00%
Instrs: 34386715 -> 34213682 (-0.50%); split: -0.51%, +0.01%
Latency: 199676290 -> 198987998 (-0.34%); split: -0.35%, +0.00%
InvThroughput: 32288299 -> 31736433 (-1.71%); split: -1.71%, +0.00%
VClause: 621521 -> 621743 (+0.04%); split: -0.00%, +0.04%
SClause: 900447 -> 899392 (-0.12%); split: -0.16%, +0.04%
Copies: 3439529 -> 3445305 (+0.17%); split: -0.02%, +0.19%
PreSGPRs: 2216297 -> 2219220 (+0.13%); split: -0.00%, +0.13%
PreVGPRs: 1842887 -> 1842867 (-0.00%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12558>
2021-08-30 14:05:33 +00:00
Timur Kristóf
76b9dd6266 aco: Unset 16 and 24-bit flags from operands in apply_extract.
Consider the following sequence in a shader:
b = p_extract a
c = v_mad_u32_u16 b, X, 0

The optimizer applies extract, resulting in:
c = v_mad_u32_u16 a, X, 0 (correct)

Then it mistakenly turns that into:
c = v_mul_u32_u24 a, X, 0 (incorrect)

In this case, the p_extract is applied to v_mad_u32_u16 by
apply_extract. After this, we can no longer be sure that
the operands are still 16 or 24-bit, so we have to remove
this flag.

No Fossil DB changes.

Fixes: 54292e99c7
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12558>
2021-08-30 14:05:33 +00:00
Mike Blumenkrantz
849033e6d8 zink: implement PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY when resizable bar not present
this helps in some cases to avoid allocating and mapping large staging resources

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12579>
2021-08-30 13:46:04 +00:00
Mike Blumenkrantz
9a8960de53 zink: determine whether the gpu has a resizable BAR at startup
this can be used to make different allocation and mapping decisions

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12579>
2021-08-30 13:46:04 +00:00
Tomeu Vizoso
1c9b0b853e panvk/ci: Build-test panvk
We still need to implement quite some functionality before it would make
sense to run dEQP in CI, but it will be already useful to build-test it.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12612>
2021-08-30 09:59:39 +02:00
Samuel Pitoiset
23ef0fb277 radv: do not allocate a clear value for images that support comp-to-single
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12565>
2021-08-30 07:18:19 +00:00
Samuel Pitoiset
df688e6941 radv: do not load/store the clear value for comp-to-single images
Images that are fast cleared with the comp-to-single mode clears DCC
to 0x10 which tells the hardware to get the clear value from the
main surface instead of the reg.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12565>
2021-08-30 07:18:19 +00:00
Samuel Pitoiset
0c550a5fe6 radv: disable DCC image stores on Navi12-14 for displayable DCC corruption
DCC image stores require 128B but 64B is used for displayable DCC.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5265
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5106
Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12521>
2021-08-30 08:28:37 +02:00
Dave Airlie
a069b4e9b9 vulkan/wsi/sw: add mit-shm support for pixmap allocation
This allocate the mit-shm pixmap instead of dri3 pixmaps and
uses the present paths when mit-shm is enabled

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12482>
2021-08-29 20:26:13 +00:00
Dave Airlie
1f55f9a97a vulkan/wsi/sw: add support for using host_ptr for shm pixmaps.
This pipes the allocation of the MIT-SHM pixmap into the wsi common
code to callback to the x11 path to allocate things in the right place.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12482>
2021-08-29 20:26:13 +00:00
Dave Airlie
b5c390c113 vulkan/wsi: add support for detecting mit-shm pixmaps.
This just adds the xcb bits to detect is the host supports shared
shm pixmaps or whether the old paths should be used.

shm pixmaps will only be used if dri3 is available

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12482>
2021-08-29 20:26:13 +00:00
Rob Clark
eacf50c27b freedreno/ci: Take fd farm offline for moving day
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12602>
2021-08-28 13:08:05 +00:00
Rob Clark
8f784c8fed freedreno/ci: Add a status variable for CI farm
Make it a one-line change to disable freedreno CI jobs if the farm is
offline.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12602>
2021-08-28 13:08:05 +00:00
Caio Marcelo de Oliveira Filho
b34f9740ca spirv: Implement non-Multiview parts of SPV_NV_mesh_shader
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10600>
2021-08-28 03:56:43 +00:00
Caio Marcelo de Oliveira Filho
10a03e30cf nir: Allow Task/Mesh to lower compute system values
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10600>
2021-08-28 03:56:43 +00:00
Caio Marcelo de Oliveira Filho
4f52681a2d nir: Don't lower Task/Mesh I/O to temporaries
These won't work since a workgroup can span more than one thread, and
the temporaries are not shared memory.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10600>
2021-08-28 03:56:43 +00:00
Caio Marcelo de Oliveira Filho
27697d5eb8 nir/divergence_analysis: Handle Task/Mesh shaders
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10600>
2021-08-28 03:56:42 +00:00
Caio Marcelo de Oliveira Filho
bf5f6add01 nir/lower_io: Identify Mesh output as arrayed
Mesh shader outputs are either:

- non-array builtins
- array builtins that are either per-primitive or per-vertex
- user-defined outputs that must be either per-primitive or per-vertex

So we can identify any array output as "arrayed" for the purposes of
I/O lowering.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10600>
2021-08-28 03:56:42 +00:00
Caio Marcelo de Oliveira Filho
9631d24c3f compiler: Add Task/Mesh to shader_info
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10600>
2021-08-28 03:56:42 +00:00
Caio Marcelo de Oliveira Filho
813d41829d compiler: Add new non-Multiview Task/Mesh builtins
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10600>
2021-08-28 03:56:42 +00:00
Caio Marcelo de Oliveira Filho
cd394017c8 nir: Add per-primitive I/O intrinsics
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10600>
2021-08-28 03:56:42 +00:00
Caio Marcelo de Oliveira Filho
f95daad3a2 nir: Add a way to identify per-primitive variables
Per-primitive is similar to per-vertex attributes, but applies to all
fragments of the primitive without any interpolation involved.

Because they are regular input and outputs, keep track in shader_info
of which I/O is per-primitive so we can distinguish them after deref
lowering.  These fields can be used combined with the regular
`inputs_read`, `outputs_written` and `outputs_read`.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10600>
2021-08-28 03:56:42 +00:00
Caio Marcelo de Oliveira Filho
927584fa67 nir: Update documentation for location to mention Task/Mesh
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10600>
2021-08-28 03:56:42 +00:00
Jason Ekstrand
3c3b75a2b7 isl/docs/tiling: Add Tile4 docs
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12550>
2021-08-28 02:49:18 +00:00
Timur Kristóf
cfb0d931f2 aco: Emit zero for the derivatives of uniforms.
Observed in a shader from Resident Evil Village.
This also helps prevent emitting invalid IR.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12599>
2021-08-27 20:34:22 +00:00
Mike Blumenkrantz
1454955e5d zink: only update inlinable constants when they change
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12577>
2021-08-27 20:16:49 +00:00
Daniel Schürmann
2eeaaabb8e aco/optimizer: combine v_pk_mul_u16 + v_pk_add_u16 -> v_pk_mad_u16
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11678>
2021-08-27 19:57:59 +00:00
Daniel Schürmann
be16ebc5ca aco/optimizer: fuse v_mul_f64 + v_add_f64 -> v_fma_f64
No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11678>
2021-08-27 19:57:59 +00:00
Daniel Schürmann
8e27ca9953 aco/optimizer: combine v_mul_lo_u16 + v_add_u16 -> v_mad_u16
Totals from 192 (0.13% of 150170) affected shaders: (GFX10.3)
CodeSize: 1027224 -> 1019872 (-0.72%)
Instrs: 174784 -> 173863 (-0.53%)
Latency: 4235742 -> 4232177 (-0.08%); split: -0.11%, +0.03%
InvThroughput: 1777026 -> 1775945 (-0.06%); split: -0.09%, +0.03%
Copies: 34098 -> 34099 (+0.00%); split: -0.03%, +0.03%
PreVGPRs: 4920 -> 4850 (-1.42%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11678>
2021-08-27 19:57:59 +00:00
Daniel Schürmann
23d5865f42 aco: refactor nir_op_imul selection
Previously, the optimization to use v_mul_lo_u16 for
32bit multiplications was done in instruction_selection.
This was moved to the optimizer to ease some case distinctions.

The mixed results are due to increased use of SDWA.

Totals from 2616 (1.74% of 150170) affected shaders: (GFX10.3)
VGPRs: 143888 -> 143872 (-0.01%); split: -0.02%, +0.01%
CodeSize: 5604032 -> 5604080 (+0.00%); split: -0.01%, +0.01%
Instrs: 1086798 -> 1083915 (-0.27%); split: -0.27%, +0.01%
Latency: 8215793 -> 8213023 (-0.03%); split: -0.10%, +0.07%
InvThroughput: 20765157 -> 20773766 (+0.04%); split: -0.02%, +0.06%
VClause: 35256 -> 35260 (+0.01%); split: -0.02%, +0.03%
SClause: 29021 -> 29024 (+0.01%); split: -0.00%, +0.01%
Copies: 74163 -> 74306 (+0.19%); split: -0.05%, +0.24%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11678>
2021-08-27 19:57:59 +00:00
Daniel Schürmann
d8eef134d8 aco: only apply extract if not used more than 4 times
Totals from 61 (0.04% of 150170) affected shaders: (GFX10.3)
CodeSize: 1087732 -> 1087380 (-0.03%); split: -0.22%, +0.18%
Instrs: 192343 -> 192205 (-0.07%); split: -0.16%, +0.09%
Latency: 7231670 -> 7148073 (-1.16%); split: -1.19%, +0.04%
InvThroughput: 3436715 -> 3394926 (-1.22%); split: -1.25%, +0.04%
VClause: 4831 -> 4833 (+0.04%)
Copies: 50130 -> 49934 (-0.39%); split: -0.67%, +0.28%
Branches: 5945 -> 5948 (+0.05%)
PreSGPRs: 3486 -> 3472 (-0.40%)
PreVGPRs: 5154 -> 5152 (-0.04%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11678>
2021-08-27 19:57:59 +00:00
Mike Blumenkrantz
b8c26e89fe freedreno: ci updates
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12600>
2021-08-27 19:38:19 +00:00
Mike Blumenkrantz
9c6938dbfd freedreno: remove primconvert
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12600>
2021-08-27 19:38:19 +00:00
Mike Blumenkrantz
744ef862b8 freedreno: export supported primtypes
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12600>
2021-08-27 19:38:19 +00:00
Jeremy Newton
80b5f4ff08 Fix building AMD MM/GL with EL7
This partially reverts commit 4d9acfa533.

The original patch said:

"Python 3 handles unicode strings by default, so we can drop all that."

But this breaks building on RHEL 7 (or similiar) since python3 support
on is much more limited than newer distros. Backporting all the needed
python 3 libraries to EL7 is a pretty big task, and isn't very easy to
maintain.

For workstation purposes, we need the AMD MM/GL driver building on RHEL
7, so only src/util/driconf_static.py needs to be reverted.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Jeremy Newton <Jeremy.Newton@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12549>
2021-08-27 19:05:25 +00:00