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aco/optimizer: combine v_mul_lo_u16 + v_add_u16 -> v_mad_u16

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Totals from 192 (0.13% of 150170) affected shaders: (GFX10.3)
CodeSize: 1027224 -> 1019872 (-0.72%)
Instrs: 174784 -> 173863 (-0.53%)
Latency: 4235742 -> 4232177 (-0.08%); split: -0.11%, +0.03%
InvThroughput: 1777026 -> 1775945 (-0.06%); split: -0.09%, +0.03%
Copies: 34098 -> 34099 (+0.00%); split: -0.03%, +0.03%
PreVGPRs: 4920 -> 4850 (-1.42%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11678>
This commit is contained in:
Daniel Schürmann 2021-07-01 18:48:09 +02:00 • committed by Marge Bot
parent 23d5865f42
commit 8e27ca9953
1 changed files with 9 additions and 5 deletions
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14
src/amd/compiler/aco_optimizer.cpp
View file

@ -1477,11 +1477,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr)
break;
}
case aco_opcode::v_mul_lo_u16:
if (instr->definitions[0].isNUW()) {
/* Most of 16-bit mul optimizations are only valid if no overflow. */
ctx.info[instr->definitions[0].tempId()].set_usedef(instr.get());
}
break;
case aco_opcode::v_mul_lo_u16_e64:
case aco_opcode::v_mul_u32_u24:
ctx.info[instr->definitions[0].tempId()].set_usedef(instr.get());
break;
@ -3381,6 +3377,14 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr)
} else if (combine_three_valu_op(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::v_xor3_b32,
"012", 1 | 2)) {
}
} else if (instr->opcode == aco_opcode::v_add_u16) {
combine_three_valu_op(
ctx, instr, aco_opcode::v_mul_lo_u16,
ctx.program->chip_class == GFX8 ? aco_opcode::v_mad_legacy_u16 : aco_opcode::v_mad_u16,
"120", 1 | 2);
} else if (instr->opcode == aco_opcode::v_add_u16_e64) {
combine_three_valu_op(ctx, instr, aco_opcode::v_mul_lo_u16_e64, aco_opcode::v_mad_u16, "120",
1 | 2);
} else if (instr->opcode == aco_opcode::v_add_u32) {
if (combine_add_sub_b2i(ctx, instr, aco_opcode::v_addc_co_u32, 1 | 2)) {
} else if (combine_add_bcnt(ctx, instr)) {