Commit graph

219335 commits

Author SHA1 Message Date
Christian Gmeiner
87fca4f51e etnaviv: Limit max line width to 1.0 on GPUs needing wide line emulation
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The HW line rasterizer on some Vivante GPUs doesn't produce
spec-conformant results for wide lines. Correct emulation via
triangle expansion is complex and interacts poorly with features
like primitive IDs, shader side effects (SSBOs, atomics), and
varying interpolation.

Rather than carrying fragile emulation, limit the advertised
max line width to 1.0 on affected GPUs. The GLES3 spec only
requires support for width 1.0, so this doesn't affect conformance.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Daniel Lang <dalang@gmx.at>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40006>
2026-03-01 11:34:56 +00:00
Christian Gmeiner
28ae3c0bf0 etnaviv: hwdb: Add WIDELINE_TRIANGLE_EMU cap
Used to tell if the GPU core needs wide line emulation.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Daniel Lang <dalang@gmx.at>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40006>
2026-03-01 11:34:56 +00:00
Dmitry Baryshkov
28f0157250 freedreno/ci: update nightly expectations
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Document nightly changes occuring in 6ea4fe98..c69f7904:
- KHR-GLES2.shaders.aggressive_optimizations.sin_vec3_frag,
  crash, run out of the register space
- dEQP-GLES2.functional.shaders.indexing.matrix_subscript.mat4_static_loop_write_dynamic_loop_read_fragment,
  passes now
- dEQP-GLES2.functional.color_clear.single_rgba,
  new flake

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40142>
2026-03-01 05:11:28 +00:00
Timothy Arceri
6c60f423b3 st/glsl_to_nir: update state var locations earlier
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We need to update the state var locations before the
st_serialize_base_nir() calls otherwise
_mesa_optimize_state_parameters() can alter params such that
variants wont be able to find the correct match when calling
_mesa_lookup_state_param_idx().

Prior to 891d46f5 this worked because after failing to match
we would end up adding additional params back in that we had
just attempted to optimise.

Fixes: a6fcc2835e ("
st/glsl_to_nir: make sure the variant has the correct locations set")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14837

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40133>
2026-02-28 23:56:10 +00:00
Luigi Santivetti
df6d398d45 pco: fix Mesa-CI regression in pco texture packed formats
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Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Fixes: 9caa563bc9 ("pvr, pco: Commonize texture packing code")
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40156>
2026-02-28 20:25:53 +00:00
Alyssa Rosenzweig
e88346330e nir/lower_io: remove incorrect Intel _block cases
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These should be handled like their non-_block counterparts - there is no i/o
index for them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40096>
2026-02-28 16:32:14 +00:00
Marek Olšák
c20245832d amd: add gfx11 and gfx12 CP packet definitions
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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40084>
2026-02-28 05:23:59 +00:00
Marek Olšák
f22f117d1a amd: add meson variable idep_amd_generated_headers for all generated headers
group all generated header under the same variable

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40084>
2026-02-28 05:23:59 +00:00
Michael Cheng
6e92be2747 anv: Rename instruction_state_pool to shader_heap
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Shaders are allocated from anv_shader_heap, which is backed by the
util_vma_heap. Rename the VA range field to shader_heap to match current
usage and avoid confusion.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40131>
2026-02-27 17:36:41 +00:00
Yiwei Zhang
69734bb903 pan/fb: fix return type for mali_to_glsl_dim
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Fixes: e3dc3dccd6 ("pan/fb: Add a common FB load shader builder")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40110>
2026-02-27 16:50:00 +00:00
Matt Coster
4d42e934ad ci,cirnm: Fix program name in usage example
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Instead of updating the name manually, use the %(prog)s specifier (as
documented at https://docs.python.org/3/library/argparse.html#prog).

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39853>
2026-02-27 15:56:14 +00:00
Mike Blumenkrantz
b8ee6f3d30 radv: fix multiview fast clears
this was only clearing layer0 because it was ignoring the viewmask

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40123>
2026-02-27 15:07:01 +00:00
Samuel Pitoiset
5fa94dba34 radv: only enable DCC/HTILE if it's compressed with SDMA
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It's wrong to enable compression if it's not compressed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40101>
2026-02-27 11:23:48 +00:00
Samuel Pitoiset
3869a6f967 ac/cmdbuf: only set DCC_WRITE_COMPRESS for DCC on SDMA 5+
Compressed HTILE writes aren't supported at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40101>
2026-02-27 11:23:48 +00:00
Benjamin Cheng
2b2b1d405a radeonsi/vcn: Use full pitch for pre-encode input
In 1f83e73145, the pre-encode input picture size was also reduced.
However it was recently discovered that VCN FW uses the input picture
pitch as the pitch for this, which means that previous change broke
pre-encode.

Fixes: 1f83e73145 ("radeonsi/vcn: Reduce allocated size for pre-encode recon pics")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40125>
2026-02-27 10:27:27 +00:00
Icenowy Zheng
5a497316d4 pvr: only specially handle gfx subcmd for BeginQuery
Among all subcommands, only gfx subcommands are bound to a query pool,
other subcommands seem to need no special handling.

In addition, if a ResetQuery is done before BeginQuery, the last
subcommand will be a event one, which fails the current assert that
assumes it's a gfx one.

Change the assertion of the subcommand being a gfx one to an addition
check of whether the subcommand is a gfx one.

This fixes crash of Vulkan CTS 1.4.5.1 test
dEQP-VK.query_pool.discard.normal.no_depth.none.discard .

Backport-to: 26.0
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39753>
2026-02-27 17:29:47 +08:00
Radu Costas
9caa563bc9 pvr, pco: Commonize texture packing code
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Format extraction moved to separate function
Removed some magic numbers

Signed-off-by: Radu Costas <radu.costas@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40067>
2026-02-27 09:08:29 +00:00
Samuel Pitoiset
d583339e79 radv/meta: add a single function for color/depth&stencil fragment resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:39 +00:00
Samuel Pitoiset
8d0206c95f radv/meta: simplify creating pipelines for color/depth&stencil fragment resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:39 +00:00
Samuel Pitoiset
009cf9bfa7 radv/meta: pass a resolve mode for fragment color resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:38 +00:00
Samuel Pitoiset
2c5685ed89 radv/meta: inline one function in the fragment resolve path
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:38 +00:00
Samuel Pitoiset
876b204703 radv/meta: use the same shader for color/depth&stencil fragment resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:37 +00:00
Samuel Pitoiset
fd9cbff41a radv/meta: move the barrier for color fragment resolves outside
This barrier is only needed for rendering resolves (ie. not for
vkCmdResolveImage()). Though, these barriers are likely unnecessary
but let's keep them for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:37 +00:00
Samuel Pitoiset
255439fd9c radv/meta: fix the shader stage for push constants in the fragment resolve path
RADV doesn't use it but better to set it correctly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:37 +00:00
Samuel Pitoiset
ed546ce809 radv/meta: add a single function for color/depth&stencil compute resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:36 +00:00
Samuel Pitoiset
94234f35fd radv/meta: simplify creating pipelines for color/depth&stencil compute resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:36 +00:00
Samuel Pitoiset
1c7b416daa radv/meta: pass a resolve mode for compute color resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:36 +00:00
Samuel Pitoiset
2ae32d709c radv/meta: inline one function in the compute resolve path
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:35 +00:00
Samuel Pitoiset
e3e52c348c radv/meta: use the same shader for color/depth&stencil compute resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:35 +00:00
Samuel Pitoiset
08f147d92c radv/meta: add depth/stencil support to the core resolve shader
This removes lot of duplicated code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:34 +00:00
Samuel Pitoiset
1e561eb1d7 radv/meta: replace radv_meta_resolve_type by VkImageAspectFlags
It's either depth or stencil.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:34 +00:00
Aditya Swarup
8a6c09e1f1 anv: Report bind events for image private binding
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Binding report test cases are failing for Gen12.5 platforms due to
missing binding events from private bindings for images creating
inconsistencies in the number of unbind events reported from
anv_DestroyImage(). Adding bind events from alloc_private_binding() to
fix the issue.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:43 +00:00
Aditya Swarup
d6eb6c58c7 anv: Enable support for VK_EXT_device_address_binding_report
Enable support for address binding report extension for anv.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:43 +00:00
Aditya Swarup
d06da76459 anv: Report addr bind events for opaque/non-opaque sparse allocations
Report vk_address_binding_report bind/unbind events for every
opaque/non-opaque sparse allocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:43 +00:00
Aditya Swarup
849b2d1c5d anv: Report bind/unbind events for sparse VA range
Report vk_address_binding_report bind/unbind events for sparse VA range
allocation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:43 +00:00
Aditya Swarup
83121a1ec2 anv: Report address binding events for VkCommandPool
Report bind/unbind events for address binding report extension
during VkCommandPool creation/destruction.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:43 +00:00
Aditya Swarup
1bb79e7e69 anv: Report address binding events for VkDescriptorPool
Report bind/unbind events for address binding report extension
during VkDescriptorPool creation/destruction.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:43 +00:00
Aditya Swarup
f0d46cc91d anv: Report address binding events for VkQueryPool
Report bind/unbind events for address binding report extension
during VkQueryPool creation/destruction.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:43 +00:00
Aditya Swarup
145eb76cb4 anv: Add BO helper macros for binding report extension
Macros that help extract anv address from BO info to use with
vk_address_binding_report().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:43 +00:00
Aditya Swarup
b769311305 anv: Report address binding events for images
Report bind/unbind events for address binding report extension
during image creation/destruction.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:43 +00:00
Aditya Swarup
1fd887a8bc anv: Report address binding events for memory buffers
Report bind/unbind events with address binding report extension
for memory buffers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:43 +00:00
Aditya Swarup
fe46a2ae9b anv: Add helper macros for address binding report extension
These macros provide support for reporting device address binding
info for VK_EXT_device_address_binding_report.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37422>
2026-02-27 01:36:42 +00:00
Rob Clark
2253afbc94 ir3: Lower 8b usub_sat
This shows up in CL CTS.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40130>
2026-02-27 01:08:12 +00:00
Valentine Burley
89c6db217c turnip/ci: Remove a618-vk-full job
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The pre-merge job now runs with fraction=1, and we can move the extra
test sets there.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39920>
2026-02-26 20:55:43 +00:00
Valentine Burley
7afd3b61ef turnip/ci: Skip more slow tests
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39920>
2026-02-26 20:55:43 +00:00
Valentine Burley
aa682376dd turnip/ci: Promote a618-vk-asan to pre-merge
Thanks to the new sc7180 runner, a few pre-merge slots are now free on
kingoftown.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39920>
2026-02-26 20:55:43 +00:00
Valentine Burley
8573a27447 turnip/ci: Move a618-vk job to new sc7180 runner
Add a new sc7180-trogdor-wormdingler-rev1-boe device type and move the
a618-vk job to it.

We'll have 12 boards, so we can increase parallelism and run fraction=1.
Update job settings and add one new expected fail, and skip a few
redundant tests in force-gmem mode.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39920>
2026-02-26 20:55:43 +00:00
Valentine Burley
32925aa188 ci: Update kernel to pull in new build for freedreno
The new kernel comes with CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 enabled which
is needed for the new sc7180-trogdor-wormdingler-rev1-boe device.

It also includes three small msm fixes and adds host support for running
VMs on arm64 for upcoming CI jobs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39920>
2026-02-26 20:55:43 +00:00
Connor Abbott
ae8928b638 ir3: Fix constlen trimming when more than one stage is trimmed
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The logic is supposed to find the stage with the maximum constlen to
trim for each time we have to trim a stage. But by not resetting
max_constlen each time, we would "trim" the same stage repeatedly,
leaving us thinking the total is below the limit when it actually isn't.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40127>
2026-02-26 20:20:04 +00:00
Connor Abbott
68c0031f56 tu: Use HW offset 0 in 3d loads/clears with FDM
The HW uses ViewportIndex to select which GRAS_BIN_FOVEAT offset to use.
For normal 3d draws, either the ViewportIndex equals the view/layer or
we make the offset the same for all viewports/layers, but we aren't
aware of this in the 3d path and we always use viewport 0.

Use the HW offset 0 when subtracting the HW offset. This is a bit of a
hack, but it should work. This fixes LOAD_OP_LOAD with FDM.

Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39976>
2026-02-26 19:53:31 +00:00