Commit graph

3030 commits

Author SHA1 Message Date
Bas Nieuwenhuizen
a4c4efad89 radv: Rework guard band calculation.
We want the guardband_x/y to be the largerst scalars such that each
viewport scaled by that amount is still a subrange of [-32767, 32767].

The old code has a couple of issues:
1) It used scissor instead of viewport_scissor, potentially taking into
   account a viewport that is too small and therefore selecting a scale
   that is too large.
2) Merging the viewports isn't ideal, as for example viewports with
   boundaries [0,1] and [1000, 1001] would allow a guardband scale of ~30k,
   while their union [0, 1001] only allows a scale of ~32.

The new code just determines the guardband per viewport and takes the minimum.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2017-04-03 23:03:46 +02:00
Bas Nieuwenhuizen
d64f689f61 radv: Enable VK_KHR_incremental_present.
Just enabling the driver-independent implementation that Jason did.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-03 23:00:07 +02:00
Jason Ekstrand
f82b6c6272 vulkan/wsi: Plumb present regions through the common code
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2017-04-03 13:51:08 -07:00
Dave Airlie
1171b304f3 radv: overhaul fragment shader sample positions.
The current code was broken, and I decided to redesign it instead.

This puts the sample positions for all samples into the queue
constant descriptor buffer after all the spill/ring descriptors.

It then uses a single offset register to point how far into the
samples the samples for num_samples are. This saves one user sgpr
and means we only generate the sample position data in the rare
single case where we need it currently.

This doesn't fix the failing CTS tests without the followup
fix.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-04 05:55:15 +10:00
Dave Airlie
03a67fbbf7 radv: fix order of the guardband register emission.
y is vert, x is horiz.

Noticed in visual inspection compared to radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-02 20:17:30 +10:00
Dave Airlie
c011fe7452 radv: enable tessellation shaders.
This enables tessellation shaders and sets some values for
the maximums.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:17:25 +10:00
Dave Airlie
3f0d69af20 radv: add ia_multi_vgt_param tessellation support.
This just ports the relevant radeonsi pieces.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:17:08 +10:00
Dave Airlie
b4495b71c6 radv/cmd: emit tessellation state.
This emits the tessellation shaders and state to the command stream.

It contains the logic to emit the LS/HS shaders.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:57 +10:00
Dave Airlie
60fc0544e0 radv/pipeline: handle tessellation shader compilation
So tess shaders have some circular dependencies,

TCS needs the TES primitive mode
TES needs the TCS vertices out

This builds the nir for each shader first to get the
info, executes a tes specific nir pass, then builds
the LLVM shaders.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:51 +10:00
Dave Airlie
4c60c68bd1 radv/pipeline: start calculating tess stage.
This calculates the pipeline state for tessellation.

It moves the gs ring calculation down to below
where the tessellation shaders will be compiled,
as it needs the info from those shaders.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:19 +10:00
Dave Airlie
823b55a8a9 radv: add tessellation support to variant code.
This just fills out the rsrc registers for tess shaders.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:14 +10:00
Dave Airlie
f239f59778 radv: add tessellation support to shader naming
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:08 +10:00
Dave Airlie
aeb49bc2b9 radv: port polaris vgt vertex reuse workaround.
This ports the VGT_VERTEX_REUSE register settings
for Polaris GPUs from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:51 +10:00
Dave Airlie
46a820b383 radv: configure tessellation distribution register.
This just takes the radeonsi values.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:45 +10:00
Dave Airlie
46e52df34d radv: add tessellation ring allocation support. (v2)
This patch adds support for the offchip rings for storing
tessellation factors and attribute data.

It includes the register setup for the TF ring

v2: always do tess ring size calcs (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:30 +10:00
Dave Airlie
bbfb62df16 radv: add support for some device specific tess information.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:26 +10:00
Dave Airlie
a4b039db04 radv: add tess shader stage user data support.
This just adds support for tess to the shader stage conversion
and emits the per-stage descriptors/constants for tess stages.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:15 +10:00
Dave Airlie
0604284e3f radv: add helper function to denote if tess is enabled on a pipeline.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:14:59 +10:00
Bas Nieuwenhuizen
0f3de89a56 radv: Use the guard band.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-03-30 22:21:14 +02:00
Bas Nieuwenhuizen
8a53e6e4c5 radv: Prepare for not using the guard band for lines & points.
Vulkan Clipping is defined in terms of vertices, the scissor based
clipping happens on pixels. There is a difference with points and
lines, as a vertex can be outside the viewport while some pixels are in.
On Vulkan thoise pixels shouldn't be drawn, while they would be with
the guardband.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-03-30 22:21:14 +02:00
Bas Nieuwenhuizen
76603aa90b radv: Drop the default viewport when 0 viewports are given.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-03-30 22:21:14 +02:00
Bas Nieuwenhuizen
4083a2ddcb radv: Set proper viewport & scissor for meta draws.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-03-30 22:21:14 +02:00
Marek Olšák
5691e14735 amd: GFX9 packet changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Marek Olšák
00e777b61c amd: add texture format definitions for GFX9
the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums
differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show
enums for both.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Marek Olšák
e6c520362d amd: resolve remaining definition conflicts with gfx9d.h
Add _GFX6 and _GFX9 suffixes to conflicting definitions.

sid.h and gfx9d.h can now be included in the same file.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Xavi Zhang
3614999878 amdgpu/addrlib: Rewrite tile mode optmization code
Note: remove reference to degrade4Space and use opt4Space instead.
2017-03-30 14:44:33 +02:00
Dave Airlie
2b35b60df1 radv: move to using nir clip/cull merge pass.
Doing this before tessellation makes doing some bits of
tessellation a bit cleaner. It also cleans up a bit of the
llvm generator code.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-30 11:04:56 +10:00
Bas Nieuwenhuizen
3df410069a radv: Enable sparseBinding feature.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-03-29 08:50:55 +02:00
Bas Nieuwenhuizen
b20af5c8d7 radv/amdgpu: Use reference counting for bos.
Per the Vulkan spec, memory objects may be deleted before the buffers
and images using them are deleted, although those resources then
cannot be used except for deletion themselves.

For the virtual buffers, we need to access them on resource destruction
to unmap the regions, so this results in a use-after-free. Implement
reference counting to avoid this.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-03-29 08:50:48 +02:00
Bas Nieuwenhuizen
e527e62e75 radv: Implement sparse memory binding.
v2: Only submit when semaphores are specified.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-03-29 08:50:41 +02:00
Bas Nieuwenhuizen
6154efc193 radv: Implement sparse image creation.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-03-29 08:50:37 +02:00
Bas Nieuwenhuizen
ef0e505d02 radv: Implement sparse buffer creation.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-03-29 08:50:33 +02:00
Bas Nieuwenhuizen
715df30a4e radv/amdgpu: Add winsys implementation of virtual buffers.
v2: - Added comments.
    - Fixed a double unmap bug.
    - Actually unmap the non-edge old ranges.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-03-29 08:50:17 +02:00
Bas Nieuwenhuizen
78ee8b3f84 radv: Assert when setting 0 registers in a sequence.
To catch more of those hangs early.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2017-03-29 01:58:16 +02:00
Dave Airlie
93d61e4945 radv: only emit ps_input_cntl is we have any to output
Otherwise we get GPU hangs.

Reported-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 20:12:10 +01:00
Dave Airlie
239a9224a3 radv: move shader stages calculation to pipeline.
With tess this becomes a bit more complex. so move to pipeline
for now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 17:40:33 +10:00
Dave Airlie
0232ea8025 radv: move pa_cl_vs_out_cntl calculation to pipeline
This also takes the side band setting code from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 17:40:29 +10:00
Dave Airlie
92e9c14a6a radv: move calculating fragment shader i/os to pipeline.
There is no need to calculate this on each command submit.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 17:40:20 +10:00
Dave Airlie
4b467c759e radv: move shader_z_format calculation to pipeline.
No need to recalculate this every time.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 17:40:17 +10:00
Dave Airlie
8996fdbf61 radv: move db_shader_control calculation to pipeline.
There is no need to recalculate this every time.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 17:40:14 +10:00
Dave Airlie
cd33a5c1cb radv: move vgt_gs_mode value to pipeline.
No need to recalculate this everytime.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 17:40:08 +10:00
Dave Airlie
931a8d0c9a radv: rework vertex/export shader output handling
In order to faciliate adding tess support, split the vs/es
output info into a separate block, so we make it easier to
have the tess shaders export the same info.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 17:39:59 +10:00
Dave Airlie
ae0551b4b3 radv: fix ia_multi_vgt_param for instanced vs indirect draw.
The logic was different than radeonsi, fix it up before adding
tess support.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 17:39:55 +10:00
Dave Airlie
a8b8e542c2 radv: handle NULL multisample state.
If rasterization is disabled, we can get a NULL multisample
state.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 17:39:38 +10:00
Bas Nieuwenhuizen
a8c51b1cd9 radv: flush DB cache before and after HTILE decompress.
It reads @ writes the DB cache, and we haven't flushed dst caches yet,
so DB cache may be stale. Also the user might be shader read (and probably is),
so also flush after.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
CC: <mesa-stable@lists.freedesktop.org>
Fixes: f4e499ec79 ("radv: add initial non-conformant radv vulkan driver")
2017-03-28 02:51:40 +02:00
Dave Airlie
b640dfcd05 radv: don't emit no color formats. (v3)
If we had no rasterization, we'd emit SPI color
format as all 0's the hw dislikes this, add the workaround
from radeonsi.

Found while debugging tessellation

v2: handle at pipeline stage, we have to handle
it after we process the fragment shader. (Bas)
v3: simplify even further, remove old fallback.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-28 08:39:14 +10:00
Alex Smith
bc5d587a80 radv: Invalidate L2 for TRANSFER_WRITE barriers
CP DMA and PKT3_WRITE_DATA (in CmdUpdateBuffer) don't (currently) write
through L2. Therefore, to make these writes visible to later accesses
we must invalidate L2 rather than just writing it back, to avoid the
possibility that stale data is read through L2.

Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-23 09:20:31 +10:00
Emil Velikov
b9d035e75b radv: consistently use ifndef guards over pragma once
Namely: annotate the single file which is not using a ifndef guard -
vk_format.h

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Vedran Miletić <vedran@miletic.net>
Acked-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-03-22 16:55:21 +00:00
Dave Airlie
021c87fa24 radv: move KHR_get_physical_device_properties2 to instance props.
This is an instance property not a device one.

Fixes:
dEQP-VK.api.info.device.extensions

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-21 10:05:49 +10:00
Dave Airlie
93e62898cc radv: drop illegal DB format error.
We'll get this if we have a stencil only setup.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-21 10:05:49 +10:00