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radv: Assert when setting 0 registers in a sequence.

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To catch more of those hangs early.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Acked-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Bas Nieuwenhuizen 2017-03-28 22:29:16 +02:00
parent f3673db3d6
commit 78ee8b3f84
1 changed files with 4 additions and 0 deletions
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4
src/amd/vulkan/radv_cs.h
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@ -43,6 +43,7 @@ static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsign
{
assert(reg < R600_CONTEXT_REG_OFFSET);
assert(cs->cdw + 2 + num <= cs->max_dw);
assert(num);
radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
}
@ -57,6 +58,7 @@ static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsig
{
assert(reg >= R600_CONTEXT_REG_OFFSET);
assert(cs->cdw + 2 + num <= cs->max_dw);
assert(num);
radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
}
@ -83,6 +85,7 @@ static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned r
{
assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
assert(cs->cdw + 2 + num <= cs->max_dw);
assert(num);
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
}
@ -97,6 +100,7 @@ static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsig
{
assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
assert(cs->cdw + 2 + num <= cs->max_dw);
assert(num);
radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
}