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amd: GFX9 packet changes

Browse source 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-15 13:38:45 +02:00
parent ecbdfbeb05
commit 5691e14735
4 changed files with 26 additions and 13 deletions
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1
src/amd/common/r600d_common.h
View file

@ -63,6 +63,7 @@
* 3 - send 64bit GPU counter value
* 4 - send 64bit sys counter value
*/
#define PKT3_RELEASE_MEM 0x49 /* GFX9+ */
#define PKT3_SET_CONFIG_REG 0x68
#define PKT3_SET_CONTEXT_REG 0x69
#define PKT3_STRMOUT_BASE_UPDATE 0x72 /* r700 only */

30
src/amd/common/sid.h
View file

@ -50,7 +50,16 @@
* 4 - *S_PARTIAL_FLUSH
* 5 - TS events
*/
#define EVENT_WRITE_INV_L2 0x100000
/* EVENT_WRITE_EOP (SI-VI) & RELEASE_MEM (GFX9) */
#define EVENT_TCL1_VOL_ACTION_ENA (1 << 12)
#define EVENT_TC_VOL_ACTION_ENA (1 << 13)
#define EVENT_TC_WB_ACTION_ENA (1 << 15)
#define EVENT_TCL1_ACTION_ENA (1 << 16)
#define EVENT_TC_ACTION_ENA (1 << 17)
#define EVENT_TC_NC_ACTION_ENA (1 << 19) /* GFX9+ */
#define EVENT_TC_WC_ACTION_ENA (1 << 20) /* GFX9+ */
#define EVENT_TC_MD_ACTION_ENA (1 << 21) /* GFX9+ */
#define PREDICATION_OP_CLEAR 0x0
@ -92,7 +101,7 @@
#define CONTEXT_CONTROL_LOAD_ENABLE(x) (((unsigned)(x) & 0x1) << 31)
#define CONTEXT_CONTROL_LOAD_CE_RAM(x) (((unsigned)(x) & 0x1) << 28)
#define CONTEXT_CONTROL_SHADOW_ENABLE(x) (((unsigned)(x) & 0x1) << 31)
#define PKT3_INDEX_TYPE 0x2A
#define PKT3_INDEX_TYPE 0x2A /* not on GFX9 */
#define PKT3_DRAW_INDIRECT_MULTI 0x2C
#define R_2C3_DRAW_INDEX_LOC 0x2C3
#define S_2C3_COUNT_INDIRECT_ENABLE(x) (((unsigned)(x) & 0x1) << 30)
@ -153,13 +162,14 @@
#define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
#define PKT3_COND_WRITE 0x45
#define PKT3_EVENT_WRITE 0x46
#define PKT3_EVENT_WRITE_EOP 0x47
#define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */
/* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets
* are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and
* DST_SEL=MC. Only CIK chips are affected.
*/
/*#define PKT3_EVENT_WRITE_EOS 0x48*/ /* fix CP DMA before uncommenting */
#define PKT3_RELEASE_MEM 0x49
/* fix CP DMA before uncommenting: */
/*#define PKT3_EVENT_WRITE_EOS 0x48*/ /* not on GFX9 */
#define PKT3_RELEASE_MEM 0x49 /* GFX9+ (any ring) or GFX8 (compute ring only) */
#define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */
#define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */
#define PKT3_SET_CONFIG_REG 0x68
@ -221,14 +231,15 @@
#define R_413_CP_DMA_WORD3 0x413 /* 0x[packet number][word index] */
#define S_413_DST_ADDR_HI(x) ((x) & 0xffff)
#define R_414_COMMAND 0x414
#define S_414_BYTE_COUNT(x) ((x) & 0x1fffff)
#define S_414_DISABLE_WR_CONFIRM(x) (((unsigned)(x) & 0x1) << 21)
#define S_414_SRC_SWAP(x) (((unsigned)(x) & 0x3) << 22)
#define S_414_BYTE_COUNT_GFX6(x) ((x) & 0x1fffff)
#define S_414_BYTE_COUNT_GFX9(x) ((x) & 0x3ffffff)
#define S_414_DISABLE_WR_CONFIRM_GFX6(x) (((unsigned)(x) & 0x1) << 21) /* not on GFX9 */
#define S_414_SRC_SWAP(x) (((unsigned)(x) & 0x3) << 22) /* not on GFX9 */
#define V_414_NONE 0
#define V_414_8_IN_16 1
#define V_414_8_IN_32 2
#define V_414_8_IN_64 3
#define S_414_DST_SWAP(x) (((unsigned)(x) & 0x3) << 24)
#define S_414_DST_SWAP(x) (((unsigned)(x) & 0x3) << 24) /* not on GFX9 */
#define V_414_NONE 0
#define V_414_8_IN_16 1
#define V_414_8_IN_32 2
@ -246,6 +257,7 @@
#define V_414_INCREMENT 0
#define V_414_NO_INCREMENT 1
#define S_414_RAW_WAIT(x) (((unsigned)(x) & 0x1) << 30)
#define S_414_DISABLE_WR_CONFIRM_GFX9(x) (((unsigned)(x) & 0x1) << 31)
#define PKT3_DMA_DATA 0x50 /* new for CIK */
/* 1. header

4
src/amd/vulkan/si_cmd_buffer.c
View file

@ -869,7 +869,7 @@ static void si_emit_cp_dma_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
{
struct radeon_winsys_cs *cs = cmd_buffer->cs;
uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM_GFX6(1) : 0;
uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
@ -917,7 +917,7 @@ static void si_emit_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer,
{
struct radeon_winsys_cs *cs = cmd_buffer->cs;
uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM_GFX6(1) : 0;
uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
uint32_t dst_sel = flags & CIK_CP_DMA_USE_L2 ? S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;

4
src/gallium/drivers/radeonsi/si_cp_dma.c
View file

@ -51,7 +51,7 @@ static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
enum r600_coherency coher)
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
uint32_t header = 0, command = S_414_BYTE_COUNT(size);
uint32_t header = 0, command = S_414_BYTE_COUNT_GFX6(size);
assert(size);
assert(size <= CP_DMA_MAX_BYTE_COUNT);
@ -60,7 +60,7 @@ static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
if (flags & CP_DMA_SYNC)
header |= S_411_CP_SYNC(1);
else
command |= S_414_DISABLE_WR_CONFIRM(1);
command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
if (flags & CP_DMA_RAW_WAIT)
command |= S_414_RAW_WAIT(1);