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radv: move db_shader_control calculation to pipeline.

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There is no need to recalculate this every time.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2017-03-28 11:34:19 +10:00
parent cd33a5c1cb
commit 8996fdbf61
3 changed files with 20 additions and 16 deletions
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16
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -674,7 +674,6 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
struct radv_blend_state *blend = &pipeline->graphics.blend;
unsigned ps_offset = 0;
unsigned z_order;
struct ac_vs_output_info *outinfo;
assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
@ -692,21 +691,8 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cmd_buffer->cs, ps->rsrc1);
radeon_emit(cmd_buffer->cs, ps->rsrc2);
if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
else
z_order = V_02880C_LATE_Z;
radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
S_02880C_Z_ORDER(z_order) |
S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
pipeline->graphics.db_shader_control);
radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
ps->config.spi_ps_input_ena);

19
src/amd/vulkan/radv_pipeline.c
View file

@ -1641,14 +1641,31 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
*
* Don't add this to CB_SHADER_MASK.
*/
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
if (!pipeline->graphics.blend.spi_shader_col_format) {
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
if (!ps->info.fs.writes_z &&
!ps->info.fs.writes_stencil &&
!ps->info.fs.writes_sample_mask)
pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
}
unsigned z_order;
pipeline->graphics.db_shader_control = 0;
if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
else
z_order = V_02880C_LATE_Z;
pipeline->graphics.db_shader_control =
S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
S_02880C_Z_ORDER(z_order) |
S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {

1
src/amd/vulkan/radv_private.h
View file

@ -955,6 +955,7 @@ struct radv_pipeline {
struct radv_depth_stencil_state ds;
struct radv_raster_state raster;
struct radv_multisample_state ms;
uint32_t db_shader_control;
unsigned prim;
unsigned gs_out;
uint32_t vgt_gs_mode;