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20134 commits

Author SHA1 Message Date
David Rosca
d1165984e9 ac/vcn_dec: Add RDECODE_IT_SCALING_TABLE_SIZE 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36645>
 2025-08-08 09:22:54 +00:00
David Rosca
532eb40404 radv/video: Remove unused enum 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36645>
 2025-08-08 09:22:54 +00:00
David Rosca
c904796350 radv/video: Simplify vp9 q params 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36645>
 2025-08-08 09:22:53 +00:00
David Rosca
27dec41c81 radv/video: Don't init vp9 probs table in message buffer 
This is needed in context buffer, but message buffer only uses the
segmentation data.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36645>
 2025-08-08 09:22:53 +00:00
David Rosca
142d54817a radv: Add timeout to video encode query 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36645>
 2025-08-08 09:22:52 +00:00
Samuel Pitoiset
2e51b50db2 radv: regroup CB related states emission together 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31659>
 2025-08-08 08:16:26 +00:00
Samuel Pitoiset
fa677ca0c3 radv: track more CB related context registers on < GFX12 
The tracked registers mechanism isn't used yet on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31659>
 2025-08-08 08:16:25 +00:00
Samuel Pitoiset
6a170c5de1 radv: precompute color blend equations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31659>
 2025-08-08 08:16:25 +00:00
Samuel Pitoiset
52589ed1e9 radv: precompute the mask for color write attachments 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31659>
 2025-08-08 08:16:25 +00:00
Samuel Pitoiset
43cc048deb radv: precompute the mask for enabled color writes 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31659>
 2025-08-08 08:16:24 +00:00
Konstantin Seurer
c4b18c689f radv: Emit compressed primitive nodes on GFX12
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Emits two triangles per node whenever possible. The nir code will
revisit the triangle node to handle the second triangle only if both
triangles are interescted by the ray.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35734>
 2025-08-07 20:23:15 +00:00
Konstantin Seurer
fb83a5793a radv/rra/gfx12: Handle compressed primitive nodes 
Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35734>
 2025-08-07 20:23:15 +00:00
Marek Olšák
900e56fc44 ac/nir: clarify the behavior of ac_nir_lower_ngg_options::can_cull
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36578>
 2025-08-07 18:12:53 +00:00
Marek Olšák
9244618e5f ac/nir/meta: allow compute blits with R5G6B5 & R5G5B5A1 formats on GFX9+ 
v2: add a workaround for incorrect hw rounding

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36578>
 2025-08-07 18:12:52 +00:00
Yonggang Luo
8e39bab014 addrlib: __debugbreak only present on Windows and from intrin.h 
Both MSVC/MINGW support this.
For fixes compiling with MINGW/GCC

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36598>
 2025-08-07 07:47:42 +00:00
Yonggang Luo
d83234c8f3 radv: Move the amdgpu.h defines for Win32 to ac_linux_drm.h 
This is for fixes compiling with MINGW/GCC

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36598>
 2025-08-07 07:47:42 +00:00
Samuel Pitoiset
9765624ed8 radv/ci: fix GPU hang detection regex with recent kernels 
Since July 2024, *ERROR* is no longer printed in dmesg and this caused
GPU hangs to not be detected with recent kernels. Hopefully, this won't
uncover more problems in CI...

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36611>
 2025-08-07 07:08:14 +00:00
jglrxavpok
b987ec42ac radv: Avoid calls to strlen when parsing umr output to speed up hang progressing 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36451>
 2025-08-07 06:44:41 +00:00
Samuel Pitoiset
4094706828 radv: invalidate compute/rt descriptors at dispatch time 
Invalidating descriptors at bind time is wrong in a scenario like
trace rays -> dispatch -> trace rays because RT uses compute shaders
and the user SGPRs need to be re-emitted.

Noticed by Konstantin.

Fixes: 40ceece75f ("radv: invalidate compute/rt descriptors at pipeline bind time")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36605>
 2025-08-07 06:26:43 +00:00
Eric Engestrom
98370280ce radv/ci: document recent flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36612>
 2025-08-06 16:15:08 +00:00
Eric Engestrom
aaab00d306 radeonsi/ci: document recent flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36612>
 2025-08-06 16:15:08 +00:00
Eric Engestrom
f6cdb2c620 radv/ci: mark all of dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.* as flaky 
Instead of adding a bunch more, let's just mark the whole group as flaky.

While at it, in the navi21 flakes
`dEQP-VK.ray_tracing_pipeline.pipeline_no_null_shaders_flag.*` already
catches the 4 lines below it, so let's drop them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36612>
 2025-08-06 16:15:08 +00:00
Hans-Kristian Arntzen
d7b17d4d9c ac/nir: Avoid 0/0 when computing texel buffer size on Polaris. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13349
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36571>
 2025-08-06 10:37:50 +00:00
Rhys Perry
08f088479a aco/ra: set late-kill for operands of temporary p_create_vector 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13543
Fixes: c279dd6e61 ("aco: Support vector-aligned ops fixed to defs")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36469>
 2025-08-06 09:44:01 +00:00
Daniel Schürmann
d3743dd7ba aco/scheduler: improve scheduling heuristic
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The heuristic we are currently using still stems from the GCN era
with the only adjustments being made for RDNA was to double (or triple)
the wave count.

This rewrite aims to detangle some concepts and provide more consistent results.

 - wave_factor: The purpose of this value is to reflect that RDNA SIMDs can
                accomodate twice as many waves as GCN SIMDs.
 - reg_file_multiple: This value accounts for the larger register file of wave32
                      and some RDNA3 families.
 - wave_minimum: Below this value, we don't sacrifice any waves. It corresponds
                 to a register demand of 64 VGPRs in wave64.
 - occupancy_factor: Depending on target_waves and wave_factor, this controls
                     the scheduling window sizes and number of moves.

The main differences from the previous heuristic is a lower wave minimum and
a slightly less aggressive reduction of waves.
It also increases SMEM_MAX_MOVES in order to mitigate some of the changes
from targeting less waves.

Totals from 62777 (78.63% of 79839) affected shaders: (Navi48)
MaxWaves: 1880983 -> 1848028 (-1.75%); split: +0.01%, -1.76%
Instrs: 40904711 -> 40800797 (-0.25%); split: -0.39%, +0.14%
CodeSize: 217132208 -> 216748832 (-0.18%); split: -0.29%, +0.12%
VGPRs: 3019304 -> 3099596 (+2.66%); split: -0.11%, +2.77%
Latency: 268857129 -> 265951122 (-1.08%); split: -1.33%, +0.25%
InvThroughput: 40960938 -> 41044533 (+0.20%); split: -0.18%, +0.39%
VClause: 794000 -> 782913 (-1.40%); split: -2.24%, +0.84%
SClause: 1192476 -> 1150831 (-3.49%); split: -3.94%, +0.45%
Copies: 2720470 -> 2700148 (-0.75%); split: -1.84%, +1.09%
Branches: 785926 -> 785951 (+0.00%); split: -0.01%, +0.01%
VALU: 22918411 -> 22890189 (-0.12%); split: -0.19%, +0.06%
SALU: 5281201 -> 5289486 (+0.16%); split: -0.21%, +0.36%
VOPD: 8790 -> 8685 (-1.19%); split: +1.08%, -2.28%

Totals from 62081 (77.77% of 79825) affected shaders: (Navi31)
MaxWaves: 1848555 -> 1812347 (-1.96%); split: +0.01%, -1.97%
Instrs: 39794460 -> 39704180 (-0.23%); split: -0.39%, +0.16%
CodeSize: 208987052 -> 208621524 (-0.17%); split: -0.31%, +0.13%
VGPRs: 3046284 -> 3135156 (+2.92%); split: -0.11%, +3.03%
Latency: 268863465 -> 265218186 (-1.36%); split: -1.59%, +0.23%
InvThroughput: 41101515 -> 41167075 (+0.16%); split: -0.22%, +0.38%
VClause: 795316 -> 774899 (-2.57%); split: -3.17%, +0.61%
SClause: 1177294 -> 1135451 (-3.55%); split: -4.06%, +0.51%
Copies: 2743254 -> 2725127 (-0.66%); split: -1.90%, +1.24%
Branches: 801395 -> 801428 (+0.00%); split: -0.01%, +0.02%
VALU: 23898938 -> 23871294 (-0.12%); split: -0.20%, +0.08%
SALU: 3908807 -> 3919130 (+0.26%); split: -0.23%, +0.50%
VOPD: 8529 -> 8500 (-0.34%); split: +1.29%, -1.63%

Totals from 44996 (71.01% of 63370) affected shaders: (Vega10)

MaxWaves: 307074 -> 304808 (-0.74%); split: +0.63%, -1.37%
Instrs: 22743534 -> 22716240 (-0.12%); split: -0.22%, +0.10%
CodeSize: 117284856 -> 117173212 (-0.10%); split: -0.19%, +0.09%
SGPRs: 3249008 -> 3330480 (+2.51%); split: -0.36%, +2.87%
VGPRs: 1901400 -> 1943880 (+2.23%); split: -0.60%, +2.83%
Latency: 224839126 -> 222878477 (-0.87%); split: -1.19%, +0.31%
InvThroughput: 114389570 -> 114316559 (-0.06%); split: -0.17%, +0.11%
VClause: 482012 -> 473304 (-1.81%); split: -2.86%, +1.05%
SClause: 757799 -> 717092 (-5.37%); split: -5.64%, +0.27%
Copies: 2182735 -> 2183598 (+0.04%); split: -1.17%, +1.21%
Branches: 396026 -> 395996 (-0.01%); split: -0.03%, +0.02%
VALU: 16740283 -> 16728098 (-0.07%); split: -0.14%, +0.07%
SALU: 2133575 -> 2145863 (+0.58%); split: -0.29%, +0.86%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30720>
 2025-08-06 09:16:33 +00:00
Samuel Pitoiset
1f490c836b ac/gpu_info,radv: use the maximum virtual address from the kernel 
Instead of hardcoding it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36573>
 2025-08-06 07:55:38 +02:00
Qiang Yu
260bdad074 all: rename gl_shader_stage_is_rt to mesa_shader_stage_is_rt 
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
 2025-08-06 10:28:41 +08:00
Qiang Yu
7a91473192 all: rename gl_shader_stage_is_compute to mesa_shader_stage_is_compute 
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
 2025-08-06 10:28:41 +08:00
Qiang Yu
196569b1a4 all: rename gl_shader_stage to mesa_shader_stage 
It's not only for GL, change to a generic name.

Use command:
  find . -type f -not -path '*/.git/*' -exec sed -i 's/\bgl_shader_stage\b/mesa_shader_stage/g' {} +

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
 2025-08-06 10:28:40 +08:00
Ernst Persson
fc8a734849 amd/vulkan: Use str.removesuffix() from Python 3.9 
Signed-off-by: Ernst Persson <ernstp@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36398>
 2025-08-05 21:39:58 +00:00
Valentine Burley
c66d4a329b radeonsi/ci: Increase Fluster job concurrency
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Fluster appears to scale well with additional threads, so bump the
concurrency, which allows reducing the `parallel`.

This is achieved by making the `radeonsi-raven-vaapi-fluster` job
not extend the `radeonsi-raven-va` job, which was setting
`FDO_CI_CONCURRENT: 1`

Also drop the timeout, as it shouldn't be set for LAVA jobs here,
and move the rules definition next to the other rules.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36369>
 2025-08-05 17:59:56 +00:00
Samuel Pitoiset
2091d199db ci: uprev VKCTS main to 9dd9a72b28218f1ca12777d9b73c2a85c5c60231 
RADV is the only driver using main.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36546>
 2025-08-05 16:12:19 +00:00
Valentine Burley
fbb42abb9b radv/ci: Add an ASan RADV job on Cezanne 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36348>
 2025-08-05 15:07:40 +00:00
Valentine Burley
b3aa602cd5 radv/ci: Use same deqp-runner suite for all RADV jobs 
The only difference was the renderer check, which only needs to confirm
"RADV".

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36348>
 2025-08-05 15:07:40 +00:00
Samuel Pitoiset
07fe297a3e vulkan: fix missing presentId2/presentWait2 enable features 
Fixes recent VKCTS changes for dEQP-VK.info.device_mandatory_features.

Fixes: 07881b085e ("vulkan: Enable PresentWait2 on many physical devices")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36547>
 2025-08-05 08:06:43 +00:00
Samuel Pitoiset
72cf81df54 radv: fix fbfetch output with compresed FMASK on <= GFX9
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GFX9 might not have DCC but compressed FMASK. In this case, it needs
to be decompressed to handle feedback loops.

Fixes new VKCTS coverage dEQP-VK.dynamic_rendering.*_ms.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36550>
 2025-08-05 07:49:31 +00:00
Pavel Asyutchenko
f4cd962434 radv: report full sparse address space size 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13588
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36423>
 2025-08-05 07:23:56 +00:00
Rhys Perry
76c96bf558 aco: fix possible scratch offset overflow 
We split vector load/store, so consider that we might add to the constant
offset.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36406>
 2025-08-04 15:06:44 +00:00
Rhys Perry
44ab4ad732 aco: align scratch size after isel 
Make it safe for VGPR spilling if it's not a multiple of 4.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36406>
 2025-08-04 15:06:43 +00:00
Rhys Perry
ab10604924 aco/gfx12: fix printing of temporal hints 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36406>
 2025-08-04 15:06:41 +00:00
Samuel Pitoiset
5062f6196f radv: replace DGC before/after dispatch helpers with the new ones 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
 2025-08-04 11:05:46 +00:00
Samuel Pitoiset
8c37fbd531 radv: add radv_{before,after}_dispatch() functions 
Similar to graphics.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
 2025-08-04 11:05:46 +00:00
Samuel Pitoiset
23e6494148 radv: handle compute/rt prefetch like graphics 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
 2025-08-04 11:05:46 +00:00
Samuel Pitoiset
b7e5bda3e2 radv: rework graphics shaders/vbos prefetch sligthly 
To add compute/rt support.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
 2025-08-04 11:05:46 +00:00
Samuel Pitoiset
23bc1cac86 radv: stop passing compute shader to radv_dispatch() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
 2025-08-04 11:05:45 +00:00
Samuel Pitoiset
40ceece75f radv: invalidate compute/rt descriptors at pipeline bind time 
No need to delay this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
 2025-08-04 11:05:45 +00:00
Eric Engestrom
9ea55d12f6 ci: uprev vkd3d to fix some nvk tests 
6be7810766...f0a3820468

The last commit fixes a vkd3d behaviour that's out of spec but is known to work
on AMD hardware to only do that on AMD, thereby fixing at least NVK.

Unfortunately, this also brings a bunch of new failures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36504>
 2025-08-04 10:35:11 +00:00
Ritesh Raj Sarraf
717adb6a01 radv/ci: Update flakes uncovered during testing 
These new/known flakes were uncovered during testing with Linux 6.16

Signed-off-by: Ritesh Raj Sarraf <ritesh.sarraf@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36493>
 2025-08-04 09:57:09 +00:00
Rhys Perry
cec845079e ac/nir/lower_ps: remove barrier for end_invocation_interlock
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SPIR-V->NIR now inserts this barrier itself.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36513>
 2025-08-04 09:30:06 +00:00
Konstantin Seurer
596ee84f16 radv: Use vk_acceleration_struct_vtx_format_supported 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36441>
 2025-08-04 08:43:07 +00:00