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all: rename gl_shader_stage_is_rt to mesa_shader_stage_is_rt

Browse source 
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
This commit is contained in:
Qiang Yu 2025-08-05 17:02:05 +08:00
parent 807d693421
commit 260bdad074
8 changed files with 11 additions and 11 deletions
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2
src/amd/vulkan/radv_pipeline.c
View file

@ -679,7 +679,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
* with LLVM, which only supports RTNE, or RT, where the mode needs to match
* across separately compiled stages.
*/
if (!radv_use_llvm_for_stage(pdev, stage->stage) && !gl_shader_stage_is_rt(stage->stage))
if (!radv_use_llvm_for_stage(pdev, stage->stage) && !mesa_shader_stage_is_rt(stage->stage))
NIR_PASS(_, stage->nir, ac_nir_opt_pack_half, gfx_level);
NIR_PASS(_, stage->nir, nir_lower_load_const_to_scalar);

2
src/amd/vulkan/radv_pipeline_cache.c
View file

@ -653,7 +653,7 @@ radv_pipeline_cache_get_binaries(struct radv_device *device, const VkAllocationC
bool complete = true;
bool is_rt = false;
for (unsigned i = 0; i < pipeline_obj->num_shaders; i++) {
if (gl_shader_stage_is_rt(pipeline_obj->shaders[i]->info.stage)) {
if (mesa_shader_stage_is_rt(pipeline_obj->shaders[i]->info.stage)) {
is_rt = true;
break;
}

4
src/amd/vulkan/radv_shader_args.c
View file

@ -554,7 +554,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics
radv_init_shader_args(device, stage, args);
if (gl_shader_stage_is_rt(stage)) {
if (mesa_shader_stage_is_rt(stage)) {
radv_declare_rt_shader_args(gfx_level, args);
return;
}
@ -883,7 +883,7 @@ radv_declare_shader_args(const struct radv_device *device, const struct radv_gra
{
declare_shader_args(device, gfx_state, info, stage, previous_stage, args, NULL);
if (gl_shader_stage_is_rt(stage))
if (mesa_shader_stage_is_rt(stage))
return;
uint32_t num_user_sgprs = args->num_user_sgprs;

4
src/amd/vulkan/radv_shader_info.c
View file

@ -485,7 +485,7 @@ radv_get_wave_size(struct radv_device *device, mesa_shader_stage stage, const st
return info->wave_size;
else if (stage == MESA_SHADER_FRAGMENT)
return pdev->ps_wave_size;
else if (gl_shader_stage_is_rt(stage))
else if (mesa_shader_stage_is_rt(stage))
return pdev->rt_wave_size;
else
return pdev->ge_wave_size;
@ -1174,7 +1174,7 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
gather_shader_info_mesh(device, nir, stage_key, info);
break;
default:
if (gl_shader_stage_is_rt(nir->info.stage))
if (mesa_shader_stage_is_rt(nir->info.stage))
gather_shader_info_rt(nir, info);
break;
}

2
src/compiler/shader_enums.h
View file

@ -116,7 +116,7 @@ mesa_shader_stage_is_callable(mesa_shader_stage stage)
}
static inline bool
gl_shader_stage_is_rt(mesa_shader_stage stage)
mesa_shader_stage_is_rt(mesa_shader_stage stage)
{
return stage == MESA_SHADER_RAYGEN || mesa_shader_stage_is_callable(stage);
}

2
src/compiler/spirv/spirv_to_nir.c
View file

@ -7353,7 +7353,7 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/5326
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/11585
*/
if (gl_shader_stage_is_rt(b->shader->info.stage)) {
if (mesa_shader_stage_is_rt(b->shader->info.stage)) {
NIR_PASS(_, b->shader, nir_remove_dead_variables, nir_var_shader_call_data,
NULL);
}

2
src/intel/compiler/brw_lower_logical_sends.cpp
View file

@ -1636,7 +1636,7 @@ lower_lsc_memory_logical_send(const brw_builder &bld, brw_inst *inst)
/* Disable LSC data port L1 cache scheme for the TGM load/store for RT
* shaders. (see HSD 18038444588)
*/
if (devinfo->ver >= 20 && gl_shader_stage_is_rt(bld.shader->stage) &&
if (devinfo->ver >= 20 && mesa_shader_stage_is_rt(bld.shader->stage) &&
inst->sfid == BRW_SFID_TGM &&
!lsc_opcode_is_atomic(op)) {
if (lsc_opcode_is_store(op)) {

4
src/intel/compiler/brw_shader.cpp
View file

@ -665,7 +665,7 @@ brw_shader::assign_curb_setup()
if (pull_constants) {
const bool pull_constants_a64 =
(gl_shader_stage_is_rt(stage) &&
(mesa_shader_stage_is_rt(stage) &&
brw_bs_prog_data(prog_data)->uses_inline_push_addr) ||
((mesa_shader_stage_is_compute(stage) ||
mesa_shader_stage_is_mesh(stage)) &&
@ -679,7 +679,7 @@ brw_shader::assign_curb_setup()
* parameter.
*/
base_addr =
gl_shader_stage_is_rt(stage) ?
mesa_shader_stage_is_rt(stage) ?
retype(bs_payload().inline_parameter, BRW_TYPE_UQ) :
retype(cs_payload().inline_parameter, BRW_TYPE_UQ);
} else {