Commit graph

188372 commits

Author SHA1 Message Date
Konstantin Seurer
3e37814956 nir/print: Do not access invalid indices of load_uniform
load_uniform does not have io_semantics and component.

Fixes: a83fd26 ("nir/print: stop trying to match i/o vars using base/driver_location")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28962>
(cherry picked from commit ea863c0c1c)
2024-04-29 16:32:37 +02:00
Yiwei Zhang
d994133c8b venus: fix to destroy all pipeline handles on early error paths
For early error returns, all pipeline handles have to be destroyed.
Otherwise the caller will treat those valid handles as successfully
created pipeline objects.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28944>
(cherry picked from commit 4ec84adbed)
2024-04-29 16:32:36 +02:00
Michel Dänzer
d051c7f304 wsi/wayland: Dispatch event queue in wsi_wl_swapchain_queue_present
With explicit sync, only if it wasn't done earlier for FIFO.

Prevents potentially unbounded memory usage for (wl_buffer.release
events in) the queue, since we don't dispatch the queue anywhere else
with explicit sync.

v2:
* Use wl_display_dispatch_queue_pending instead of
  wl_display_dispatch_queue_timeout. (Sebastian Wick)
* Call it from wsi_wl_swapchain_queue_present instead of
  wsi_wl_swapchain_acquire_next_image_explicit. (Joshua Ashton)

Fixes: 5f7a5a27ef ("wsi: Implement linux-drm-syncobj-v1")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28874>
(cherry picked from commit c3be21f177)
2024-04-29 16:32:35 +02:00
Matt Turner
7ad091b02c intel: Build float64 shader only for Vulkan
It's only used by anv and it requires glslang, which isn't otherwise
required for building iris.

Fixes: b52e25d3a8 ("anv: rewrite internal shaders using OpenCL")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28943>
(cherry picked from commit 2a417e3fc1)
2024-04-29 16:32:35 +02:00
Connor Abbott
c4e621471f ir3/ra: Don't demote movmsk instructions to non-shared
It only supports shared register destinations.

Fixes: fa22b0901a ("ir3/ra: Add specialized shared register RA/spilling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
(cherry picked from commit dbeeec2570)
2024-04-29 16:32:34 +02:00
Connor Abbott
f7a8e1a126 ir3: Add scan_clusters.macro to is_subgroup_cond_mov_macro()
Fixes: 60413e1 ("ir3: optimize subgroup operations using brcst.active")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
(cherry picked from commit 3c71667dda)
2024-04-29 16:32:34 +02:00
Connor Abbott
6b138e0e75 ir3: Add scan_clusters_macro to ir3_valid_flags()
Fixes: 60413e1 ("ir3: optimize subgroup operations using brcst.active")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
(cherry picked from commit 031b612449)
2024-04-29 16:32:33 +02:00
Erik Faye-Lund
cf443b52c7 panvk: avoid dereferencing a null-pointer
If we're passed a memory-info, but no memory-prop, we'd end up
dereferencing a null-pointer here. Let's use a fallback struct instead,
similar to what RADV does.

Fixes: d970fe2e9d ("panfrost: Add a Vulkan driver for Midgard/Bifrost GPUs")
CID: 1496060
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28856>
(cherry picked from commit 3b3df7b8a9)
2024-04-29 16:32:33 +02:00
Erik Faye-Lund
06995f634f panfrost: correct first-tracking for signature
If we unconditionally assign false to first *before* we use it, it's
never true when used. Instead, let's assign it *both* at the end *and*
when continuing.

Fixes: 4da88060d0 ("panfrost: Skip blit shader labelling if the buffer has no space")
CID: 1476270
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28856>
(cherry picked from commit 9058d5ff62)
2024-04-29 16:32:32 +02:00
Erik Faye-Lund
afb24c6612 panfrost: do not deref potentially null pointer
We need to check for failure to import *before* we dereference here.

Fixes: f94889d079 ("panfrost: Make pan_texture.{c,h} panfrost_bo agnostic")
CID: 1587376
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28856>
(cherry picked from commit 8deaf37047)
2024-04-29 16:32:31 +02:00
Boris Brezillon
926715dcb8 panfrost: do not write outside num_wg_sysval
This array has 3 components, because it's meant to hold the X, Y and Z
components of the work-group size sysval. However, mir_pick_ubo assumes
vec4 for the push-uniforms, which ends up promoting this to 4
components.

So let's make sure we don't write that last component. It's not going to
do anything good.

In practice, this leads to the viewport descriptor being smashed, which
doesn't actually do any real-world harm, because this only happens in
compute batches where that descriptor is unused. However, writing
outside of arrays is undefined behavior, so we should fix it regardless.

Fixes: 5006167061 ("panfrost: Hook-up indirect dispatch support")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28856>
(cherry picked from commit 186f7fa915)
2024-04-29 16:32:30 +02:00
David Rosca
dd48005fc6 radv/video: Report maxBitrate in encode capabilities
Some cards can do higher bitrate, but 1000 Mbit/s should be high enough
for any practical use. It's also the value that AMF reports as max bitrate.

Fixes: 54d499818c ("radv/video: add initial support for encoding with h264.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28736>
(cherry picked from commit 1f07f5a79b)
2024-04-29 16:30:26 +02:00
David Rosca
cb75aa3dfe radv/video: Check encode profiles and bit depth in capabilities query
Fixes: 967e4e09de ("radv/video: add h265 encode support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28736>
(cherry picked from commit c210bb7952)
2024-04-29 16:30:25 +02:00
David Rosca
c8a6c7ff02 radv/video: Set correct bit depth and format for 10bit input
Fixes: 967e4e09de ("radv/video: add h265 encode support")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11011
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28736>
(cherry picked from commit 2d0282f576)
2024-04-29 16:30:24 +02:00
Konstantin Seurer
3315d83248 radv: Handle all dependencies of CmdWaitEvents2
The spec describes pDependencyInfos as an array with eventCount elements.

cc: mesa-stable

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10579
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28896>
(cherry picked from commit d6c9b1d03f)
2024-04-29 16:30:21 +02:00
Ryan Neph
2bf927dcce venus: reclaim signal semaphore feedback resources for wasteful clients
Pending feedback resources (cmds, buffers, slots) for timeline semaphores are
generally reclaimed for re-use during subsequent semaphore waits/queries or any
queue submission containing at least one "wait" semaphore.

They are never reclaimed in the unexpected case when all submissions only
contain "signal" timeline semaphores, which consume such resources but
are never subsequently queried or waited upon.

This strange behavior is observed in several Valve games (Portal 2,
L4D2, CS2), which all run natively on linux with their own internal
distributions of DXVK v2.0 (at time of this MR submission). A Cursory
analysis of recent DXVK history indicates that it may be gone by v2.1.

The consequence is rapid guest memory leak and host Vk resource leak,
resulting in a crash within 1-2 minutes.

Fix that leak by running the reclaimation procedure for submissions with
_any_ accompanying semaphores.

Fixes: d63432012d ("venus: refactor semaphore feedback")
Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28915>
(cherry picked from commit ee7e0168a1)
2024-04-29 16:30:20 +02:00
Yiwei Zhang
065b7b4d37 venus: avoid client allocators for ring internals
There're many cases in which the ring submissions must succeed. We don't
worry about real oom since things would fail earlier. For simulated oom
from random intentional allocs, there isn't robust way to fail those
must succeeds. e.g. the commands that don't have return codes or valid
error return struct defaults. So real oom propagation is still at best
effort.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28914>
(cherry picked from commit 3e16d25d1a)
2024-04-29 16:30:19 +02:00
Lionel Landwerlin
1f04269566 intel/brw: fixup wm_prog_data_barycentric_modes()
Always select sample barycentric when persample dispatch is unknown at
compile time and let the payload adjustments feed the expected value
based on dispatch.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27803>
(cherry picked from commit 1bbe2d9833)
2024-04-29 16:30:18 +02:00
Mike Blumenkrantz
9eb7ff49a4 zink: fully wait on all program fences during ctx destroy
optimized pipeline compile jobs may still be ongoing during ctx
destroy, and these must complete too or else crashes will occur

fixes shutdown crash with dEQP-EGL.functional.sharing.gles2.multithread.simple.images.texture_source.teximage2d_render

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28900>
(cherry picked from commit bd1a3921d1)
2024-04-29 16:30:17 +02:00
Mike Blumenkrantz
ab4db3b681 zink: prune zink_shader::programs under lock
it's possible for a shader to be precompiling its separate shader variants
during destruction, which requires that the programs set be iterated
under lock in order to prune every new variant as it is created without
crashing

fixes crashes in spec@arb_separate_shader_objects@400 combinations.*

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28900>
(cherry picked from commit f18a1d3a31)
2024-04-29 16:30:17 +02:00
Iván Briano
0e3116b978 anv: check requirements for VK_IMAGE_USAGE_FRAGMENT_SHADING_RATE
Somehow I missed this one in 164c0951a0

If the format the image is being created with doesn't have the FSR
format feature, report it as unsupported.

Also fixes future CTS tests: dEQP-VK.api.info.unsupported_image_usage.*

Cc: mesa-stable

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28913>
(cherry picked from commit 8ebf07eccd)
2024-04-29 16:30:16 +02:00
Eric Engestrom
89c7f85d5d ci: pass MESA_VK_ABORT_ON_DEVICE_LOSS through to the DUT
Fixes: 9bbbe90f06 ("ci: enable MESA_VK_ABORT_ON_DEVICE_LOSS globally")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28940>
(cherry picked from commit 497672ac74)
2024-04-29 16:30:15 +02:00
Tomeu Vizoso
d80f150bbf etnaviv/nn: Make parallel jobs disabled by default
It doesn't work for all models, with the same happening to the
proprietary driver. There may be some hardware limitation on at least
the HW that is currently supported in Mesa.

So match what the proprietary driver is doing and disable by default.

Fixes: d6473ce28e ("etnaviv: Use NN cores to accelerate convolutions")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28918>
(cherry picked from commit 1277f58d8a)
2024-04-29 16:30:13 +02:00
Rohan Garg
7d8190bc7e anv: formatting fix when printing pipe controls
Fixes: abc4111 ('anv: pass steam output as argument for anv_dump_pipe_bits')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28931>
(cherry picked from commit b406759479)
2024-04-29 16:30:13 +02:00
Mike Blumenkrantz
9ff7c70589 zink: reconstruct features pnext after determining extension support
for extensions that require features/properties to enable support, this
avoids adding the feature struct to the device createinfo

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11067

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28925>
(cherry picked from commit 2c180c47f7)
2024-04-29 16:30:12 +02:00
Daniel Schürmann
0cbf577433 aco/ra: fix kill flags after renaming fixed Operands
Suggested-by: Rhys Perry <pendingchaos02@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28876>
(cherry picked from commit be1e68b4ee)
2024-04-29 16:30:12 +02:00
Eric Engestrom
4f205bc37e .pick_status.json: Update to 8248cc0bf4 2024-04-29 16:30:08 +02:00
Mike Blumenkrantz
30f5352649 glthread: check for invalid primitive modes in DrawElementsBaseVertex
fixes KHR-GLESEXT.draw_elements_base_vertex_tests.invalid_mode_argument

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28903>
(cherry picked from commit 4660ee1dea)
2024-04-25 16:50:35 +02:00
Constantine Shablia
15466d7d79 pan/bi: fix 1D array tex coord lowering
We were erroneously specifying Y for 1D arrays

Cc: mesa-stable
Suggested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28899>
(cherry picked from commit 3139f8f623)
2024-04-25 16:50:28 +02:00
Mary Guillemard
01f45e49d4 nak: Pass has_mod to all form of src2 requiring it
This was missing from the original changes and was causing HFMA2 to
misbehave with an immediate value.

Also fix inverted value passed around for cbuf and ureg forms.

Fixes: bad23ddb48 ("nak: Add F16 and F16v2 sources")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28828>
(cherry picked from commit 40422927dc)
2024-04-25 16:50:28 +02:00
Lionel Landwerlin
e08d22ae86 anv: disable dual source blending state if not used in shader
Fixing some simulation issues on Gfx9/11 with zink on anv running dual
source blending piglit tests like :

   ./bin/arb_blend_func_extended-dual-src-blending-discard-without-src1 -auto -fbo

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28901>
(cherry picked from commit 68dfe17abc)
2024-04-25 16:50:27 +02:00
Kenneth Graunke
cc5da81e31 isl: Set MOCS to uncached for Gfx12.0 blitter sources/destinations
We were accidentally leaving XY_BLOCK_COPY_BLT's Source and Destination
MOCS fields set to 0 (Error: Reserved for Non-Use) on Gfx12.0 systems.
This was causing assert fails in debug builds, since we try to ensure
that we don't do that.  In theory, MOCS 0 is supposed to be equivalent
to MOCS 2 (all the caching), but...we probably ought to use MOCS 3
(uncached).  Every Gfx12.5+ platform requires it, so although there
isn't a note about Gfx12.0 needing that, it's possible that it does.
We're currently only using the blitter for DRI PRIME blits on Gfx12.0,
anyway, and I think we're flushing all the caches regardless.

This bug was somewhat obscure to hit:
- You need a hybrid graphics system with Gfx12.0 and some other GPU
- You have to be using "reverse PRIME", i.e. rendering on the integrated
  GPU and displaying on the discrete one.  This is not the common case.
- You have to be using a debug build.

No observable performance delta in GfxBench5 Car Chase (an arbitrary
program) when rendering on Alderlake GT1 and displaying on an Arc A770.

Fixes: 194afe8416 ("anv/iris/blorp: use the right MOCS values for each engine")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28894>
(cherry picked from commit e6fb3ba037)
2024-04-25 16:50:27 +02:00
Samuel Pitoiset
99627c617c radv: fix image format properties with fragment shading rate usage
This was missing and this caused test failures for formats different
than VK_FORMAT_R8_UINT which is the only one supported for FSR.

Fixes recent
dEQP-VK.api.info.unsupported_image_usage.*.fragment_shading_rate_attachment.*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28893>
(cherry picked from commit e8d94536d2)
2024-04-25 16:50:26 +02:00
Eric Engestrom
6927823307 .pick_status.json: Update to 84632dce93 2024-04-25 16:50:22 +02:00
Eric Engestrom
1d8901f345 ci: fix container rules on release branches and tags
Fixes: 2487e18d4e ("ci: bare-metal: poe: Create strutured logs")
Fixes: 7c0b19a607 ("ci: run python-test automatically only in merge pipelines")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28911>
(cherry picked from commit 0666a715c7)
2024-04-25 16:48:54 +02:00
Eric Engestrom
418e19a6ff .pick_status.json: Update to 4660ee1dea 2024-04-25 16:16:21 +02:00
Eric Engestrom
b0de5e98f0 VERSION: bump for 24.1.0-rc1 2024-04-24 22:28:09 +02:00
Marek Olšák
c3fc214a98 radeonsi: implement user_data_amd for 5, 6, and 7 components correctly
NIR can't handle those component counts, so we have to split it into 2
SGPR vectors where each has max 4 components.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
882ee264a6 radeonsi: use ip_type in debug code instead of hardcoding GFX
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
e7000c02e4 radeonsi: always run nir_opt_16bit_tex_image
It optimizes constants in srcs to 16 bits.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
18bcdbb634 radeonsi: only expose 8 EQAA samples due to shader limitations
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
256cc77f84 radeonsi: don't add whether NIR is used into the shader key
This is from when we had TGSI and NIR was a debug option.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
e5c8f0781c radeonsi: make clear_render_target clear DCC directly instead of via pipe->clear()
This extracts the relevant parts from si_fast_clear.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
eccaba9dfa radeonsi: enable fast FB clears for conditional rendering
They use compute shaders, which always support the render condition.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
9a47fbecd7 radeonsi: don't flush CB and DB if there have been no draw calls
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
f0160443a2 radeonsi: don't flush CB in si_launch_grid_internal_images if not needed
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
708f57e681 radeonsi: don't use si_get_flush_flags() for flushing images
si_make_{CB/DB}_shader_coherent are more correct.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
38f74d6277 radeonsi: disable VRS flat shading for selected 8xMSAA and thick tiling cases
for better slow clear performance

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
86131c25a1 radeonsi/gfx11: implement DCC clear to "single" for fast non-0/1 clears
If the clear color isn't 0 or 1, we used a slow clear. This adds a new
DCC clear where the DCC buffer is cleared to a special value and the clear
color is stored at the beginning of each 256B block in the image.

It can be very fast, but it's not always faster than a slow clear.
There is a heuristic that determines whether this new fast clear is
better.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00
Marek Olšák
10ec468983 radeonsi: don't call resource_copy_region in pipe->blit
It's slower because it forces preservation of NaNs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
2024-04-24 19:17:10 +00:00