Commit graph

528 commits

Author SHA1 Message Date
Nicolai Hähnle
3c78215a1c tgsi: clarify the semantics of DFRACEXP
The status quo is quite the mess:

1. tgsi_exec will do a per-channel computation, and store the dst[0]
   result (significand) correctly for each channel. The dst[1] result
   (exponent) will be written to the first bit set in the writemask.
   So per-component calculation only works partially.

2. r600 will only do a single computation. It will replicate the
   exponent but not the significand.

3. The docs pretend that there's per-component calculation, but even
   get dst[0] and dst[1] confused.

4. Luckily, st_glsl_to_tgsi only ever emits single-component instructions,
   and kind-of assumes that everything is replicated, generating this for
   the dvec4 case:

     DFRACEXP TEMP[0].xy, TEMP[1].x, CONST[0][0].xyxy
     DFRACEXP TEMP[0].zw, TEMP[1].y, CONST[0][0].zwzw
     DFRACEXP TEMP[2].xy, TEMP[1].z, CONST[0][1].xyxy
     DFRACEXP TEMP[2].zw, TEMP[1].w, CONST[0][1].zwzw

Settle on the simplest behavior, which is single-component calculation
with replication, document it, and adjust tgsi_exec and r600.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-09-29 12:07:50 +02:00
Nicolai Hähnle
dbe7fc00d5 tgsi: fix the documentation of DLDEXP
Sourcing the exponent for the zw destination pair from Z is consistent
with both tgsi_exec and gallivm. In practice, st_glsl_to_tgsi always
generates per-channel instructions anyway.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-09-29 12:07:46 +02:00
Gwan-gyeong Mun
5603670bc0 gallium/docs: add reference links for resource_create method
It adds reference links for arguments usage and bind of resource_create().

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-28 13:20:14 +01:00
Gwan-gyeong Mun
c6c23e95a7 gallium/docs: fix a reference link for get_paramf
Previous get_paramf links same as get_param. It changes the reference link to
PIPE_CAPF_*

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-28 13:20:14 +01:00
Jan Vesely
9c87150618 gallium: Add PIPE_SHADER_CAP_INT64_ATOMICS
Denotes availability of 64bit int atomic instructions

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-21 11:18:17 -04:00
Jan Vesely
7b2c5547c3 gallium: Add PIPE_SHADER_CAP_FP16
Denotes native half precision float operations capability
v2: PIPE_CAP_HALFS -> PIPE_SHADER_CAP_FP16
    fix indentation

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-18 10:45:02 -04:00
Nicolai Hähnle
3f6b3d9db7 gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
To be able to properly distinguish between GL_ANY_SAMPLES_PASSED
and GL_ANY_SAMPLES_PASSED_CONSERVATIVE.

This patch goes through all drivers, having them treat the two
query types identically, except:

1. radeon incorrectly enabled conservative mode on
   PIPE_QUERY_OCCLUSION_PREDICATE. We now do it correctly, only
   on PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE.
2. st/mesa uses the new query type.

Fixes dEQP-GLES31.functional.fbo.no_attachments.*

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-18 11:25:18 +02:00
Timothy Arceri
c96e45ebf0 gallium: introduce PIPE_CAP_LOAD_CONSTBUF
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-15 11:42:55 +10:00
Nicolai Hähnle
37dd8e8dee gallium: all drivers should accept two-dimensional constant buffer indexing
Most older drivers seem to just ignore the Dimension setting, so virtually
no changes should be needed.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-04 13:43:36 +02:00
Gwan-gyeong Mun
c261bc11e6 gallium/docs: Fix an inequality sign of TGSI_SEMANTIC_SUBGROUP_LT_MASK
A previous expression presents same as TGSI_SEMANTIC_SUBGROUP_GT_MASK.
It fixes a direction of an inequality for TGSI_SEMANTIC_SUBGROUP_LT_MASK.

before:
  bit index > TGSI_SEMANTIC_SUBGROUP_INVOCATION

after:
  bit index < TGSI_SEMANTIC_SUBGROUP_INVOCATION

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-28 12:05:44 +02:00
Gwan-gyeong Mun
db91b8536e gallium/docs: fix a typo
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-28 10:33:42 +02:00
Gwan-gyeong Mun
9649c6acce gallium/docs: Fix the math formula of U2I64
before:
  dst.xy = (uint64_t) src0.x
  dst.zw = (uint64_t) src0.y

after:
  dst.xy = (int64_t) src0.x
  dst.zw = (int64_t) src0.y

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-23 14:09:49 +02:00
Gwan-gyeong Mun
9aabf80ef3 gallium/docs: Add missing word "Not"
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-23 14:09:22 +02:00
Marek Olšák
497506ad93 gallium: remove TGSI opcode SCS
use COS+SIN instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2017-08-22 16:42:17 +02:00
Marek Olšák
cdaaf66566 gallium: remove TGSI opcode BREAKC
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:33:48 +02:00
Marek Olšák
985e6b5ef9 gallium: remove TGSI opcode XPD
use MUL+MAD+MOV instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
3e2ff8fade gallium: remove TGSI opcode DPH
use DP4 or DP3 + ADD.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
86e6f7a73b gallium: remove TGSI opcode DP2A
use DP3 instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
0bb367830a gallium: remove TGSI_OPCODE_CALLNZ
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
068c3ad2cb gallium: remove TGSI FENCE opcodes
use MEMBAR instead

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
44716655e6 gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZ
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Brian Paul
426673e271 gallium/docs: add more info about TXF and MSAA textures
If the texture is multisampled, the coord.w component indicates which
sample to fetch.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-03 14:13:57 -06:00
Brian Paul
722ba1ad19 gallium/docs: document automatic per-sample FS execution
Both the GLSL 4.00 specs and DX10.1 specs specify that if a fragment
shader uses the sample ID or sample position inputs, the shader is
automatically run at per sample frequency.  Document that expectation
for gallium fragment shaders.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-03 14:13:57 -06:00
Timothy Arceri
4e4042df6b gallium: introduce PIPE_CAP_MEMOBJ
This can be used to guard support for EXT_memory_object and related
extensions.

v2: update gallium docs

v3 (Timothy Arceri):
 - add cap to nv50

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-08-03 13:57:16 +10:00
Nicolai Hähnle
a677799e51 gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE and corresponding cap
v2: rename cap to PIPE_CAP_QUERY_SO_OVERFLOW and be a bit more explicit
    in the documentation

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-02 09:37:10 +02:00
Nicolai Hähnle
01f1598a40 gallium: add PIPE_CAP_NIR_SAMPLERS_AS_DEREF
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-31 14:55:29 +02:00
Karol Herbst
c5cbb9a543 gallium/docs: add precise instruction modifier
v4: add comment about intermediate rounding step to MAD

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-07-21 23:45:18 -04:00
Brian Paul
e54fe78e0e gallium/docs: document that TXF is used with PIPE_BUFFER resources
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-06-30 13:37:10 -06:00
Brian Paul
f4091e1638 gallium/docs: clarify that samplers are not used with PIPE_BUFFER resources
Commit 8aba778fa2 "st/mesa: don't set
sampler states for TBOs" changed how texture buffer objects are handled.
Document the new convention.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-06-30 13:37:10 -06:00
Brian Paul
1c33dc77f7 gallium/docs: improve docs for SAMPLE_POS, SAMPLE_INFO, TXQS, MSAA semantics
For the SAMPLE_POS and SAMPLE_INFO opcodes, clarify resource vs. render
target queries, range of postion values, swizzling, etc.  We basically
follow the DX10.1 conventions.

For the TXQS opcode and TGSI_SEMANTIC_SAMPLEID, clarify return value
and type.

For the TGSI_SEMANTIC_SAMPLEPOS system value, clarify the range of
positions returned.

v2: use 'undef' for unused vector components.  Use (0.5, 0.5, undef, undef)
for sample pos when MSAA not applicable.

v3: Add note that OPCODE_SAMPLE_INFO, OPCODE_SAMPLE_POS are not used yet
and the information is subject to change.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-06-16 14:07:31 -06:00
Samuel Pitoiset
8a68b4de08 gallium: add ARB_bindless_texture interface
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-14 10:04:36 +02:00
Samuel Pitoiset
973822bcee gallium: add PIPE_CAP_BINDLESS_TEXTURE
Whether bindless texture operations are supported by the
underlying driver.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-14 10:04:36 +02:00
Brian Paul
def8d1d23f gallium/docs: clarify TGSI_SEMANTIC_SAMPLEMASK, again
I've since discovered the fragment shader sample mask system value (which
corresponds to gl_SampleMaskIn).

v2: It's a system value, not a shader input.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-13 08:02:43 -06:00
Marek Olšák
7448342a1f gallium/docs: clarify gen_name/get_vendor/get_device_vendor behavior
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Brian Paul
81e15a5dea tgsi: clarify TGSI_SEMANTIC_SAMPLEMASK documentation
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-09 08:51:56 -06:00
Lyude
467af445a3 gallium: Add a cap to check if the driver supports ARB_post_depth_coverage
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-06-02 23:19:22 -04:00
Lyude
af788a82d5 gallium: Add TGSI shader token for ARB_post_depth_coverage
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-06-02 23:19:22 -04:00
Marek Olšák
50189379fa gallium: add PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
for skipping mapped-buffer checking in every GL draw call

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-17 20:28:44 +02:00
Marek Olšák
70dcb7377d gallium: add PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
The next patch will use it. This is really for svga and GL2-level drivers.

Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-05-10 19:29:08 +02:00
Marek Olšák
330d0607ed gallium: remove pipe_index_buffer and set_index_buffer
pipe_draw_info::indexed is replaced with index_size. index_size == 0 means
non-indexed.

Instead of pipe_index_buffer::offset, pipe_draw_info::start is used.
For indexed indirect draws, pipe_draw_info::start is added to the indirect
start. This is the only case when "start" affects indirect draws.

pipe_draw_info::index is a union. Use either index::resource or
index::user depending on the value of pipe_draw_info::has_user_indices.

v2: fixes for nine, svga
2017-05-10 19:00:16 +02:00
Marek Olšák
22f6624ed3 gallium: separate indirect stuff from pipe_draw_info - 80 -> 56 bytes
For faster initialization of non-indirect draws.
2017-05-10 19:00:16 +02:00
Samuel Pitoiset
3a927e0aa3 gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-26 19:15:34 +02:00
Nicolai Hähnle
f3d2cf6c1f tgsi: clarify TGSI_SEMANTIC_{LAYER,VIEWPORT_INDEX}
Depending on pipe caps they can be writable in all vertex processing
stages, but only the output of the last stage counts.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-04-14 22:50:06 +02:00
Nicolai Hähnle
17f24a9b75 gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-04-14 22:49:44 +02:00
Tim Rowley
4dcfa83114 swr: update gallium driver docs
v2: add back scons section, mention additional built swr libraries

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-14 15:21:31 -05:00
Rob Clark
16d493f1e7 gallium/docs: small correction about register files for atomics
These can operate on MEMORY[], in addition to BUFFER[] and IMAGE[]

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-14 12:46:12 -04:00
Ilia Mirkin
5dd490f134 gallium: fix some math formulas to display better
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-07 20:20:17 -04:00
Ilia Mirkin
08bd0aa507 tgsi: add SUBGROUP_* semantics
v2: add documentation (Nicolai)

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 15:29:41 +02:00
Ilia Mirkin
3650d7455f tgsi: add BALLOT/READ_* opcodes
v2 (Nicolai):
- BALLOT isn't per-channel
- expand the documentation (also for VOTE_*)

v3:
- only BALLOT returns a 64-bit lanemask (Boyan)
- relax the requirement on READ_INVOC: the invocation number to read
  from must be uniform within a sub-group. This matches the
  GL_ARB_shader_ballot spect (and the v_readlane instruction of AMD
  GCN)

v4:
- hopefully really fix the doc of VOTE_* returns (Ilia)

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
2017-04-05 15:29:34 +02:00
Nicolai Hähnle
d3e6f6d7f7 gallium: add PIPE_CAP_TGSI_BALLOT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 15:29:31 +02:00