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gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Samuel Pitoiset 2017-04-25 00:31:46 +02:00
parent ec301497b8
commit 3a927e0aa3
15 changed files with 21 additions and 0 deletions
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1
src/gallium/auxiliary/gallivm/lp_bld_limits.h
View file

@ -135,6 +135,7 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;

1
src/gallium/auxiliary/tgsi/tgsi_exec.h
View file

@ -527,6 +527,7 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
return PIPE_MAX_SHADER_BUFFERS;

3
src/gallium/docs/source/screen.rst
View file

@ -489,6 +489,9 @@ to be 0.
cost than this value should be lowered by the state tracker for better
performance. This is a tunable for the GLSL compiler and the behavior is
specific to the compiler.
* ``PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS``: Whether the merge registers
TGSI pass is skipped. This might reduce code size and register pressure if
the underlying driver has a real backend compiler.
.. _pipe_compute_cap:

1
src/gallium/drivers/etnaviv/etnaviv_screen.c
View file

@ -438,6 +438,7 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
}

1
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -520,6 +520,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
}
debug_printf("unknown shader param %d\n", param);

2
src/gallium/drivers/nouveau/nv30/nv30_screen.c
View file

@ -313,6 +313,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
default:
debug_printf("unknown vertex shader param %d\n", param);
@ -360,6 +361,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
default:
debug_printf("unknown fragment shader param %d\n", param);

1
src/gallium/drivers/nouveau/nv50/nv50_screen.c
View file

@ -357,6 +357,7 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_SUPPORTED_IRS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
default:
NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);

1
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
View file

@ -390,6 +390,7 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
return NVC0_MAX_BUFFERS;

2
src/gallium/drivers/r300/r300_screen.c
View file

@ -352,6 +352,7 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
@ -412,6 +413,7 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;

1
src/gallium/drivers/r600/r600_pipe.c
View file

@ -581,6 +581,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
/* due to a bug in the shader compiler, some loops hang

1
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -693,6 +693,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_SUPPORTED_IRS:
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
}
return 0;

3
src/gallium/drivers/svga/svga_screen.c
View file

@ -511,6 +511,7 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
@ -571,6 +572,7 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
@ -665,6 +667,7 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;

1
src/gallium/drivers/vc4/vc4_screen.c
View file

@ -411,6 +411,7 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
default:
fprintf(stderr, "unknown shader param %d\n", param);

1
src/gallium/drivers/virgl/virgl_screen.c
View file

@ -327,6 +327,7 @@ virgl_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 4096 * sizeof(float[4]);
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
default:
return 0;
}

1
src/gallium/include/pipe/p_defines.h
View file

@ -830,6 +830,7 @@ enum pipe_shader_cap
PIPE_SHADER_CAP_SUPPORTED_IRS,
PIPE_SHADER_CAP_MAX_SHADER_IMAGES,
PIPE_SHADER_CAP_LOWER_IF_THRESHOLD,
PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS,
};
/**