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gallium: remove TGSI opcode BREAKC

Browse source 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-08-20 12:41:13 +02:00
parent 985e6b5ef9
commit cdaaf66566
13 changed files with 7 additions and 133 deletions
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1
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
View file

@ -1198,7 +1198,6 @@ lp_set_default_actions(struct lp_build_tgsi_context * bld_base)
bld_base->op_actions[TGSI_OPCODE_SCS] = scs_action;
bld_base->op_actions[TGSI_OPCODE_UP2H] = up2h_action;
bld_base->op_actions[TGSI_OPCODE_BREAKC].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_SWITCH].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_CASE].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_COS].fetch_args = scalar_unary_fetch_args;

1
src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
View file

@ -438,7 +438,6 @@ analyse_instruction(struct analysis_context *ctx,
case TGSI_OPCODE_ENDIF:
case TGSI_OPCODE_BGNLOOP:
case TGSI_OPCODE_BRK:
case TGSI_OPCODE_BREAKC:
case TGSI_OPCODE_CONT:
case TGSI_OPCODE_ENDLOOP:
case TGSI_OPCODE_CAL:

43
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
View file

@ -402,30 +402,6 @@ static void lp_exec_break(struct lp_exec_mask *mask,
lp_exec_mask_update(mask);
}
static void lp_exec_break_condition(struct lp_exec_mask *mask,
LLVMValueRef cond)
{
LLVMBuilderRef builder = mask->bld->gallivm->builder;
struct function_ctx *ctx = func_ctx(mask);
LLVMValueRef cond_mask = LLVMBuildAnd(builder,
mask->exec_mask,
cond, "cond_mask");
cond_mask = LLVMBuildNot(builder, cond_mask, "break_cond");
if (ctx->break_type == LP_EXEC_MASK_BREAK_TYPE_LOOP) {
mask->break_mask = LLVMBuildAnd(builder,
mask->break_mask,
cond_mask, "breakc_full");
}
else {
mask->switch_mask = LLVMBuildAnd(builder,
mask->switch_mask,
cond_mask, "breakc_switch");
}
lp_exec_mask_update(mask);
}
static void lp_exec_continue(struct lp_exec_mask *mask)
{
LLVMBuilderRef builder = mask->bld->gallivm->builder;
@ -3477,24 +3453,6 @@ brk_emit(
lp_exec_break(&bld->exec_mask, bld_base);
}
static void
breakc_emit(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
LLVMBuilderRef builder = bld_base->base.gallivm->builder;
struct lp_build_context *uint_bld = &bld_base->uint_bld;
LLVMValueRef unsigned_cond =
LLVMBuildBitCast(builder, emit_data->args[0], uint_bld->vec_type, "");
LLVMValueRef cond = lp_build_cmp(uint_bld, PIPE_FUNC_NOTEQUAL,
unsigned_cond,
uint_bld->zero);
lp_exec_break_condition(&bld->exec_mask, cond);
}
static void
if_emit(
const struct lp_build_tgsi_action * action,
@ -3876,7 +3834,6 @@ lp_build_tgsi_soa(struct gallivm_state *gallivm,
bld.bld_base.op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
bld.bld_base.op_actions[TGSI_OPCODE_BGNSUB].emit = bgnsub_emit;
bld.bld_base.op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
bld.bld_base.op_actions[TGSI_OPCODE_BREAKC].emit = breakc_emit;
bld.bld_base.op_actions[TGSI_OPCODE_CAL].emit = cal_emit;
bld.bld_base.op_actions[TGSI_OPCODE_CASE].emit = case_emit;
bld.bld_base.op_actions[TGSI_OPCODE_CONT].emit = cont_emit;

3
src/gallium/auxiliary/nir/tgsi_to_nir.c
View file

@ -1582,9 +1582,6 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_FSLT] = nir_op_flt,
[TGSI_OPCODE_FSNE] = nir_op_fne,
/* No control flow yet */
[TGSI_OPCODE_BREAKC] = 0, /* not emitted by glsl_to_tgsi.cpp */
[TGSI_OPCODE_KILL_IF] = 0,
[TGSI_OPCODE_END] = 0,

19
src/gallium/auxiliary/tgsi/tgsi_exec.c
View file

@ -5557,25 +5557,6 @@ exec_instruction(
case TGSI_OPCODE_NOP:
break;
case TGSI_OPCODE_BREAKC:
IFETCH(&r[0], 0, TGSI_CHAN_X);
/* update CondMask */
if (r[0].u[0] && (mach->ExecMask & 0x1)) {
mach->LoopMask &= ~0x1;
}
if (r[0].u[1] && (mach->ExecMask & 0x2)) {
mach->LoopMask &= ~0x2;
}
if (r[0].u[2] && (mach->ExecMask & 0x4)) {
mach->LoopMask &= ~0x4;
}
if (r[0].u[3] && (mach->ExecMask & 0x8)) {
mach->LoopMask &= ~0x8;
}
/* Todo: if mach->LoopMask == 0, jump to end of loop */
UPDATE_EXEC_MASK(mach);
break;
case TGSI_OPCODE_F2I:
exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
break;

5
src/gallium/auxiliary/tgsi/tgsi_info.c
View file

@ -151,8 +151,8 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
{ 1, 2, 0, 0, 0, 0, 0, COMP, "FSNE", TGSI_OPCODE_FSNE },
{ 0, 1, 0, 0, 0, 0, 0, OTHR, "MEMBAR", TGSI_OPCODE_MEMBAR },
{ 0, 1, 0, 0, 0, 0, 0, NONE, "", 113 }, /* removed */
{ 0, 1, 0, 0, 0, 0, 0, NONE, "", 114 }, /* removed */
{ 0, 1, 0, 0, 0, 0, 0, NONE, "BREAKC", TGSI_OPCODE_BREAKC },
{ 0, 1, 0, 0, 0, 0, 0, NONE, "", 114 }, /* removed */
{ 0, 1, 0, 0, 0, 0, 0, NONE, "", 115 }, /* removed */
{ 0, 1, 0, 0, 0, 0, 0, NONE, "KILL_IF", TGSI_OPCODE_KILL_IF },
{ 0, 0, 0, 0, 0, 0, 0, NONE, "END", TGSI_OPCODE_END },
{ 1, 3, 0, 0, 0, 0, 0, COMP, "DFMA", TGSI_OPCODE_DFMA },
@ -477,7 +477,6 @@ tgsi_opcode_infer_src_type( uint opcode )
case TGSI_OPCODE_UIF:
case TGSI_OPCODE_TXF:
case TGSI_OPCODE_TXF_LZ:
case TGSI_OPCODE_BREAKC:
case TGSI_OPCODE_U2F:
case TGSI_OPCODE_U2D:
case TGSI_OPCODE_UADD:

1
src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
View file

@ -119,7 +119,6 @@ OP00(BGNSUB)
OP00_LBL(ENDLOOP)
OP00(ENDSUB)
OP00(NOP)
OP01(BREAKC)
OP01(KILL_IF)
OP00(END)
OP11(F2I)

16
src/gallium/docs/source/tgsi.rst
View file

@ -1596,7 +1596,7 @@ GLSL ISA
These opcodes are part of :term:`GLSL`'s opcode set. Support for these
opcodes is determined by a special capability bit, ``GLSL``.
Some require glsl version 1.30 (UIF/BREAKC/SWITCH/CASE/DEFAULT/ENDSWITCH).
Some require glsl version 1.30 (UIF/SWITCH/CASE/DEFAULT/ENDSWITCH).
.. opcode:: CAL - Subroutine Call
@ -1652,20 +1652,6 @@ Some require glsl version 1.30 (UIF/BREAKC/SWITCH/CASE/DEFAULT/ENDSWITCH).
or switch/endswitch.
.. opcode:: BREAKC - Break Conditional
Conditionally moves the point of execution to the instruction after the
next endloop or endswitch. The instruction must appear within a loop/endloop
or switch/endswitch.
Condition evaluates to true if src0.x != 0 where src0.x is interpreted
as an integer register.
.. note::
Considered for removal as it's quite inconsistent wrt other opcodes
(could emulate with UIF/BRK/ENDIF).
.. opcode:: IF - Float If
Start an IF ... ELSE .. ENDIF block. Condition evaluates to true if

1
src/gallium/drivers/r300/r300_tgsi_to_rc.c
View file

@ -115,7 +115,6 @@ static unsigned translate_opcode(unsigned opcode)
/* case TGSI_OPCODE_ENDLOOP2: return RC_OPCODE_ENDLOOP2; */
/* case TGSI_OPCODE_ENDSUB: return RC_OPCODE_ENDSUB; */
case TGSI_OPCODE_NOP: return RC_OPCODE_NOP;
/* case TGSI_OPCODE_BREAKC: return RC_OPCODE_BREAKC; */
case TGSI_OPCODE_KILL_IF: return RC_OPCODE_KIL;
}

45
src/gallium/drivers/r600/r600_shader.c
View file

@ -8733,45 +8733,6 @@ static int tgsi_endloop(struct r600_shader_ctx *ctx)
return 0;
}
static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
{
int r;
unsigned int fscp;
for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
{
if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
break;
}
if (fscp == 0) {
R600_ERR("BREAKC not inside loop/endloop pair\n");
return -EINVAL;
}
if (ctx->bc->chip_class == EVERGREEN &&
ctx->bc->family != CHIP_CYPRESS &&
ctx->bc->family != CHIP_JUNIPER) {
/* HW bug: ALU_BREAK does not save the active mask correctly */
r = tgsi_uif(ctx);
if (r)
return r;
r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
if (r)
return r;
fc_set_mid(ctx, fscp - 1);
return tgsi_endif(ctx);
} else {
r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
if (r)
return r;
fc_set_mid(ctx, fscp - 1);
}
return 0;
}
static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
{
unsigned int fscp;
@ -9104,7 +9065,7 @@ static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[]
[TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
[113] = { ALU_OP0_NOP, tgsi_unsupported},
[114] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
[115] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
[TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
[TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
@ -9302,7 +9263,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
[TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
[113] = { ALU_OP0_NOP, tgsi_unsupported},
[114] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
[115] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
[TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
/* Refer below for TGSI_OPCODE_DFMA */
@ -9525,7 +9486,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
[TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
[113] = { ALU_OP0_NOP, tgsi_unsupported},
[114] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
[115] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
[TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
/* Refer below for TGSI_OPCODE_DFMA */

2
src/gallium/drivers/svga/svga_tgsi_vgpu10.c
View file

@ -578,8 +578,6 @@ translate_opcode(unsigned opcode)
return VGPU10_OPCODE_RET;
case TGSI_OPCODE_NOP:
return VGPU10_OPCODE_NOP;
case TGSI_OPCODE_BREAKC:
return VGPU10_OPCODE_BREAKC;
case TGSI_OPCODE_END:
return VGPU10_OPCODE_RET;
case TGSI_OPCODE_F2I:

1
src/gallium/include/pipe/p_shader_tokens.h
View file

@ -453,7 +453,6 @@ struct tgsi_property_data {
#define TGSI_OPCODE_MEMBAR 112
/* gap */
#define TGSI_OPCODE_BREAKC 115
#define TGSI_OPCODE_KILL_IF 116 /* conditional kill */
#define TGSI_OPCODE_END 117 /* aka HALT */
#define TGSI_OPCODE_DFMA 118

2
src/gallium/state_trackers/nine/nine_shader.c
View file

@ -2954,7 +2954,7 @@ struct sm1_op_info inst_table[] =
_OPI(ELSE, ELSE, V(2,0), V(3,0), V(2,1), V(3,0), 0, 0, SPECIAL(ELSE)),
_OPI(ENDIF, ENDIF, V(2,0), V(3,0), V(2,1), V(3,0), 0, 0, SPECIAL(ENDIF)),
_OPI(BREAK, BRK, V(2,1), V(3,0), V(2,1), V(3,0), 0, 0, NULL),
_OPI(BREAKC, BREAKC, V(2,1), V(3,0), V(2,1), V(3,0), 0, 2, SPECIAL(BREAKC)),
_OPI(BREAKC, NOP, V(2,1), V(3,0), V(2,1), V(3,0), 0, 2, SPECIAL(BREAKC)),
/* we don't write to the address register, but a normal register (copied
* when needed to the address register), thus we don't use ARR */
_OPI(MOVA, MOV, V(2,0), V(3,0), V(0,0), V(0,0), 1, 1, NULL),