Commit graph

76907 commits

Author SHA1 Message Date
Ilia Mirkin
1d708aacb7 gk110/ir: fix imad sat/hi flag emission for immediate args
According to nvdisasm both the immediate and non-imm cases use the same
bits. Both of these flags are quite rarely set though.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-07 18:49:28 -05:00
Kenneth Graunke
87a1166310 i965: Add brw_device_info::min_ds_entries field.
From the 3DSTATE_URB_DS documentation:

"Project: IVB, HSW
 If Domain Shader Thread Dispatch is Enabled then the minimum number of
 handles that must be allocated is 10 URB entries."

"Project: BDW+
 If Domain Shader Thread Dispatch is Enabled then the minimum number of
 handles that must be allocated is 34 URB entries."

When the HS is run in SINGLE_PATCH mode (the only mode we support
today), there is no minimum for HS - it's just zero.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:55 -08:00
Chris Forbes
42ca675cc9 i965: Add state bits for tess stages
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:55 -08:00
Chris Forbes
80ea18d1a1 i965: Add backend structures for tess stages
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:55 -08:00
Chris Forbes
5340f37902 i965: Set core tessellation-related limits
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:54 -08:00
Kenneth Graunke
a9e6a56a02 i965: Request lowering of gl_TessLevel* from float[] to vec4s.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:54 -08:00
Kenneth Graunke
7a17356800 i965: Create new files for HS/DS/TE state upload code.
For now, this just splits the existing code to disable these stages into
separate atoms/files.  We can then replace it with real code.

v2: Bump the render atoms in this patch so it compiles (in my branch,
    I'd bumped it in an earlier patch).  61 seems to be the minimum
    that works, which doesn't match the old value + the number of atoms
    I added in this patch, so apparently we had some slop before.

v3: Actually disable the DS unit on Gen8+.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> [v1]
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:54 -08:00
Ilia Mirkin
63b850403c gk104/ir: sampler doesn't matter for txf
We actually leave the sampler unset for OP_TXF, which caused the GK104+
logic to treat some texel fetches as indirect. While this works, it's
incredibly wasteful. This only happened when the texture was > 0 (since
sampler remained == 0).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-07 16:22:54 -05:00
Marek Olšák
32f05fadbb radeonsi: disable DCC on Stoney
Cc: 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-07 22:01:08 +01:00
Sonny Jiang
2618886600 winsys/amdgpu: addrlib - port a Fiji bug fix
Fiji: Fixed tiled resource failures

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

v2: fix a compile failure (typo) - Marek
2015-12-07 21:58:42 +01:00
Sonny Jiang
338d7bf053 winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatible
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-07 21:58:42 +01:00
Sonny Jiang
676bc25140 winsys/amdgpu: addrlib - port fix error for workaround for 1D tiling
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-07 21:58:42 +01:00
Christian König
a2c5200a4b st/va: disable MPEG4 by default v2
The workarounds are too hacky to enable them by default
and otherwise MPEG4 doesn't work reliably.

v2: add docs/envvars.html, CC stable and fix typos

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> (v1)
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1)
Cc: "11.1.0" <mesa-stable@lists.freedesktop.org>
2015-12-07 20:34:17 +01:00
Christian König
ca3e2b76c0 st/va: move HEVC functions into separate file v2
v2: actually copy all of it

Signed-off-by: Christian König <christian.koenig@amd.com>
2015-12-07 20:34:17 +01:00
Alejandro Piñeiro
3d260cc653 mesa: remove _mesa_tex_target_is_array
_mesa_is_array_texture provides the same functionality and:

1. it returns bool instead of GLboolean
2. it's not related to the texture format (texformat.c)
3. the name's a little shorter

v2: remove _mesa_tex_target_is_array instead (Brian Paul)

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-12-07 20:31:20 +01:00
Alejandro Piñeiro
b16e0ff34e i965: use _mesa_is_array_texture instead of _mesa_tex_target_is_array
Both methods provide the same functionality, so one would be
removed.

v2: use _mesa_is_array_texture and not the other way (Brian Paul)

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-12-07 20:30:24 +01:00
Ilia Mirkin
db072d2086 gk110/ir: fix imul hi emission with limm arg
The elemental demo hits this case.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-07 13:30:17 -05:00
Chad Versace
9098e0f074 anv/image: Refactor anv_image_make_surface()
Reduce the number of function parameters. Deduce the
anv_image::*_surface from the parameters instead of requiring the caller
to do that.
2015-12-07 09:28:14 -08:00
Chad Versace
3d85a28e90 anv: Assert the succes of isl_surf_init() 2015-12-07 08:54:59 -08:00
Chad Versace
64e8af69b1 anv: Use isl_tiling_flags in anv_image_create_info
Replace
    anv_image_create_info::force_tiling
    anv_image_create_info::tiling
with the bitmask
    anv_image_create_info::isl_tiling_flags

This allows us to drop the function
anv_image.c:choose_isl_tiling_flags().
2015-12-07 08:50:28 -08:00
Chad Versace
c97d8af9aa anv: Fix anv_gem_set_tiling to respect tiling param
Function anv_gem_set_tiling() ignored its 'tiling' parameter. It
unconditionally set the bo's tiling to I915_TILING_X.
2015-12-07 08:42:11 -08:00
Chad Versace
01e2932d6a anv: Remove unused anv_format_s8_uint
This is no longer needed after migrating to isl.
2015-12-07 08:40:14 -08:00
Brian Paul
32a6e081c3 svga: use the debug callback to report issues to the state tracker
Use the new debug callback hook to report conformance, performance
and fallbacks to the state tracker.  The state tracker, in turn can
report this issues to the user via the GL_ARB_debug_output extension.

More issues can be reported in the future; this is just a start.

v2: remove conditionals around pipe_debug_message() calls since the
check is now done in the macro itself.
v3: remove unneeded dummy %s substitutions

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>,
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2015-12-07 08:57:49 -07:00
Brian Paul
5effc3ae74 gallium/util: check callback pointers for non-null in pipe_debug_message()
So the callers don't have to do it.

v2: also check cb!=NULL in the macro

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2015-12-07 08:56:51 -07:00
Abdiel Janulgue
b19546abf3 i965: Add defines for gather push constants
v2 (Francisco Jerez):
   - Rename HSW_GATHER_CONSTANTS_RESERVED to HSW_GATHER_POOL_ALLOC_MUST_BE_ONE.
   - Rename BRW_GATHER_* prefix to HSW_GATHER_CONSTANT_*.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2015-12-07 14:58:12 +02:00
Timothy Arceri
9214664aed mesa: move GLES checks for SSO input/output validation
This function is unfinished there is a bunch more validation rules
that need to be applied here. We will still want to call it for desktop
GL we just don't want to validate precision so move the ES check to
reflect this.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-12-07 21:41:14 +11:00
Timothy Arceri
ad02621854 mesa: move GL_INVALID_OPERATION error to rendering call
The validation api doesn't trigger this error so just move it to the
code called during rendering.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:41:09 +11:00
Timothy Arceri
4dd096d741 mesa: move pipeline input/output validation inside _mesa_validate_program_pipeline()
This allows validation to be done on rendering calls also.

Fixes 3 dEQP-GLES31.functional.separate tests.

Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:41:05 +11:00
Timothy Arceri
da1a01361b glsl: re-validate program pipeline after sampler change
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
https://bugs.freedesktop.org/show_bug.cgi?id=93180
2015-12-07 21:41:00 +11:00
Dave Airlie
41e82f4f96 r600: apply SIMD workaround to cayman also.
At last on ARUBA this is required to stop tessellation hanging
in heaven.

This removes one of the SIMDs from use by the HS/LS.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 18:57:34 +10:00
Dave Airlie
6bf6bdbc2b r600: fix regression introduced with ring emit changes.
This was adding one after a CUT which broke end primitive
2015-12-07 05:44:55 +00:00
Dave Airlie
fc276bda22 r600: remove stale tessellation comment
pointed out by Marek.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 11:04:48 +10:00
Dave Airlie
5ca9825758 docs: consolidate r600 entry in GL3.txt
Though fp64 emulation still needs to be done for a lot of the evergreen hw.
2015-12-07 10:06:44 +10:00
Dave Airlie
7fa2914b06 docs: update with r600 tessellation status.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:02 +10:00
Dave Airlie
33404f1415 r600: enable tessellation for evergreen/cayman (v2)
This enables tessellation for evergreen/cayman,

This will need changes before committing depending
on what hw works etc.
working are CAYMAN/REDWOOD/BARTS/TURKS/SUMO/CAICOS

v2: only enable on evergreen and above.
2015-12-07 09:59:02 +10:00
Dave Airlie
a2885d9cf9 r600g: reduce number of ps thread on caicos
this allows tess apps to start

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:02 +10:00
Dave Airlie
fe64a0c8bf r600g: adjust ls/hs thread counts for sumo
these stop tess hangs here.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:02 +10:00
Dave Airlie
e7ce9e3bb8 r600/asm: enable nstack check for tess ctrl/eval shaders.
This just makes sure they register at least one stack
usage frame like vertex shaders.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:02 +10:00
Dave Airlie
bb44c1f036 r600/asm: handle lds read operations.
Reads from the queue shouldn't be merged for now read operations.

Reads from the queue shouldn't be merged for now, or put in
T slots.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:02 +10:00
Dave Airlie
8ec2cb13e5 r600/asm: add LDS ops and barrier to the once per group restriction.
LDS ops must be scheduled in X slot, and barrier should be on its
own in a group.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:02 +10:00
Dave Airlie
18871ac576 r600: move VGT_VTX_CNT_EN into shader stages atom.
This should be enabled for tessellation shaders as well.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:02 +10:00
Dave Airlie
958d617d98 r600: enable tcs/tes dumping for R600_DUMP_SHADERS.
Trivial patch just to enable dumping more.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:01 +10:00
Dave Airlie
b8df7d03c8 r600: handle SIMD allocation issue with HS/LS
At least one SIMD must be kept away from the HS/LS
stages in order to avoid a hw issue on evergreen/cayman.

This patch implements this workaround.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:01 +10:00
Dave Airlie
7b5878ee04 r600/shader: increase number of inputs/outputs to 64.
Tessellation exceeds these sometimes, so increase them for now.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:01 +10:00
Edward O'Callaghan
22058f69fb r600: handle barrier opcode.
This handles the barrier opcode for EG/CM.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:01 +10:00
Dave Airlie
9662a43d23 r600/shader: handle tess related system-values.
This adds handling for TESSINNER/TESSOUTER in the TES
where they need to be fetched from LDS,
and TESSCOORD which comes in via r0.

It also handle primitive ID and invocation ID.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:01 +10:00
Dave Airlie
92fbf856f4 r600/shader: allow multi-dimension arrays for tcs/tes inputs/outputs.
This just allows multi-dim arrays to be processed.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:01 +10:00
Dave Airlie
30d56d1c00 r600/shader: handle TES exports and streamout
when tessellation is enabled the TES shader is responsible
for handling streamout and exports.

This adds the streamout and export workarounds to TES,
and also makes sure TES sets up spi_sid.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:01 +10:00
Dave Airlie
2239f3eaff r600/shader: emit tessellation factors to GDS at end of TCS.
When we are finished the shader, we read back all the tess factors
from LDS and write them to special global memory storage using
GDS instructions.

This also handles adding NOP when GDS or ENDLOOP end the TCS.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:01 +10:00
Dave Airlie
cfc2818e23 r600/shader: handle TCS output writing.
TCS outputs whenever they are written in the shader,
need to be written to LDS not temporaries, this handles
this case. It also fixes up the case where the output
is a relative addressed output, so we don't try to apply
the relative address at the wrong time.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:59:01 +10:00